EP1026569B1 - Spannungsregler - Google Patents
Spannungsregler Download PDFInfo
- Publication number
- EP1026569B1 EP1026569B1 EP00101965A EP00101965A EP1026569B1 EP 1026569 B1 EP1026569 B1 EP 1026569B1 EP 00101965 A EP00101965 A EP 00101965A EP 00101965 A EP00101965 A EP 00101965A EP 1026569 B1 EP1026569 B1 EP 1026569B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- interruption
- input
- output
- voltage value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
Definitions
- the invention relates to a voltage regulator, its input is connected to a first supply voltage and its Output voltage at an output in normal operation via a Feedback line an input of an integrated circuit with a circuit block for controlling the actuator is supplied so as to monitor and control the output voltage to a predetermined first voltage value guarantee.
- linear Voltage regulators are, for example, from Tietze, Schenk; Semiconductor circuit technology, 10th edition, Springer-Verlag, 1993, pages 542 to 555.
- Clocked voltage regulators for example in the form of a step-up or step-down converter are in the same reference on pages 563 to 571.
- the object of the present invention is therefore to to provide a voltage regulator of the type described in the introduction, the one condition deviating from normal operation, in particular an interruption in the feedback line from the output recognizes a control and that with the output of the Voltage regulator connected consumers safe from malfunction or protects destruction.
- a circuit arrangement in the voltage regulator to detect a break in the feedback line provided, at the output of the voltage regulator at an interruption of the feedback line from a given one first voltage value to a predetermined second Voltage value is switched.
- The is advantageously Output of the voltage regulator with a mass-related charge storage connected, the one in a first period can store the first quantity of charge, which on the charge storage falling voltage of the control and in normal operation the circuit arrangement for detecting an interruption is fed to the feedback line.
- the circuit arrangement to detect a break in the feedback line is advantageously with its output connected to the control. This ensures that in In the event of an interruption in the feedback line, regulate up the voltage at the output of the voltage regulator prevented can be, so that a malfunction or destruction of the connected Consumer cannot occur.
- the circuit arrangement to detect a break in the feedback line is both in a linear and in a clocked voltage regulator can be used.
- the circuit arrangement for detecting an interruption a predetermined first voltage value in the invention Voltage regulator is such that in the event of an interruption at the input of the circuit arrangement within a second period of time a second smaller, predetermined voltage value than that falling on the charge storage device during normal operation Voltage is present that is within one third period from the time the interruption occurred Reference voltage value each one input of an evaluation is supplied, which is a signal at the output of the circuit arrangement generated, which is fed to the control.
- the advantage of the circuit arrangement according to the invention is in that the actual function of the feedback line is not affected, namely the one at the exit Supply voltage to a control that the output voltage at a constant, predetermined first voltage value holds.
- the second voltage value a series connection from a power source, one Switching device and a resistor between supply potential connections provided, the connection point between the resistor and the switching device on the one hand with the input of the circuit arrangement and on the other hand with is connected to the first input of the evaluation.
- the reference voltage value is advantageously a Series connection of a second current source, a second Circuit device and a charge storage between the Supply potential connections are provided, the connection point between the second charge storage and the second Switching device with the second input of the evaluation is connected and wherein the charge storage is at least one Semiconductor switch connected in parallel with its load path is.
- the voltage caused by impressing a reference current can be established above the second charge store whether there is an interruption in the feedback line or not.
- the first and the second charge storage are dimensioned such that the voltage during normal operation increases significantly more slowly at the input of the circuit arrangement than the voltage across the second charge storage. at an interruption in the feedback line does not determine the first charge store the voltage at the input of the circuit arrangement, but the one immediately falling above the resistance Voltage that is much smaller than that on the first charge storage falling target voltage is.
- the evaluation of the circuit arrangement for detecting a Interruption of a predetermined first voltage value in the voltage regulator according to the invention is such that it has first and a second differential amplifier, their positive inputs with each other and with the input of the Circuitry are connected and the first input of the Form evaluation.
- the negative input of the first differential amplifier is with one between two voltage values switchable device connected.
- the negative input of the second differential amplifier is the connection point between the second charge storage device and the second switching device connected.
- the output of the first differential amplifier controls the first and the second switching device in the event of a fault, on the other hand the second Charge storage semiconductor switches connected in parallel in the Blocking error and is still with a first input a logical logic element connected.
- the Output of the second differential amplifier is with a second Input of the logic logic element connected and the output of the logic logic element with the output the circuit arrangement for detecting an interruption a predetermined first voltage value.
- the second Switching device advantageously has two with their Load path of series-connected semiconductor switches.
- the logic gate is advantageously an AND gate, the first input being inverted.
- the first and the second charge storage are advantageous Capacitors, the storage capacity of the first Charge storage is much larger than the storage capacity of the second charge storage is.
- the circuit arrangement in the voltage regulator according to the invention has the advantageous property that an error in the feedback line from a startup of the voltage regulator can be distinguished. Under a ramp-up of the Voltage regulator is to be understood here that at the input of the Voltage regulator for the first time different from zero Voltage is applied so that the voltage regulator at the output tries to reach the specified setpoint voltage. On Undefined changing of the status output is prevented that is, it can be determined beyond any doubt whether a There is an error or not. Otherwise the status output points the circuit arrangement on a signal which the control or the correct one via a signal device Functionality of the voltage regulator indicates. Because of the special Design of the circuit arrangement is still achieved that this only has a low power consumption in normal operation has because the power sources through the special How the evaluation works can be switched off.
- FIG. 1 shows the basic structure of an inventive clocked voltage regulator
- the voltage regulator SR1 is designed in the form of a step-down converter.
- the voltage regulator will IN at its input, which at the same time represents a first supply potential connection 1 with a generally positive supply voltage Vbb.
- the voltage regulator SR1 contains a semiconductor switch S1, which can be designed, for example, as a MOSFET can. However, it is also any other controllable switch conceivable.
- the semiconductor switch S1 is with its drain connected to the input IN, while its source terminal S with the cathode connection of one connected to reference potential Diode D1 is connected.
- the reference potential GND provides at the same time a second supply potential connection 2 Furthermore, with the source terminal S of the semiconductor switch S1 connected to a terminal of an inductor whose another connection is connected to the output OUT and is connected to a charge storage LS, which is against reference potential is connected.
- the charge storage LS is as Capacitor executed, which has a capacitance C1.
- the Voltage regulator on a feedback line RL on the one hand with the output OUT and on the other hand with the input IN1 one integrated circuit IC is connected.
- the integrated Circuit IC has a control AN, which depends on the output voltage Ua the clock frequency of the gate G des Semiconductor switch S1 controls.
- the integrated circuit is continue with the input IN and the reference potential GND connected.
- the integrated circuit IC also has one Circuit arrangement SDU for detecting an interruption the feedback line RL.
- the circuit arrangement is SDU therefore also via the input IN1 with the feedback line RL connected.
- It also has an output ST, which is connected on the one hand to the control AN in order to switch off the voltage regulator in the event of a defect can.
- the output ST is the circuit arrangement SDU led out of the integrated circuit IC.
- the clocked voltage regulator SR1 could also be used as a step-up converter or designed as a linear voltage regulator his.
- FIG. 2 shows the essential element of the invention Voltage regulator, namely the circuit arrangement SDU for detection an interruption in the feedback line.
- the Circuit arrangement SDU together with the control of the Switch S1 integrated monolithically on the integrated Circuit IC are present.
- the circuit arrangement SDU has one Input IN1 to which the output voltage is in normal operation One of them is via the feedback line RL.
- the entrance IN1 of the circuit arrangement SDU is with a first Input 51 of an evaluation 5 connected.
- one Series connection from a first current source 3, a semiconductor switch M2 and a resistor R are provided with a first supply potential connection 1, at which usually the supply voltage Vbb or one of them derived voltage is present, and a second supply potential connection 2, which represents the reference potential, connected is.
- the semiconductor switch M2 is in the present Example as a p-channel enhancement MOSFET, it could however, for example, a bipolar transistor or any one controllable switch can be used.
- the connection point 7 between the resistor R and the drain connection of the semiconductor switch M2 is connected to the input IN1 of the circuit arrangement SDU connected.
- the circuit arrangement SDU has a further series connection from a second current source 4, two semiconductor switches M1 and M3 whose load paths are connected together in series, as well as a capacitor C on. This series connection is again between the first 1 and the second supply potential connection 2 located.
- the first supply potential connection 1 is here in each case with the first or with the second current source 4 in connection.
- the charge storage C are two more Semiconductor switches M4 and M5 with their load path in parallel connected.
- the semiconductor switches M1 and M3 are as p-channel enhancement MOSFETs run while the semiconductor switch M4 and M5 are n-channel enhancement MOSFETs. Also could replace the semiconductor switches M1, M3, M4 and M5 any controllable switch occur.
- the connection point 8 between the capacitor C and the drain of Semiconductor switch M3 is a voltage source 6, the provides the preset voltage V3 with a second Input 52 of evaluation 5 connected.
- the evaluation 5 comprises a first 53 and a second Differential amplifier 54, their positive inputs to each other are connected. These are in turn with the first Input 51 and thus with input IN1 of the circuit arrangement SDU in connection.
- the first differential amplifier 53 is advantageously carried out with input hysteresis, the means at its negative input two are different large, positive voltages V1 or V2 applied. For example, two separate voltage sources can be used for this purpose V1 or V2 can be provided for generation.
- the second input 52 of evaluation 5 is directly connected to the negative input of the second differential amplifier 54.
- Evaluation 5 also has a logical link element 55, which is designed as an AND gate. This has an inverting input, which with is connected to the output of the first differential amplifier 53.
- the non-inverting, second input stands with the output of the second differential amplifier 54 in connection.
- the exit ST of the logic logic element 55 provides at the same time represents the output ST of the circuit arrangement SDU Output of the first differential amplifier 53 is still with the gate connections of the semiconductor switches M2, M3 and M4 connected.
- the output ST of the logic logic element 55 which normally assumes a logic low level or but assumes a logic high level in the event of an error the gate of the semiconductor switches M1 and M5.
- the current sources 3 and 4, the capacitor C and the voltage sources V1, V2 and V3 are dimensioned such that the voltage at the input node IN1 normally, that is to say with a correctly connected external capacitor LS, increases significantly more slowly than the voltage across the capacitor C.
- the following dimensions are provided for this: V2 ⁇ V3 ⁇ I1 * R ⁇ V1 ⁇ V IN1, target ,
- This dimensioning means that the output of the second differential amplifier 54 in the normal case at the output Logical L delivers and thus also the output ST with a logic L signals the correct functioning of the voltage regulator.
- the diagnosis of an open circuit in the feedback line RL is present, is usually canceled as soon as the voltage at input IN1 via reference voltage V1 has risen.
- the first differential amplifier changes 53 from a logical L to a logical H, see above that the current sources 3 and 4 using the semiconductor switch M2 and M3 can be switched off.
- the contained in the capacitor C. Charge is released by closing the semiconductor switch M4 discharged.
- the voltage at input IN1 immediately changes to a voltage value UR, which is obtained from the product of current I1 and resistance R, due to the lack of an external charge store LS.
- the second differential amplifier 54 changes from its logic level to a logic H at its output, while the state of the first differential amplifier 53 remains unchanged at a logic L level.
- the output ST also changes from a logic L to a logic H, so that an error is signaled. If the circuit arrangement SDU is connected to the control AN, the voltage regulator can, for. B. be switched off immediately.
- the first differential amplifier 53 which is advantageously designed as a Schmitt trigger, is designed to suppress transient interference signals with a large hysteresis, that is to say: V1 - V2> I1 * R.
- Figures 3a to 3c show the Voltage values present at input IN1 as well as the logical ones Signal values of the two differential amplifiers 53 and 54 and the Switching states of the semiconductor switches M1 to M5.
- Figure 3a illustrates the operation of the circuit arrangement SDU during startup of the voltage regulator and during operation of the voltage regulator in normal operation.
- the voltage regulator is switched on at time t ⁇ .
- both differential amplifiers In front when the time t ⁇ is reached, both differential amplifiers have 53 and 54 a logic L at the output. hereby the semiconductor switches M1 and M3 are switched to conditional, while the semiconductor switches M4 and M5 lock.
- the logic L of the first differential amplifier 53 is inverted, so that at the output ST of the logic logic element there is a logical L This in turn means that the semiconductor switch M1 is turned on.
- the first supply potential connection is made 1 the supply voltage Vbb is applied.
- the ramp-up of the voltage regulator begins, i.e. the voltage at the input IN1, which is connected to the output via the feedback line RL OUT of the voltage regulator is connected starts continuously to rise to a value of ULS.
- the tension value ULS is specified by the control loop.
- the states of the individual components change Not.
- the voltage present at input IN1 is voltage value V1. This has the consequence that the output of the first differential amplifier 53 changes from a logical L to a logical H.
- the semiconductor switches M2 and M3 are thereby blocked switched, that is, the further current flow through the resistor R or a further increase in voltage at connection point 8 is prevented.
- the Semiconductor switch M4 turned on, so that in the Charge storage C can drain stored charge and itself sets a voltage of 0 V at connection point 8. M5 remains unchanged in the locked state.
- Figure 3b shows the operation of the voltage regulator according to the invention in the event of a run-up, if the feedback line is interrupted.
- the run-up begins at time t ⁇ .
- the differential amplifiers 53 and 54 instruct a logical L on their outputs.
- the semiconductor switches M2 and M3 are switched on while the semiconductor switches Lock M4 and M5.
- the status output ST points to A logical L also appears at time t '.
- the semiconductor switch M1 is therefore switched on.
- the first supply potential connection is located 1 the positive supply voltage Vbb, that is ramp-up begins. Because the external charge storage LS due the interruption of the feedback line RL the input IN1 is connected by the current source 3 a voltage across the closed switch M2 in the resistor R. UR stamped on the input IN1 and thus on the first Input 51 of the evaluation is pending. This tension is instant to disposal. The voltage UR dropping across the resistor is larger in magnitude than the voltages V2, the negative ones Input of the first differential amplifier 53 is present and greater than V3, that at the negative input of the second differential amplifier 54 is present.
- an advantage of Circuit arrangement SDU according to the invention is that an error in the feedback line RL from a startup of the Voltage regulator can be distinguished.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Dc-Dc Converters (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
- Figur 1
- ein erfindungsgemäßer getakteter Spannungsregler in Form eines Abwärtswandlers,
- Figur 2
- die erfindungsgemäße Schaltungsanordnung zum Detektieren einer Unterbrechung der Rückkoppelleitung,
- Figur 3a
- die Arbeitsweise der Schaltungsanordnung beim Hochlaufen des Spannungsreglers sowie während eines Betriebes des Spannungsreglers im Normalbetrieb,
- Figur 3b
- die Arbeitsweise der Schaltungsanordnung des Spannungsreglers, wenn beim Hochlauf ein Fehler auftritt und
- Figur 3c
- die Arbeitsweise der Schaltungsanordnung des Spannungsreglers beim Auftreten eines Fehlers während des Betriebes des Spannungsreglers.
- IN
- Eingang Spannungsregler
- OUT
- Ausgang Spannungsregler
- LS
- Ladungsspeicher
- ULS
- Ausgangsspannung
- t1
- Zeitspanne
- RL
- Rückkoppelleitung
- IC
- integrierte Schaltung
- IN1
- Eingang integrierte Schaltung
- AN
- Ansteuerung
- SDU
- Schaltungsanordnung zum Detektieren einer Unterbrechung in der Rückkoppelleitung
- Vbb
- positives Versorgungspotential
- GND
- Bezugspotential/Masse
- SR1
- Spannungsregler
- S1
- Halbleiterschalter (MOSFET)
- D1
- Diode
- L1
- Induktivität
- 1
- erster Versorgungspotentialanschluß
- 2
- zweiter Versorgungspotentialanschluß
- 3
- erste Stromquelle
- 4
- zweite Stromquelle
- 5
- Auswertung
- 6
- Spannungsquelle
- 7
- Verbindungspunkt
- 8
- Verbindungspunkt
- 51
- erster Eingang
- 52
- zweiter Eingang
- 53
- erster Differenzverstärker
- 54
- zweiter Differenzverstärker
- 55
- logisches Verknüpfungselement
- 56
- Verbindungspunkt
- M1
- Halbleiterschalter (zweite Schaltvorrichtung)
- M3
- Halbleiterschalter (zweite Schaltvorrichtung)
- M2
- Halbleiterschalter (erste Schaltvorrichtung)
- M4
- Halbleiterschalter (erste Schaltvorrichtung)
- M5
- Halbleiterschalter
- R
- Widerstand
- UR
- Spannung (an R)
- ST
- Ausgang von SDU
- C
- Ladungsspeicher
Claims (14)
- Spannungsregler (SR1), dessen Eingang (IN) mit einer ersten Versorgungsspannung (Vbb) verbunden ist und dessen Ausgangsspannung (Ua) an einem Ausgang (OUT) im Normalbetrieb über eine Rückkoppelleitung (RL) einem Eingang (IN1) einer integrierten Schaltung (IC) mit einer Ansteuerung (AN) zugeführt wird zur Überwachung und Regelung der Ausgangsspannung (Ua) auf einen vorgegebenen ersten Spannungswert durch die Ansteuerung (AN) ,
dadurch gekennzeichnet, daß eine Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung der Rückkoppelleitung (RL) vorgesehen ist und, daß am Ausgang (OUT) bei einer Unterbrechung von dem vorgegebenen ersten Spannungswert auf einen vorgegebenen zweiten Spannungswert umgeschaltet wird. - Spannungsregler nach Patentanspruch 1,
dadurch gekennzeichnet, daß der Ausgang (OUT) mit einem massebezogenen, ersten Ladungsspeicher (LS) verbunden ist, wobei die an dem Ladungsspeicher (LS) abfallende Spannung (ULS) im Normalbetrieb der Ansteuerung und der Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung der Rückkoppelleitung (RL) zugeführt wird. - Spannungsregler nach Patentanspruch 1 oder 2,
dadurch gekennzeichnet, daß die Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung der Rückkoppelleitung (RL) mit ihrem Ausgang (ST) mit der Ansteuerung (AN) verbunden ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 1 bis 3,
dadurch gekennzeichnet, daß im Falle einer Unterbrechung am Eingang (IN1) innerhalb einer zweiten Zeitspanne (t2) ein zweiter kleinerer, vorgegebener Spannungswert (UR) als die im Normalbetrieb abfallende Spannung (ULS) anliegt, der mit einem innerhalb einer dritten Zeitspanne (t3) ab dem Eintreten der Unterbrechung erzeugten Referenzspannungswert (Uref) jeweils einem Eingang (51,52) einer Auswertung (5) zugeführt wird, die ein Signal am Ausgang (ST) erzeugt, das der Auswertung (AN) zugeführt wird. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach Patentanspruch 4,
dadurch gekennzeichnet, daß zur Erzeugung des zweiten Spannungswertes (UR) zwischen Versorgungspotentialanschlüssen (Vbb, GND) eine Serienschaltung aus einer ersten Stromquelle (3), einer ersten Schaltvorrichtung (M2) und einem Widerstand (R) vorgesehen ist, wobei der Verbindungspunkt (7) zwischen dem Widerstand (R) und der ersten Schaltungsvorrichtung (M2) einerseits mit dem Eingang (IN1) und andererseits mit dem ersten Eingang (51) der Auswertung (5) verschalten ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 4 oder 5,
dadurch gekennzeichnet, daß zur Erzeugung des Referenzspannungswertes (Uref) eine Serienschaltung aus einer zweiten Stromquelle (4), einer zweiten Schaltungsvorrichtung (M1, M3) und einem zweiten Ladungsspeicher (C) zwischen den Versorgungspotentialanschlüssen (Vbb, GND) vorgesehen ist, wobei der Verbindungspunkt zwischen dem zweiten Ladungsspeicher (C) und der zweiten Schaltvorrichtung (M1, M3) mit dem zweiten Eingang (52) der Auswertung (5) verschalten ist und wobei dem Ladungsspeicher (C) zumindest ein Halbleiterschalter (M4, M5) mit seiner Laststrecke parallel geschalten ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach Patentanspruch 6,
dadurch gekennzeichnet, daß die zweite Schaltvorrichtung (M1, M3) zwei mit ihrer Laststrecke seriell verschaltete Halbleiterschalter aufweist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 4 bis 7,
dadurch gekennzeichnet, daß die Auswertung einen ersten (53) und einen zweiten Differenzverstärker (54) aufweist, deren positive Eingänge miteinander und mit dem Eingang (IN1) verbunden sind und den ersten Eingang der Auswertung bilden,
daß der negative Eingang des ersten Differenzverstärkers (53) mit einer zwei Spannungswerten (V1, V2) bereitstellende Vorrichtung verbunden ist und
daß der negative Eingang des zweiten Differenzverstärkers (54) mit dem Verbindungspunkt zwischen dem zweiten Ladungsspeicher (C) und der zweiten Schaltvorrichtung (M1, M3) verbunden ist,
wobei der Ausgang des ersten Differenzverstärkers (53) einerseits die erste (M2) und die zweite Schaltvorrichtung (M3) im Fehlerfall leitend steuert, andererseits den Halbleiterschalter (M4) im Fehlerfall sperrend schaltet und weiterhin mit einem ersten Eingang eines logischen Verknüpfungsgliedes verbunden ist
und wobei der Ausgang des zweiten Differenzverstärker (54) mit einem zweiten Eingang des logischen Verknüpfungsgliedes (55) verbunden ist und der Ausgang des logischen Verknüpfungsgliedes (55) mit dem Ausgang (ST) in Verbindung ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach Patentanspruch 8,
dadurch gekennzeichnet, daß der Ausgang (ST) des logischen Verknüpfungsgliedes (55) im Fehlerfall die zweite Schaltvorrichtung (M1) sperrend und den Halbleiterschalter (M5) leitend schaltet. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 8 oder 9,
dadurch gekennzeichnet, daß der erste Eingang des logischen Verknüpfungsgliedes (55) invertierend ist und das logische Verknüpfungsglied (55) ansonsten ein UND-Gatter ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 6 bis 10,
dadurch gekennzeichnet, daß der erste Ladungsspeicher (LS) und der zweite Ladungsspeicher (C) Kondensatoren sind, wobei die Kapazität (C1) des ersten Ladungsspeichers (LS) größer als Kapazität (C2) des zweiten Ladungsspeichers (C) ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 8 bis 11,
dadurch gekennzeichnet, daß zwischen den negativen Eingang des zweiten Differenzverstärkers (54) und den Ladungsspeicher (C) eine Spannungsquelle (6) geschalten ist. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 8 bis 12,
dadurch gekennzeichnet, daß über ein externes Signal ( ) die Schaltungsanordnung in den Stand-by-Betrieb geschalten werden kann. - Schaltungsanordnung (SDU) zum Detektieren einer Unterbrechung eines vorgegebenen ersten Spannungswertes nach einem der Patentansprüche 8 bis 13,
dadurch gekennzeichnet, daß der erste Differenzverstärker (53) als Schmitt-Trigger ausgeführt ist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19904344 | 1999-02-03 | ||
DE19904344A DE19904344A1 (de) | 1999-02-03 | 1999-02-03 | Spannungsregler |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1026569A1 EP1026569A1 (de) | 2000-08-09 |
EP1026569B1 true EP1026569B1 (de) | 2003-09-24 |
Family
ID=7896301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00101965A Expired - Lifetime EP1026569B1 (de) | 1999-02-03 | 2000-02-01 | Spannungsregler |
Country Status (3)
Country | Link |
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US (1) | US6150804A (de) |
EP (1) | EP1026569B1 (de) |
DE (2) | DE19904344A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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US6304067B1 (en) * | 2000-12-08 | 2001-10-16 | Micrel, Incorporated | Adding a laplace transform zero to a linear integrated circuit for frequency stability |
US6424132B1 (en) | 2000-12-08 | 2002-07-23 | Micrel, Incorporated | Adding a laplace transform zero to a linear integrated circuit for frequency stability |
FR2818761B1 (fr) * | 2000-12-27 | 2003-03-21 | St Microelectronics Sa | Dispositif et procede de regulation de tension |
JP2002312043A (ja) * | 2001-04-10 | 2002-10-25 | Ricoh Co Ltd | ボルテージレギュレータ |
US7062647B2 (en) * | 2002-05-31 | 2006-06-13 | Intel Corporation | Method and apparatus for reducing the power consumed by a computer system |
US6737841B2 (en) | 2002-07-31 | 2004-05-18 | Micrel, Inc. | Amplifier circuit for adding a laplace transform zero in a linear integrated circuit |
US6724257B2 (en) | 2002-07-31 | 2004-04-20 | Micrel, Inc. | Error amplifier circuit |
US6861830B1 (en) * | 2003-10-22 | 2005-03-01 | Aimtron Technology Corp. | Method of improving transient noise of a switching DC-to-DC converter with multiple output voltages |
EP3914482B1 (de) * | 2019-01-24 | 2023-04-12 | Elmos Semiconductor SE | Verfahren und vorrichtung zur regelung der elektrischen spannung für eine sicherheitsrelevante last |
CN110021258B (zh) * | 2019-04-23 | 2023-06-02 | 京东方科技集团股份有限公司 | 一种信号转换电路和方法,以及驱动电路和显示装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823070A (en) * | 1986-11-18 | 1989-04-18 | Linear Technology Corporation | Switching voltage regulator circuit |
US5220272A (en) * | 1990-09-10 | 1993-06-15 | Linear Technology Corporation | Switching regulator with asymmetrical feedback amplifier and method |
DE4224243C1 (de) * | 1992-07-22 | 1994-01-05 | Siemens Ag | Schaltungsanordnung zur Lastaufschaltung und Lastüberwachung |
US5894243A (en) * | 1996-12-11 | 1999-04-13 | Micro Linear Corporation | Three-pin buck and four-pin boost converter having open loop output voltage control |
TW357944U (en) * | 1997-03-24 | 1999-05-01 | Advance Reality Technology Inc | Wave width controller |
FR2764450B1 (fr) * | 1997-06-04 | 1999-08-27 | Sgs Thomson Microelectronics | Systeme de fourniture d'une tension regulee |
-
1999
- 1999-02-03 DE DE19904344A patent/DE19904344A1/de not_active Withdrawn
-
2000
- 2000-02-01 DE DE50003777T patent/DE50003777D1/de not_active Expired - Lifetime
- 2000-02-01 US US09/495,713 patent/US6150804A/en not_active Expired - Lifetime
- 2000-02-01 EP EP00101965A patent/EP1026569B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE50003777D1 (de) | 2003-10-30 |
US6150804A (en) | 2000-11-21 |
EP1026569A1 (de) | 2000-08-09 |
DE19904344A1 (de) | 2000-08-31 |
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