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EP0972336B1 - Funksystem und -verfahren mit fet-mischer und rechteckspannungsgetriebener schalterschaltung - Google Patents

Funksystem und -verfahren mit fet-mischer und rechteckspannungsgetriebener schalterschaltung Download PDF

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Publication number
EP0972336B1
EP0972336B1 EP99905547A EP99905547A EP0972336B1 EP 0972336 B1 EP0972336 B1 EP 0972336B1 EP 99905547 A EP99905547 A EP 99905547A EP 99905547 A EP99905547 A EP 99905547A EP 0972336 B1 EP0972336 B1 EP 0972336B1
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Prior art keywords
signal
radio
frequency
mixer
circuit
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French (fr)
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EP0972336A1 (de
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Michael Wendell Vice
Charles Edward Dexter
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DRS Signal Solutions Inc
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DRS Signal Solutions Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements

Definitions

  • the invention relates generally to frequency conversion systems, devices, and methods, and more specifically to radio frequency communication devices and systems including, mixers, radio tuners, transmitter, and receivers incorporating FET mixer type frequency conversion devices for up- and down- frequency conversion.
  • the document EP-A-0 789 449 discloses a FET mixer.
  • a heterodyne receiver down convert a radio-frequency (RF) signal to a baseband signal using one or more intermediate stages in which the RF signal is converted to one or more intermediate-frequency signals, lower than the RF signal, until the base-band frequency is reached.
  • a heterodyne transmitter generates a higher frequency RF signal from a baseband signal using one or more intermediate stages to up-convert the frequency.
  • a transmitter provides both transmit and receive components and function.
  • a homodyne receiver directly down-converts radio-frequency (RF) signals to baseband frequency without intermediate stages.
  • a homodyne transmitter up-converts from base-band to RF without intermediate stages.
  • a radio system may include homodyne and heterodyne components.
  • the term system may be used when referring to any or a combination of such stage, tuner, receiver, transmitter, or transceiver, so as to simplify the description.
  • DSP Digital Signal Processing
  • This additional DSP task undesirably requires a higher clock rate than would otherwise be required for a given bandwidth.
  • Wider signal bandwidth may typically need a processor clock rate that is from about 10 times to about 20 times or more the clock rate required without compensation, in order to compensate phase and amplitude errors over the entire receiver bandwidth of interest. The higher clock rate presents additional problems in itself.
  • Digital compensation after digitization reduce the wanted spectrum bandwidth. Without compensation, homodyne receivers or direct conversion receivers employing mixers are limited to around 40 dB of dynamic range and bandwidth in the audio frequency range.
  • An additional problem with conventional wireless (radio) communication systems pertains to frequent requirements for skilled radio operators to initiate and maintain contact between multiple radio stations or transceivers. This problem is particularly acute because of the need to monitor or provide surveillance over a large HF/VHF/UHF frequency spectrum. Both commercial and non-commercial communicators have been working to achieve automatic, reliable and robust communications using the HF/VHF/UHF spectrum, particularly the HF spectrum. One goal of this work has been an attempt to eliminate or reduce the need for highly skilled radio operators while simultaneously increasing the reliability of the HF spectrum as a communication medium.
  • ALE Automatic Link Establishment
  • ALE is defined as the capability of an HF radio station to make contact between itself and another station or stations under automatic processor control.
  • ALE techniques include automatic signaling, selective calling, and automatic handshaking at different bands in the HF spectrum. Monitoring and following all these activities requires a near simultaneous full band HF receiver. Digitizing the entire HF frequency band, and handling ALE protocol with Digital Signal Processing (DSP) presents many challenges. For example, if the monitoring sites are not ideal in location, dynamic range, resulting from near by transmitters masking far away ALE signals, presents a problem. It has been estimated that an adaptive HF monitoring solution requires full simultaneous HF coverage with 100 dB of Spur Free Dynamic Range (SFDR). The cost for implementing and deploying such ALE systems also remains problematic.
  • DSP Digital Signal Processing
  • ADCs analog-to-digital converters
  • sensitivity sensitivity
  • SFDR Spur Free Dynamic Range
  • MSPS 65 mega samples per second
  • SFDR narrower bandwidth
  • ADCs for example, bandwidths less than about 10 Mhz
  • Frequency conversion or mixer stages in conventional RF systems have been heretofore been unable to attain the approximately 85-100 dB Spur-Free Dynamic Range required in certain tuner/receiver systems, particularly where the output of that mixer stage was intended as the input to high performance Analog-to-Digital Converters (ADCs) where the 100 dB SPRD is required at the input. In fact such systems have been limited to substantially lower performance.
  • ADCs Analog-to-Digital Converters
  • the last or final mixer stage just prior to output to the ADC (baseband frequency converter stage) typically has the highest signal amplitude level in the tuner.
  • a state-of-the-art ADC requires about a 2 volt peak-to-peak signal for full ADC conversion scale, and should have all spurious signal products down by about 100 dB in order to utilize the capabilities of the ADC without introducing other undesirable artifacts.
  • These ADC performance specifications correspond to a baseband spectrum mixer stage coupled to the ADC input terminals having an input third order intercept point (IP3) of about +50 dBm and an input second order intercept point (IP2) of about +100 dBm.
  • Another problem in conventional tuners is that they typically perform the final stage mixing to baseband at a low Intermediate Frequency (IF) signal amplitude level, and then boost the amplitude of the final stage mixer output with a separate power amplifier to achieve the desired ADC signal level (typically in the range of from about 1 Volt to about 4 Volts peak-to-peak).
  • This baseband conversion approach only achieves approximately +43 dBm IP3 and + 82 dBm IP2 into the ADC, may have unacceptable levels of distortion, and typically may not provide performance levels that keep with evolving state-of-the-art ADC dynamic range capability, or that meet the needs the end user.
  • the first conversion stage of a tuner also significantly affects overall dynamic range, in fact so much so that degradation in the first stage may make it impossible to meet overall system performance requirements. For example, if the first mixing operation is too lossy, there may be an added requirement for a preamplifier gain stage in the signal path to boost the signal amplitude in an attempt to achieve the required sensitivity. However, such a preamplifier gain stage in the signal path upstream from the mixer circuit undesirably increases the required IP3 and IP2 of the mixer by an amount equal to the added preamplifier gain. Therefore, any system requirement for a preamplifier gain stage to increase sensitivity imposes even more sever constraints on other radio system components. Desirably, a mixer would have very low conversion loss in the first stage to avoid the need for any preamplification, and also have a high or large dynamic range.
  • the invention includes a wireless communication structure, device, and system and method for operating the same, a mixing structure for use with the wireless communication device or for use otherwise and a method of mixing signals, as well as an inventive differential square wave mixer switching circuit and method for controlling the mixer device which may be used with the inventive mixing device and wireless communication device.
  • the inventive mixer structure and method include an overall mixer architecture topology and several embodiments of the mixer structure which present variations particularly suitable for use in a radio receivers, transmitters, tuners, as well as instrumentation systems, and other systems and devices performing frequency conversion.
  • the inventive mixer is applicable to homodyne and heterodyne receiver/transmitter/tuner implementations, instrumentation and telemetry systems.
  • the invention also provides structural and methodological components of the mixer including a precise mixer device with its LO phase splitter, and differential square wave gate drive.
  • Wireless communication devices includes radios, cellular telephones, and telemetry systems whether land, sea, airborne, or space based, and whether fixed or mobile.
  • the inventive mixer device is advantageously a GaAs FET mixer where the FETs are implemented on a common substrate.
  • the inventive mixer has superior intermodulation and harmonic distortion suppression and features excellent conversion loss, noise figure, port match, and port isolation as a result of its topology.
  • the mixer device circuit combines the advantages of series mixing FETs, a triple balanced design using a balanced passive reflection transformer, a very precise LO phase splitter, and square wave gate drive to achieve its high levels of performance. It is power conservative and offers the advantage of long battery life in portable devices such as portable radios and cellular telephones as it requires only a modest amount of DC and LO drive power, and is useful for operation over at least a multi-decade bandwidth.
  • the invention provides a high-performance mixing device that achieves a high IP2 and IP3.
  • the invention provides a mixer device which is energy conservative, power efficient, and which therefore provides size, weight, and operational life for mobile and/or portable hand-held implementations.
  • the invention provides a mixer having a large dynamic range and very low distortion.
  • the invention provides a differential square wave drive circuit for use with a mixer.
  • the invention provides a mixer generating, at most, very low spurious signal withing the frequency band of interest.
  • the invention provides a mixer generating an analog output signal that does not exceed the input specifications for 14-bit and higher bit analog-to-digital converters.
  • the invention provides a mixer that minimizes amplitude and phase imbalances, such as imbalances contributed by an imperfect quadrature modulator local oscillator frequency signal.
  • the invention provides a mixer that meets or exceeds the input requirements of high-bit (e.g. 12-bit, 14-bit, 16-bit) analog-to-digital converters (ADCs) so as to provide a radio in which the mixer is employed where the RF spectrum may be moved down to baseband frequencies, while maintaining high sensitivity and low distortion, where the spectrum may be digitized by the ADCs and processed under software control.
  • high-bit e.g. 12-bit, 14-bit, 16-bit
  • ADCs analog-to-digital converters
  • the invention provides a high-performance direct conversion system.
  • the invention provides a radio, tuner, receiver, and/or transmitter, or components thereof in which about 100 dB or greater of Spur Free Dynamic Range is provided over a sufficiently large spectral bandwidth meeting the needs of an Automatic Link Establishment (ALE) or adaptive HF, VHF, and/or UHF system.
  • ALE Automatic Link Establishment
  • the invention provides a method for mixing signals to provide a high performance mixer achieving hgh SPDR, large bandwidth, low distortion, and low power consumption in a wireless communication system.
  • FIG. 1 there is shown an overview of several aspects and embodiments of the inventive structure and corresponding inventive method.
  • an exemplary down-frequency conversion embodiment of a homodyne structure such as may be used in a radio system is shown in which each of two of the inventive mixer devices 32a, 32b (also referred to as "super-mixer” devices) receive an RF signal, and super-mixer control (switching) signals at a control (switching) port, which control signals are derived from a conventional externally applied sinusoidal LO signal but which have special properties described in greater detail hereinafter.
  • the in-phase (I) channel and quadrature-phase (Q) channel signals output by each super-mixer 32a, 32b are coupled directly to separate ADC 27a, 27b, without the need for any intervening amplifier.
  • the ADCs (advantageously having at least 14-bit resolution) digitize each of the I and Q channels so that subsequent conventional down stream processing may be accomplished.
  • DSP Digital Signal Processor
  • an exemplary down-frequency conversion embodiment of a heterodyne structure such as also may be used in a radio system is shown in which one of the inventive mixer devices 32 ("super-mixer" device 32) receives an RF signal, and a super-mixer control (switching) signal at a control (switching) port, which control signal is derived from a conventional externally applied sinusoidal LO signal but which has special properties as alluded to relative to FIG. 1a.
  • the IF output signal from the super-mixer 32 is coupled directly to an ADC 27, without the need for any intervening post-mixing device amplifier.
  • the ADC digitizes the IF output signal so that subsequent conventional down stream processing may be accomplished as described herein before.
  • the circuit topologies shown and described relative to FIG. 1a and FIG. 1b are different, yet each includes at least one of the inventive super-mixers among the elements.
  • FIG. 1c shows some of the significant features of the inventive super-mixer 32, 32a, 32b.
  • the super-mixer 32 is configured with and coupled to an RF/IF separation/filter circuit 33 (such as a balun) to operate as a passive reflection FET mixer wherein (when operating as a down-converter) RF energy is input to the RF/IF separation circuit at an RF port 34, and the IF output signal generated at the dual FET mixing devices 36a, 36b in a manner described hereinafter, is separated from the RF signal by the separation circuit at IF port 35.
  • RF/IF separation/filter circuit 33 such as a balun
  • a FET drive circuit 37 which is advantageously implemented as a "floating" or differential drive circuit.
  • An externally generated (nominally) sinusoidal LO signal is input to a phase splitter circuit 38, which generates a phase complementary (180 degree phase difference) between two sets of differential nominally sinusoidal signals at the LO frequency.
  • the LO signal is nominally sinusoidal, because some variation from true sinusoid may be tolerated as the sinusoid is used to generate or regenerate a very high slew rate signal such as a square wave or substantially square wave which actually controls the FET gates to cause the desired FET switching. Therefore, any input signal to the complementary square wave generation circuits 40a, 40b that provides a suitable high slew rate signal to the mixing devices 36a, 36b may be used as the LO input.
  • the sinusoidal LO signal is split into two complementary phases and then coupled to ground isolation circuits 39a, 39b associated with each of the complementary signals paths. These ground isolated or floating phase complementary signal pairs are then coupled to a pair of square wave generation circuits 40a, 40b, the outputs of which are signals having high slew-rate leading and trailing edges, such as square waves.
  • the square wave generation circuits comprise digital logic gates, such as "AND" gates, which provide a nearly perfect square wave output with two levels, very high slew-rate leading and trailing edges, and extremely low cost per device.
  • the inventive receiver incorporates a mixer device advantageously implemented triple-balanced passive reflection FET mixing devices as in GaAs on a single monolithic substrate, and a FET switch drive circuit (LO drive circuit) that provides near ideal switching.
  • LO drive circuit FET switch drive circuit
  • the triple-balanced passive reflection FET mixer 32 has a square wave (or near square wave) switching waveform derived or regenerated from a sinusoidal local oscillator waveform, and operates in the LO/RF/IF frequency range of from about 1 Mhz to about 200 Mhz with reduced levels of nonlinearity and intermodulation distortion compared to conventional mixers as the result of the topological structure, the application of a DC bias to the FET channels, and other factors.
  • Other embodiments of the mixer are described which extend the range of operation from 200 Mhz to tens of Ghz.
  • the mixer 32 is useful for both up- and down-frequency conversion of RF and IF signal frequencies, through characterization as RF and IF for the primary radio receiver application are arbitrary, and various alternative embodiments have features that are advantageously implemented to optimize up-frequency conversion and down-frequency conversion respectively.
  • the LO drive signal is operable within the range of from about 1 Mhz to about 200 Mhz; the RF signal is operable within the range of from about 1 Mhz to about 200 Mhz; and the IF signal is similarly operable within the range of from about 1 Mhz to about 200 Mhz.
  • the RF, IF, and LO signal frequencies may therefore overlap so that there is no frequency exclusion.
  • the inventive mixer 32 structure and method addresses this need for an ultra high dynamic range mixer by providing superior second and third order intercept point and compression point performance without the degradation of other mixer performance parameters, such as the conversion loss, noise figure, port isolation, and power consumption. Furthermore, the conventional need for relatively high Local Oscillator (LO) drive levels, that is LO drive levels above about one (1) Watt at the external LO input, when specifying input third order intercept points (IIP3) in the +45 dBm range, is eliminated by the LO waveform regeneration circuit of the inventive mixer. In the inventive mixer 32 LO drive, measured at the external LO input port, the inventive structure needs only about 100 milliwatts for comparable or even superior performance. Dynamic range refers to noise characteristics and conversion linearity, and the way the two characteristics combine to produce dynamic range and the useful power level over which one can operate the mixer.
  • the LO drive signal applied to switch the FETs is non-sinusoidal square wave or pseudo-square wave.
  • These square waves are generated by a novel Local Oscillator drive circuit, such as a drive circuit employing two floating CMOS "AND" gates, to generate a pair of complementary square waves from a sinusoidal LO drive input.
  • the switching devices e.g. FETs
  • the switching devices exhibit relatively linear characteristics in the ON or OFF states, but less linear characteristics in the transition between ON and OFF states.
  • the inventive square wave switch drive speeds the devices through transition, reducing the time period during which distortion is generated.
  • any periodic waveform having monotonic rise and fall segment and having suitable amplitude to trigger the square wave regeneration circuit may be used to drive the square wave regeneration circuit, and the regenerated complementary square waves driving the switches need not be perfect square waves, what is important is that they have steep slopes in rise and fall (high slew rate) so that the transition period between ON and OFF is short.
  • Logic gates readily provide the required input/output device characteristics.
  • each mixer device 32 typically is improved by up to approximately 15 dB or better (for example, from about 40 dBm to about 55 dBm), more typically by at least from 5dB to about 10dB (for example, from approximately 40 dBm to about 50 dBm), and dynamic range is improved equivalently.
  • Noise figure is also improved by the inventive mixer device structure and method, resulting in greater dynamic range for each mixer device 32, for example in one embodiment dynamic range is improved by from about 10 dB to 15 dB.
  • Intermodulation distortion is suppressed commensurate with the third order intercept improvement described above.
  • the required sinusoidal wave LO drive measured at the LO input port terminals is also reduced by about 10 dB.
  • conversion loss, noise figure, port match, and isolation between the L-port (LO-port) and the R-port (RF-port) and I-port (IF-port) are also favorably effected by square wave drive.
  • Noise figure is improved because the longer switch transition phase of conventional mixer configurations generates more noise than does the inventive mixer 32, and reducing the time spent in the transition phase reduces noise.
  • the improvements in each of these areas for the inventive mixer 32 may typically be about 1 dB (conversion loss), from I dB to about 3 dB (noise figure), from about 1dB to about 5 dB (port match), and from about 1dB to about 10 dB (L-port to I- and R-port isolation), often the larger figure will be achieved, and even greater figures may be achieved, however, these are only a typical range over which improvements may be expected. Because of the very large voltage gain of CMOS gates in the transition region (typically a voltage gain on the order of about 1 ⁇ 10 5 ), the LO drive requirement for the inventive mixer apparatus and method is comparable to the most ordinary mixers, that is about 13 dBm.
  • sinusoidal-to-square wave generation or conversion circuit may be used in other than radio receivers, and for other than mixer applications, the regeneration circuit design is described in greater detail relative to embodiments of an up-frequency and down-frequency convention below.
  • the inventive mixer may be advantageously configured as an up-frequency converter or as a down frequency converter.
  • a simple embodiment of the inventive mixer is described relative to FIGs. 2 and 3.
  • operation and structure of the up converter are described relative to the illustration in FIG. 4, after which minor difference in structure and operation are described for the second embodiment configured as a down-converter are described relative to FIG. 5.
  • phase splitter 110 receives a Local Oscillator (LO) signal from an external LO signal source (not shown) at LO input port 120 and splits the LO signal into two separate phases to generate a pair of phase complementary output signals ( ⁇ 1, ⁇ 2).
  • Phase splitter 110 may also include ground isolation circuitry 115, such as ground isolation transformers 115a, 115b provided for each split phase or other means for providing ground isolation as is known in the art. Alternatively, and advantageously the ground isolation 115 may be provided by means separate from the phase splitter 110.
  • phase complementary signals in the present context are signals that have substantially equal amplitude and 180-degree phase difference between them.
  • the floating or differential signal output by the ground isolation circuitry 115 are designated ⁇ 1f and ⁇ 2f in FIG. 2.
  • a second functional component, the square wave generator 130 receives the two split phase floating sinusoidal signals from ground isolator 115 or from an integrated phase splitter 110 and ground isolation circuit 115, and generates a pair of "floating" (or differential) square wave switch drive output signals ( ⁇ 1f-sq , ⁇ 2f-sq ).
  • the square wave signals are termed "floating" (or differential) because they are generated by a circuit which is isolated from ground, such as via isolation transformers, the square wave generator circuit 130 is only capable of injecting a current into a load that is connected across the two FET gate terminals 160, 170, and will not generally inject current into a load that has ground as the return path because the balanced circuit is isolated from ground, and does not desire to send current into a grounded circuit terminal or node.
  • a third functional component, switching network 150 here including two four-terminal switches 160, 170, one for each switch drive signal ⁇ 1f-sq , ⁇ 2f-sq , and advantageously implemented with two pairs of serially connected MESFETs (161, 162 and 171, 172) which receives the differential square wave output signals.
  • each two or pair of FETs Q1, Q2 or Q3, Q4 forms a four terminal switching circuit (160, 170) such that each switching circuit has two input terminals and two output terminals, and that, in total, eight terminals exit from switching network 150.
  • the switching circuits 160, 170 are switched to complementary ON and OFF conduction states by the square wave output signals during each half cycle of the LO input signal, one ON, one OFF.
  • Switching network 150 is connected to the reflection plane 190 of a fourth functional component, the RF/IF balun network 180.
  • a Radio-Frequency (RF) signal is applied to mixer 100 at RF signal input port 200, and enters the RF/IF balun network 180.
  • the RF/IF balun network 180 advantageously includes a balanced reflection transformer 210 having reflection plane 190.
  • the ON or OFF conduction states of the switching network switch circuits 160, 170 provide the desired reflection characteristics, including occurrence and non-occurrence of signal phase reversal at the reflection plane 190.
  • the input RF energy reflects from switching network 150 and an IF signal emerges into an IF isolation transformer 220 and exits the mixer 100 at the IF output port 230.
  • the structures of the aforementioned phase splitter 110, isolation circuit 115, square wave generator 130, switching network 150, and RF/IF balun 180 are selected to maximize second order intermodulation suppression, optimally correct any capacitive asymmetry that may be present in the RF/IF balun network 150, and are sized to prevent undue loading of the ground isolation circuit 115, such as ground isolation transformers 115a, 115b on the IF isolation transformer 220 or RF isolation transformer 222.
  • phase splitter 302 also provides a ground isolation function and both phase splitting of the input LO sinusoidal signal are implemented with a passive transformer 306.
  • passive means such as a transformer having no semiconductors may be used, or alternatively, active means such as an amplifier, or floating logic gate circuit may be used, as well as other ground isolation structures and methods, as are known in the art.
  • Square wave generation circuit 130 includes separate gates 310, 312 for each LO input signal phase output the phase splitter and the output of each gate 310, 312 is separately fed to a different switching circuit 160, 170.
  • each of the functional components has utility separate from the combination.
  • the square wave drive may be applied to other than triple-balanced mixers, or to mixers that are transmission type rather than reflection type, and that the phase splitter and/or ground isolation means, are optional for some application, and may be provided by different circuits.
  • the phase splitter circuit 110 is not needed for mixers that do not use a balanced local oscillator or a complementary local oscillator.
  • Reference to input port and output port are indented to pertain to this particular embodiment of an up-frequency connector in the mixer environment; however, it is understood that the mixer has a first or input port and a second or output port and that depending upon the application, the input port may have higher, lower, or substantially the same frequency as the output port, an that more generally, the first and second ports may receive or deliver a signal to the ports.
  • the LO Phase Splitter is now described relative to the mixer 600 embodiment in FIG. 4.
  • the LO signal from which is derived the switch signal is input at L port 622 where it enters LO signal conditional circuitry and phase splitter transformer T1 623.
  • Resisters R12, R13, R14, R15 (624, 625, 626,627) ensure good impedance match for the two 50 ohm outputs (terminal pairs 1, 2 and 3, 4) of the transformer 623 while maintaining good match at input L-port 622.
  • Capacitors C18, C19, C20 (628, 629, 630) are DC blocking capacitors.
  • phase splitter 621 and more specifically transformer 623, generates first and second ( ⁇ 1, ⁇ 2) balanced signals that have matched signal characteristics.
  • phase splitter transformer 623 The two LO outputs from phase splitter transformer 623 are separately fed to first and second isolation transformers T2 642 and T3 643 each of which receives a two-terminal input ⁇ 1 or ⁇ 2 and generates a ground (or other voltage referenced) isolated floating two-terminal output which is communicated to square wave generator circuit 640.
  • Square wave generator circuit 640, 641 receives each output of the phase splitter 621 via isolation transformers T2 642 or T3 643.
  • DC bias voltage from the phase splitter circuit 621 passes through isolation transformer T2 and T3, and though resists R6 644 and R7 645, and supplies the CMOS "AND" gates U1 646 and U2 647 respectively.
  • U1 and U2 are 74AHC1G08 AND gates made by Texas Instruments, Inc.
  • the structure and operation of square wave circuits 640, 641 are the same so that only circuit 640 is described in detail. With respect to square wave generator circuit 640, current returns through transformer T2 to ground. The bias supply voltages are locally bypassed by capacitor C12 648 (or C13 649).
  • Resister R6 644 (or R7 645) doubles as a termination resister for transformer T2 (or T3).
  • One input 653 of gate U1 is tied to the bias supply, while the other input 654 is biased to half voltage by means of resister divider network R8 641 and R9 652.
  • Capacitor C14 654 couples the LO signal to gate U1 646 without disturbing the gate U1 bias point.
  • Pins 4 655 and 3 656 of U1 form a first floating square wave output at terminals 661 and 662.
  • An identical second square wave generator 651 is fed by transformer T3 in analogous manner to form a second floating square wave output at terminals 663 and 664.
  • transformer T1 623 at the output of phase splitter may be adequate for certain applications. In such cases, transformers T2 642 and T3 643 would not be required and the phase splitter outputs would be sent directly into the square wave generator circuits 640, 641. Transformers T2 and T3 serve to better isolate the floating circuitry, that is gates U1 646 and U2 647, and their surrounding components from ground. And, at the same time the burden of achieving the floating condition is advantageously removed from the phase splitter transformer T1 623, so that the two operations (LO signal phase splitting and ground isolation) may be separated and more precisely achieved by providing explicit separate transformers for each one operation. That is, transformer T1 is responsible for phase splitting, and transformers T2 and T3 are responsible for ground isolation, and each can be designed to optimally to perform its function.
  • phase splitter and ground isolation means provides benefits or conveniences in addition to those already described.
  • a DC current path from the common sources (S1, S2) of the mixing FETs to ground is advantageously provided by transformers T2 and T3.
  • Providing the transformers T2 and T3 in the circuit also provides the ground isolation very nicely without participating in the phase splitting function, and the phase splitter 621 accomplishes its job without having to generate a large amount of ground isolation.
  • phase splitter 621 does not have to generate any ground isolation because terminal pin 2 of transformer T1 is AC coupled directly to ground so that it is still a ground referenced signal.
  • Terminal pin 3 for the second phase is also AC coupled to ground in like manner.
  • phase splitting is more readily accomplished if one can maintain a ground referenced signal during the phase splitting operation, and then isolate those split signals from ground. While one may accomplish phase splitting in a single ground isolated circuit, typically the accuracy of the operation is diminished when it is accomplished by a single transformer.
  • Square wave generation circuits 640 and 641, such as logic gates U1 and U2, may be implemented by NAND, AND, OR, NOR, XOR, XNOR gates with appropriate modification to the circuit, as well as other so-called primitive gates.
  • a gate is designed to generate two discrete logic levels (about 0 volts and about 5 volts for CMOS) representative of the two levels of a square wave.
  • the logic gates each generate two decreet levels (for example, about zero (0) volts and about five (5) volts for micro-gate logic family), the amplitude of the gate output is limited, and the output level does not correspond to a high amplitude sinusoidal signal except that in the sense that the slew rate of the square wave gate output signal is very high, this high slew rate has the effect of a very large amplitude sinusoid in terms of minimizing the period of time spent in transition between ON and OFF conduction states of the FETs.
  • the need for a high sinusoidal LO drive level is therefore alleviated by the greatly improved high slew (square wave) drive waveform shape, hence, only about 20 milliwatt (mW) of power is required to operate the inventive structure. This compares to about 200 milliwatt for conventional structures. The benefit is achieved because the shape of the square wave is ideal, or at least more nearly ideal than the conventional sinusoidal signal.
  • One embodiment of the inventive circuit only terminates about 13 dBm, which is 20 milliwatts.
  • the circuit thereafter generates somewhat larger signal levels, which are more ideally shaped, but these signals are applied to a capacitive load and are not terminated into any resistive load.
  • the signals are presented to the capacitive load of the FET gate, so that the inventive circuit is "power conservative" and the gates themselves require minimal power, typically only about 35 milliwatts to perform their mixing function.
  • This circuit is therefore far more power conservative than conventional circuits that would use or require a large magnitude conventional sinusoidal signal LO drive, or LO drive coupled to a high gain amplifier to provide the 200 milliwatt operating power.
  • This inventive power conservation feature is advantageous for portable or battery powered radio products, and could for example be of great benefit in a mobile communication handset, in that better performance would be obtained at considerably lower power than is obtainable with conventional structures.
  • the invention therefore provides for power conservation in mobile radios and modems, cellular telephones, and any other devices that use a mixer, especially for battery-powered devices where battery life and/or radiated power for a particular operating time are a significant concerns.
  • the benefits of power conservation would be achieved.
  • heat generation and dissipation concerns that may reduce product life are also reduced.
  • Satellite developed communication devices typically dependent on battery, fuel cell, or solar power
  • employing large mixers may also benefit as a result of reduced operating power and reduced thermal power generation.
  • first and second logic gates 121, 122 here CMOS "AND” gates, such as the 74AHC1G08 manufactured by Texas Instruments.
  • CMOS "AND” gates such as the 74AHC1G08 manufactured by Texas Instruments.
  • logic gates 121, 122 other than “AND” gates such as, but not limited to, NAND, OR, NOR, XOR, and that other logic gates may be used either alone or with the addition of additional gates or conditioning circuitry, and that logic families other than CMOS, such as, but not limited to TTL, ECL, or other logic families may be used to implement the selected gates.
  • the gates 205, 206 form the square wave generator circuit and may alternatively be replaced with other circuits or devices which generate a high slew rate signal in response to the input sinusoid.
  • Schottkey diodes may be used in place of gates to increase the mixers applicability into the gigahertz (GHz) frequency range.
  • GHz gigahertz
  • Independent bias voltage inputs for the two CMOS "AND" gates allows precise trimming of the output square wave amplitudes, which is useful in optimizing second order intercept point. Due to the excellent gain of the CMOS logic gates, very little LO sinusoidal drive power is required. Potentially as little as 0 dBm of LO sinusoidal signal drive applied to the gates would still result in normal mixer operation.
  • One embodiment of the inventive mixer device achieves a conversion loss of about 6dB, a noise figure of about 7dB, a port return loss of about 15dB, isolation between any ports greater than about 40dB, and input IP2 of about 90dBm, and input IP3 of about 45dBm. These input intercept points (IIP2 AND IIP3) are achieved with only a +13dBm LO sinusoidal drive level.
  • Such mixer would also advantageously be provided with square wave LO signal derived drive.
  • the FET source terminals of such a mixer would be grounded, and the load connected to the mixer would be ground referenced, there is no need for a phase splitter.
  • Such mixer configuration would only require the logic gate to receive the sinusoidal LO input signal directly.
  • Mixers are used in communications electronics including cellular communication systems and devices, space communications, ground communication stations, instrumentation and test equipment, no name only a few mixer applications.
  • the particular embodiment of the device being shown and described with respect to FIG. 4 may have a useful bandwidth up to several hundred Megahertz. But, with appropriate modifications readily appreciated, in light of the disclosure provided herein, by workers in the art, other embodiments of the invention readily extend this bandwidth range to tens of Gigahertz.
  • the invention may also be used in a base station application where there may be more than one mixing or frequency conversion process during the down-conversion of the incoming 900 Mhz or higher frequency signal to an intermediate frequency (IF) signal, and then a second down-conversion from that IF to baseband.
  • IF intermediate frequency
  • the inventive mixer device may be used for the second (IF-to-baseband) conversion to obtain very high linearity. This makes sense because the back end of such a system normally has the gain of previous stages to contend with, and so it is working at higher signal levels. Preservation of the higher levels of linearity are important in those back end stages in order to preserve the intercept point of the whole receiver.
  • square wave regenerating devices and methods other than logic gates that could be floated in the manner described here, that have bandwidths up to one or a few gigahertz.
  • a method using step-recovery diodes as the square wave generation means may be applied up to about a few gigahertz, and which may be implemented in a small size within a floating environment.
  • An amplifier run in hard saturation will also convert a sinusoidal wave into a square wave by clipping it symmetrically.
  • Even a simpler embodiment of the mixer circuit may be provided that would allow the level of the sine wave be fairly high and by using back-to-back Schottky diodes the large amplitude sine wave would be clipped into a lower amplitude square wave.
  • Small physical device or component size is important when trying to float a component because large physical dimensions typically imply a large amount of coupling capacitive or inductive parasitics between the component and the ground plane of the circuit or to the enclosure of the circuit.
  • the logic gates that generate the square wave By keeping dimensions of the logic gates that generate the square wave small (easily accomplished using readily available commercial logic gate chips or custom designed and fabricated logic gates), the coupling is minimized and it is possible to float circuits and isolate them from ground and from the enclosure very effectively.
  • These commercial logic gates cost on the order of less than a dollar per gate in small numbers, and fractions of a dollar per gate in quantity so that use of such gates in the mixer has significant cost advantages as well as performance advantages.
  • Switching devices such as FETs
  • FETs have undesirable characteristics at points of transition in replicating a short circuit and an open circuit.
  • the device For a switching device, one prefers the device to be operating as either a short or as an open circuit, and rapidly toggling between the two states. In order to get between the states, the switching device must pass through a transition state. It is during the transition state or phase that the transistor, diode, or other switching element or circuit being used, displays the maximum amount of nonlinearity, generates the maximum amount of distortion components, and injects a maximum amount of noise into the circuit.
  • the perturbation (or destruction) of mixer port-match and mixer isolation is also typically worse during the transition phase than at any other time because the non-ideal (and typically time varying) impedance value exhibited by the switch during the transition, is a different impedance than the circuit has been designed to have. Therefore, the faster the switch moves through the transition phase, the less time the mixer circuit has to endure the hardships associated with transition phase characteristics.
  • An "ideal" square wave is infinitely fast and does not spend any time in the transition.
  • the ideal square wave also has a fifty-percent (50%) duty cycle and perfect signal symmetry (e.g 180 degrees).
  • Feedback circuits can also optionally be used to insure that perfect symmetry and duty cycle characteristics are precisely maintained over a range of operating conditions and environments.
  • a real square wave or pseudo-square wave form by high slew rate but which is somewhat bandwidth limited transits the transition phase in a minimum time. For these and other reasons, the square wave is an optimal waveform for driving a mixing device.
  • FIG. 6 aids in illustrating how back-to-back FETs cancel intermodulation distortion in the mixer circuit.
  • the gate-to-source voltages for each FET are equal and also equal to the FET control voltage.
  • Vs 1 d 1 -Vs 2 d 2
  • Vs 1 d 1 the source-to-drain voltage across transistor Q1
  • Vs 2 d 2 the source-to-drain voltage across transistor Q2.
  • ⁇ R ds c ⁇ ⁇ V gd , which says that the channel resistance across the drain-to-source channel ( ⁇ R ds ) is linear (to a multiplicative constant c) to gate bias voltage ( ⁇ V gd ). This assumption is nearly correct during the time that the FETs are heavily conductive.
  • the small signal passes through the FET channel combination without controlling its resistance. This condition is equivalent to infinite intermodulation suppression. This is the technique used in mixer to help reduce intermodulation distortion.
  • the distortion signal can be separated into two distinct components.
  • a signal voltage V sig can be applied to the FET pair as a potential difference between the two drains D 1 and D 2 .
  • V ds1 V sig / 2
  • V ds2 -V sig / 2
  • V ds1 is the drain-to-source voltage for the first FET
  • V ds2 is the drain-to-source voltage for the second FET and the total voltage is split between the two.
  • V ds1 V sig / 2 + V dist,odd (V sig / 2) + V dist,even (V sig / 2)
  • V ds2 -V sig / 2 + V dist,odd (-V sig / 2) + V dist,even (-V sig / 2)
  • V ds1 V sig / 2 + V dist,odd (V sig / 2) + V dist,even (V sig / 2)
  • V ds2 -V sig / 2 - V dist,odd (V sig / 2) + V dist,even (V sig / 2)
  • V ds1 V sig / 2 + V dist,odd (V sig / 2)
  • V ds2 -V sig / 2 - V dist,odd (V sig / 2) + V dist,even (V sig / 2)
  • V ds1 V sig / 2
  • V ds drain-to-source
  • V gs gate-to-source voltage
  • the distortion produced by each of the two FETs operating as a pair is summed by means of the back-to-back serial connectivity between the two FETs, so that the distortion is canceled.
  • This condition is met in the invention by the common source connection of the two FETs, and by the connection of the two drains of the FET pair to the mixer ports.
  • Conversion loss, noise figure, and intermodulation suppression are even further enhanced by the use of a square wave gate drive.
  • the square wave switches the mixing FETs rapidly between ON and OFF states, thus avoiding the lossy and strongly nonlinear transition state substantially.
  • Further improvements in second order intermodulation suppression are achieved by providing precise balance in the mixer circuit, which assists in maintaining cancellation of unwanted mixer products.
  • the balance desired, and the performance achieved in one embodiment, is at least partially attributed to the ideal characteristics of the balanced reflection transformer which cancels second order non-linearities.
  • Isolation transformers are advantageously used at the RF and IF ports, as well as at the CMOS gate inputs to preserve the balance of the mixing process.
  • the balance is advantageously improved even further by providing a well matched LO phase splitter transformer 623 in the mixer 600, where input series resistors (e.g. R12, R13, R14, R15) are added to completely eliminate standing waves in the transformer 623.
  • Resistors R12-R15 along with capacitors C19-C20 decouple the LO signal from the gate bias. This structure ensures very accurate phase control.
  • inventive structure and method provide the means for achieving a square wave drive in the mixer circuit or within the direct drive receiver system without adversely effecting other conditions of the circuit or system in order to obtain high-performance.
  • inventive structure provides a synergistic set of structures and processor to introduce square waves into the mixer. Also, to implement the square wave drive, over a broad band of frequencies in balanced form, and/or in ground isolated form is difficult and not disclosed or suggested by conventional structure or methods know to the inventors.
  • FET pair Q1 is formed from a pair of identical MESFETs each having a drain (D1, D2), a gate (G1, G2), and a source (S1, S2) connected together to form a four terminal switching circuit 671.
  • the first switch circuit 671 is switched on and off by the square wave output of gate U1 646, which is capacitively coupled to the gates of Q1 via capacitor C10 673. Note that the gates of the FETs making up Q 1 are tied directly together and that the sources are also connected together so that the two FETs are connected serially back-to-back (source-to-source).
  • Capacitors C10 and C11 serve to allow the gate terminal of Q1 to self bias while resistors R4 and R5 acts to further control the self bias point by a gate ground return.
  • the second switching circuit Q2 672, capacitor C11 674, and resistor R5 680 function in a like manner.
  • Resistor R3 682 ties the two switching networks 668, 669 together at the common FET source nodes and how a resistance value (here 150 ohm) is chosen to maximize second order intermodulation suppression. Second order intermodulation suppression is positively affected by R3 because it keeps Q 1 and Q2 at equal potentials but isolates them.
  • Transformers T4, T5 and T6 (684, 685, 686) operate as a balun network 687.
  • RF signal energy enters the mixer at the R-port 688 where it is ground isolated by RF port isolation transformer T6 686, through DC blocking capacitors C1 689 and C2 690 as the RF signal enters balanced reflection transformer T4 684.
  • Switching networks Q1 and Q2 (671, 672) are connected to the reflection plane 691 of transformer T4 634 such that the RF signal energy reflects off Q1-Q2 and emerges as the IF signal into IF isolation transformer T5 685 and out the I-port 692.
  • Slight capacitive asymmetry in the balun network may be trimmed out by means of capacitors C6 693, C7 694, C8 695, and C9 696.
  • Means for injecting a drain bias at Vdd bias for Q1 and Q2 is provided by filtering network C3 697, C4 698, and C5 599 and L1 700, and by resisters R1 701, R2 702 and R16 703, R17 704.
  • the four resisters (R1, R2, R16, R17) are chosen to prevent undue loading of the RF isolation transformer T6 and T4.
  • a third alternative mixer 800 embodiment is illustrated in FIG. 7.
  • the resistive networks R16, R18, R19, R1 and R17, R20, R21, R2 provided in this serial-parallel combination of FIGS. 4 and 5 for power handling receivers have been simplified to two resistors RA, RB.
  • the resistors provided in the LO input stage (R14, R15, R12, R13) for LO decoupling have been eliminated, as have resistors R4, R5 for FET gate self bias in the gate drive circuit.
  • a further performance improvement to the inventive mixer may be realized by providing temperature compensation circuity to compensate the logic gate circuits for operating temperature.
  • a voltage divider pair of resistors pull-off of the V dd voltage supply terminal of the chip, divide the voltage in half and put the half voltage in the gate to set the operating point.
  • This compensation is desirable because it was discovered that going over the operating temperature range of the mixer, some compensation is at least desirable because the particular CMOS gate (Model No. 74AHC1GOB) manufactured by of Texas Instruments, Inc. has an internal reference voltage that may drift with temperature and it is desirable for the bias point to drift with the drifting reference voltage.
  • the temperature sensor puts out a proportional voltage. Initially, at room temperature, resistor R2 is set for 5 volts for gate bias. As the temperature changes, this initial voltage at R3 is adjusted at the temperature limits of -10 C and +60 C to compensate for gate bias changes.
  • inventive super-mixer 32 may advantageously be used.
  • one aspect of the present invention includes a mixer device structure 32 and mixing method, and structure and method for a tuner and transmitter/receiver.
  • a mixer device structure 32 and mixing method, and structure and method for a tuner and transmitter/receiver may be provided, and reference to either type in this disclosure is not to be construed as limiting the invention to one type or the other.
  • tuner, receiver, or transmitter we will refer to tuner, receiver, or transmitter, and the particular type will be apparent from the structure shown or described, or the description will be applicable to all types.
  • the inventive tuner has high-dynamic-range, and may be used to convert wireless spectrums down to baseband.
  • Analog to Digital (A/D) Converters digitize the analog spectrum and Digital Signal Processors extract the modulation intelligence from the signal.
  • Digital to Analog (D/A) Converters can reproduce any part of the input spectrum at baseband or any modulation back to analog form. This entire conversion process illustrated relative to FIG. 9, should ideally replicate the wireless spectrum exactly with no distortion added at any stage or step of the process. One can measure this distortion less process as a function of dynamic range.
  • the inventive tuner keeps up with the state of the art stages and provides more than sufficient performance which meets or exceeds the dynamic range of next-generation high performance 14-bit and 16 bit A/D Converters.
  • FIG. 10 shows a digital conversion system topology.
  • the final IF is band-limited with a standing acoustic wave (SAW) filter, converted to baseband, low-pass filtered, and amplified to the drive level required by the A/D converter, typically about 1 to 2 volts.
  • SAW standing acoustic wave
  • IIP2 or IIP3 for the input to a tuner stage
  • OIP2 or OIP3 for the output of a tuner stage.
  • the output IP differs from the input IP by the gain or loss of the stage.
  • A/D-converter manufacturers have their own unique way of specifying spurious signal content.
  • Spur-Free Dynamic Range as dB from full scale to the spurious signal with two signals being 7 dB from full scale is described relative to FIG. 13. Note that this definition of SFDR differs from the classic analog form that we describe later.
  • the A/D-converter performance specifications control how much dynamic range a tuner requires in order to faithfully process large and small signals, while overcoming the A/D-converter noise floor with distortion less tuner gain.
  • the A/D converter industry has made much progress in the past few years. Until recently, a state-of-the-art A/D converter for use with a tuner would have 12-bits resolution sampled at a 65-MHz clock rate, and 80-dB SFDR over a 25-MHz bandwidth.
  • State-of-the-art A/D converters have at least 14-bits resolution (some are expected to provide 16-bit resolution) a near 100-dB SFDR, a Signal to Noise Ratio (SNR), and a full-scale signal level, and, when clocked at 65 MSPS, will support IF bandwidths out to 30 MHz (See FIG. 14). This is 20-dB higher dynamic range than A/D converters available in 1997.
  • FIG. 15a is a graph illustrating a 100-dB SFDR signal spectrum into these 14-bit A/D converters.
  • the tuner requires a capability to process two signals, without producing spurious signals over 100 dB from full scale.
  • the final frequency converter processes the largest tuner signals and must supply the A/D converter with up to about 2-volts peak-to-peak (P-P) into 800 Ohms as illustrated relative to FIG. 15b.
  • the signal transformed down to 50 Ohms should be about 2-dBm for full-scale drive.
  • the IP2 and the IP3 calculation shows the final frequency converter needing an IP2 of about +98 dBm and IP3 of about +48 dBm.
  • This calculation uses 6 dB as a safety factor to account for possible differences in A/D-converter SFDR and the analog drive requirement.
  • No practical A/D-converter driver amplifier known to the inventors can process a signal at -2 dBm out to 30 MHz with the second and third harmonic i.e., N ⁇ N distortion (e.g. 2 ⁇ 2, 3 ⁇ 3, etc.) down 100 dB.
  • Eliminating the A/D converter driver amplifier and driving the A/D converter directly from the mixer would require a +4 dBm input, an input IP3 of +54 dBm, and an IP2 of +104 dBm.
  • the inventive mixer provides performance that meets or exceeds these specifications for this final frequency conversion stage.
  • An A/D converter for a tuner application may also have a high noise figure. The increased bits of resolution of the 14-bit A/D reduces the noise floor as compared to earlier 12-bit A/D converters.
  • Noise Figure (dB) -174 - SIG fullscale - NOISE FLOOR, where -174 is the nominal noise floor of a 50 ohm resistor in a 1 Hz bandwidth at room temperature, and SIG fullscale is the signal level at full scale. For the 14-bit A/D converter, this results in a Noise Figure of 25 dB. With respect to FIG. 16, and for this description, if the overall tuner requires a noise figure of 10 dB, then the overall tuner gain (tg) in front of the A/D converter must be approximately 16 dB with a very large signal-handling capability.
  • Tuner design is complex, with the competing demands of balancing noise figure and dynamic range requires both skill and a deep knowledge of preselectors, mixers, amplifiers and filter components. Too much gain, to get a better noise figure, hurts the intercept points; too little gain cannot overcome the high A/D-converter noise figure. These principles are understood by workers having ordinary skill in the art of mixer design. All stage component parameters in the tuner signal path contribute to this dilemma.
  • One of a mixer designer's first tool for this balancing act is the Gain (G), Noise Figure (N), Intercept Point (IP) computer aided design (CAD) program -- sometimes called a GNIP run or simulation, which programs are known in the art and not described further here.
  • FIG. 17 illustrates a GNIP run of a hypothetical tuner equipped with the best known conventional components presently available; and it includes an exemplary inventive super-mixer structure as the final conversion stage. Exemplary values for stage gain, stage noise figure, stage IP2 and IP3, as well as cumulative values for stage gain, stage noise figure, stage IP2 and IP3 are indicated for the GNIP simulated configuration. Note that the preamplifier and first mixer severely limit both IP2 and IP3 as recorded in the cumulative run. A sub-octave preselector can help reduce the IP2 requirement, but adds a costly component to the tuner.
  • FIG. 18 shows the GNIP run performance with the new super components.
  • the super mixer eliminates the costly preselector.
  • FIG. 19 relates the 100-dB dynamic-range super-mixer performance to both real-world signal conditions and the classic analog dynamic-range formula.
  • FIG. 20 provides some specifications for these mixer components. Ideal mixers require perfect or nearly perfect switching functions with no or substantially no non-linearities.
  • FIG. 21 is a high level block diagram of one embodiment of the mixer showing the IF, RF and LO circuits, switching circuits (FETs) floating driver circuits, and the connections therebetween, which may be used either for frequency up or down converting. FETs are advantageously selected and matched or fabricated to a high level of exactness and precision.
  • the LO circuits that produce nearly perfectly symmetrical switch signals only need an external drive level of about 100 millivolts.
  • the LO drive circuitry and FET switches are embedded on the tuner printed-circuit board and need not be confined in a metal can. This allows considerable design freedom with circuit-component values adjusted for proper balance and drive level.
  • One of the most difficult tasks for assessing the inventive structure involves measuring distortion parameters for the inventive mixer and tuner. Only high-level signals with the purest spectral content could be used. Conventional signal generators capable of providing the two-tone test may not be generally available, nor may spectrum analyzers that would not intermodulate and produce a signal in the wanted-signal output-test spectrum.
  • An exemplary test configuration for measuring distortion parameters is shown in FIG. 22. Note the power amplifiers used to boost the signals and the low-pass filters to clean up the harmonics. The mixer was terminated into 1:1 VSWR load for the tests. The converted signal was then notched or low-pass filtered in order to measure only the super-mixer distortion products.
  • One embodiment of the inventive mixer is incorporated into a Dual Tuner Module (DTM) intended for HF applications requiring maximum dynamic range in minimum space.
  • DTM Dual Tuner Module
  • the particular tuner embodiment specifically interfaces with the Hewlett-Packard E1430A A/D Converter for both single and multichannel applications. It covers the 0.1 to 32 MHz frequency range providing over 95-dB instantaneous SFDR in a 4- MHz bandwidth (and 8 MHz option may also be implemented).
  • the tuner uses state-of-the-art architecture and component technology and achieves an out-of-band IP3 of from +40 dBm to more than +45 dBm and out-of-band IP2 of from + 80 dBm to more than + 90 dBm, and an overall dynamic range of from 95 dB to more than 100 dB.
  • Direct and frequency converted paths as illustrated in FIG. 23, ensure maximum performance for any frequency.
  • the tuner switches the upper frequency band (here, about 4 to 32 MHz) to a signal path that amplifies and up converts it to a 70-MHz first IF.
  • the tuner then amplifies, filters, and down converts the signal to near baseband.
  • SAW bandpass filters obtain sharp shape factors and provide constant group-delay characteristics.
  • the low-band (about 1-4 MHz) and high-band (about 4-32MHz) frequency paths again come together for final amplification, impedance transformation and filtering. It is advantageous that these baseband amplifiers exhibit extremely low spurious output because the super-mixer does not drive an A/D converter directly.
  • An optional internal noise source at the front end of the RF tuner advantageously provides built-in-test operations.
  • the inventive embodiment gives special attention to optimizing conversion performance by using the inventive mixer since spurious outputs of the down-conversion mixer and amplifier, as previously explained, are critical and can limit the SFDR performance of the tuner.
  • the N ⁇ N (2 ⁇ 2, 3 ⁇ 3, etc., etc.) products are key, since they fall within the IF passband. For this particular embodiment, this performance is achieved in a small physical package with two HF tuners housed in a single-width C-size VXI module.
  • the inventive system provides the required SFDR performance (e.g. 100 dB of Spur Free Dynamic Range) with a 14-bit or higher-bit ADC (that is from about 6 dB to about 9 dB of dynamic range per ADC bit) and the capability of providing this digitization over a 30 Mhz frequency spectrum.
  • the system circuit topology as well as the circuit implementation of the FET super-mixer also provides this level at a modest cost as compared with the cost for conventional approaches even if they could someday achieve the required performance.
  • FIG. 24 One HF collection topology for the ALE which collects all of the HF signal spectrum in one band using two tuners (each including the inventive super mixer 32) is illustrated in FIG. 24.
  • Two tuner sections are used to cut the HF bandwidth (here, 2 Mhz to 30 Mhz) in half (e.g. 9 Mhz ⁇ 7 Mhz, and 23 Mhz ⁇ 7 Mhz) and two leading edge ADCs are used to cover the HF band in two parts.
  • Four of the inventive super-mixer 32 are used in this topology, along with suitable amplification and filters as shown.
  • the ADCs are 14 bit to preserve the sensitivity and resolution to required levels.
  • tuners must have a high dynamic range, and although such tuners are available (such as from Watkins-Johnson Company) of Palo Alto, California, the present cost of such very-high performance high-dynamic range tuners satisfying the specifications for ALE monitoring sites would be higher than that of other alternatives using a single tuner for the entire HF band as described elsewhere in this specification.
  • a single heterodyne HF band tuner using super-mixer as the first frequency converter, a 70 Mhz IF bandpass filter and a direct conversion I/Q down converter provides as good or better performance.
  • Each of the ADC's coupled to the I and Q channels need only 15 Mhz of bandwidth instead of 30 Mhz, and the DSP circuitry receiving the ADC digitized output can run at a slower clock speed.
  • the direct I/Q conversion topology described herein provides a basis for this operation in that the I and Q signals are amplitude and phase matched within a very small percentage over a wide frequency range, LO quadrature may be maintained by providing LO feedback circuits, and the RF signal is provided in-phase to the mixers.
  • the applicability of the direct conversion/ADC approach for down-conversion and for up-conversion when combined into a single receiver/transmitter system provides total "software radio" communications capability, where the receive and transmit components operate under total computer or processor software (including hardwired, firmware, or hybrid software/firmware/hardware) control.
  • the inventive structure is now described relative to a conventional heterodyne receiver 21 illustrated in FIG. 25 and an embodiment of the inventive heterodyne receiver in FIG. 26.
  • a first frequency e.g. RF
  • a second frequency e.g. IF or Baseband
  • the inventive mixer achieves over + 50 dBm IP3 and over +100 dBm IP2 as a baseband converter that can directly drive 14-bit analog-to-digital Converters (ADCs).
  • ADCs analog-to-digital Converters
  • This combination of mixer and ADC places all spurious responses close to 100 dB from full scale over a 30 MHz bandwidth.
  • This super mixer is a near perfect analog converter with insertion loss approaching theoretical. It is based on a grown GaAs FET switch with excellent switch properties.
  • the LO signal switch control
  • inventive super-mixer's IF port baseband
  • the inventive mixer is capable of down-conversion and up-conversion.
  • FIG. 25 there is shown a conventional overall heterodyne receiver system topology 21 including an IF signal source 22, IF signal attenuator 23 (shown here to emphasize the higher input level of the inventive mixer 31 even though an attenuator 23 may not actually be provided), a conventional mixer device 24 which receives the IF signal having amplitude A, from attenuator 23, and a sinusoidal local oscillator (LO) drive signal provided from an external LO signal source 25, and output power amplifier 26.
  • the inventive radio receiver 31 topology which includes the inventive mixer device 32, efficiently eliminates the attenuator 23 (by virtue of its lower drive requirement) and output amplifier 26 (by virtue of its higher output level).
  • the conventional receiver 21 requires a lower input IF signal level (attenuator 23) so that spurious signals are minimized or controlled to acceptable levels and requires an output amplifier 26 to subsequently achieve full ADC scale. Even the best amplifiers known to the inventors at the time of the invention create second and third order harmonics that exceed ADC specification limits for spurious free dynamic range.
  • the inventive mixer topology 31 including the inventive mixer device 32 allows a higher IF (or RF when used to down current signals) signal level input, provides lower loss internally, has lower spurious signal generation levels that are well within the ADC limits, and does not require an output amplifier 26 to provide the required output level (up to about 2 Volts peak-to-peak signal level or 0.1 watts of power).
  • the output of amplifier 26 would be fed to ADC 27 at about a 2 volt peak-to-peak signal level.
  • a signal notch filter 28 may be provided to remove the wanted converted signal in order to measure the performance on a spectrum analyzer during calibration and performance testing since the otherwise the spurs may be so small as to be undetectable with generally available laboratory instrumentation, but no such notch filter would be used in an actual system since the objective is to pass the converted signal not suppress it.
  • the performance would be a mixer device 32 output signal level of 0.5 volt peak-to-peak.
  • the inventive mixer device 32 provides structure and method for a mixer system with about +50 dBm IP3 and about +100 dBm IP2, and provides a baseband converter that is capable of directly driving 14-bit ADCs with 65 MSPS conversion rates. In one embodiment, this combination of mixer and ADC places spurious responses close to 100 dB from full scale over a 30 MHz bandwidth.
  • the inventive mixer is a near perfect converter with insertion loss approaching theoretical limits of about 5.5 dB.
  • the mixing device 32 may advantageously incorporate a GaAs FET switch with near ideal switch properties.
  • the switch control circuit (LO drive circuit) provides an ideal or near-ideal switch waveform for symmetrical complimentary switching the RF signal.
  • the mixer's IF port baseband can drive an ADC full scale directly without the limitations of a high powered amplifier.
  • the invention could also provide a homodyne mixer using two super mixer circuits.
  • the inventive LO drive circuit switches two sets of FETs, advantageously implemented as GaAs FETs, in perfect quadrature thereby insuring near perfect in-phase and quadrature phase baseband signals.
  • the two mixers have high intercept points (IP2 and IP3) to reduce spurious signals below all other conversion errors in the mixer, even including phase and amplitude conversion errors.
  • the mixer circuits desirably have matched baluns and phase and amplitude errors are reduced in the in-phase (I) and quadrature-phase (Q) output signals.
  • the direct drive to the ADC also preserves the I/Q signal linearity by eliminating the final amplifier used in conventional systems that typically may introduce non-linearities.
  • the I/Q signals are only one-half (1 ⁇ 2) the bandwidth of the RF signal, and therefore, the two ADC's need sample clocks (fs) running at one-half frequency.
  • the inventive homodyne mixer has significant advantages and applications over the conventional heterodyne structure and method including: providing structure and method for a HF/VHF/UHF wide band down converter, providing better multichannel beam forming with improved phase and amplitude match, reducing a radio's complexity by one IF stage without a reduction in dynamic range, elimination of Surface Acoustic Wave (SAW) filters and their insertion loss and cost, use of a fixed LO signal frequency over the entire cellular band (about 800 Mhz to about 1 GHz) to provide improved phase noise characteristics, and to provide an inexpensive two-device radio using the mixer and ADC/DSP integrated circuit.
  • SAW Surface Acoustic Wave
  • the inventive mixer circuits 32 utilize a switch, desirably implemented with a GaAs FET transistor, which is characterized by nearly ideal mixer switching properties and a switch control (Local Oscillator driver) circuit designed and implemented with a nearly ideal switching waveform, capable of converting the Radio-Frequency (RF) signal at such high levels and low loss that the IF output can directly drive the afore described state-of-the-art ADCs without limiting SFDR.
  • RF Radio-Frequency
  • the inventive homodyne receiver 31 may also desirably utilize "embedded technology" a technique that provides a radio tuner having the mixer and any balun circuits right into the pads of the printed circuit board, thereby eliminating a separate and costly packaging stage and allowing the circuit to be optimized for near perfect LO duty cycle, symmetry, and balance.
  • the direct drive conversion receiver advantageously provides better RF tuner dynamic range than would be provided by existing state-of-the-art ADCs or by predicted state-of-the-art ADCs for the foreseeable future, has lower conversion stage costs as the result of embedded technology, provides a basis for a Super Homodyne (as compared to heterodyne) receiver in that the IF stages are eliminated, boosts performance of both receiver and transmitter dynamic range for base stations as a result of lower spurious conversion, implements the receiver in hard to copy embedded circuits.
  • enhancements may also be provided to optimize receiver and mixer performance in order realize even higher dynamic range. For example, it may be desirable to: (i) optimize amplitude and phase match over a wide band by monitoring duty cycle symmetry, (ii) to provide feedback from the FET source to the digital gates to provide optimal LO quadrature, (iii) to provide in-phase RF signal to the mixer and IF output balance to the ADC, and/or (iv) to add some correction algorithms to the DSP in order to compensate for phase and amplitude and correcting any in-phase and quadrature signal errors.
  • the homodyne receiver provides structure and method for implementing an inexpensive approach for digitizing the radio-frequency spectrum with the resolution and dynamic range required for advanced communication, detection, and surveillance systems.
  • the inventive structure and method provide for both up- and down-frequency conversion so that, in general, references to RF signals as input and IF signals as output in the specification may be reversed.
  • An IF signal may be provided as the input and the RF signal may be generated or extracted on the output, and more generally signals may be referred to as the input and output and the ports which receive or output the signals referred to as first or primary port and second or secondary port.
  • FIG. 27 An exemplary direct conversion circuit topology 41 using two of the inventive super-mixers is illustrated for down-conversion is illustrated in FIG. 27 which shows RF and LO derived sine and cosine signal components generated by a divide-by-four circuit 45 from RF signal source 42 as inputs to first 43 and second 44 super mixer devices.
  • the sinusoidal LO input signal derived FET switching signals are coupled to two sets of FETs, advantageously GaAs FETs, to switch the sets of FETs in near perfect quadrature, thereby insuring perfect or substantially perfect sine and cosine (I and Q) baseband signals.
  • the direct drive to the ADC also preserves the I/Q linearity by eliminating any need for a final amplifier as typically provided in conventional systems.
  • two super-mixers are provided for directly converting the signal, where the same frequency LO derived signal driving the two super mixers in quadrature.
  • the in-phase (I) and quadrature (Q) channel outputs from these mixer devices 44, 45 are fed to first 46 and second 44 analog-to-digital converters (here shown as 14-bit ADCs), each of which ADC also receives a clock input to clock the ADCs from system clock 49.
  • each of the two ADCs 46, 47 are digitized versions or representations of the in-phase and quadrature-phase signals which are then fed to the DSP circuits 51, 52 for use in DSP demodulation.
  • the inventive mixer may be used for both up- and down-conversion in the same system, thereby providing structure and method for a software radio having both transmit and receive (transceiver) capabilities.
  • the inventive topology has several advantages over conventional heterodyne converter, including elimination of a conversion stage, elimination of the final amplifier to the ADC, requires only one-half the ADC needed bandwidth by digitizing analog I and Q signals, providing about 40 dB more dynamic range than conventional converters.
  • the inventive structure and method achieves at least about +50 dBm IP3 and +100 dBm IP2 as a baseband converter that will directly drive state-of-the-art 14-bit ADCs for example, the Analog Devices AD6644 made by Analog Devices, Inc. with 65 MSPS conversion rates as well as the narrower bandwidth 16-bit ADCs.
  • the combination of the inventive mixer 32 and high-performance ADC 46 places all spurious responses at 100 dB or below full scale over a 30 MHz or greater bandwidth.
  • the mixer 32 provides a near perfect first stage converter having high dynamic range and insertion loss approaching theoretical insertion loss limits.
  • FIG. 28 there is shown an illustration of functional block diagram of an exemplary embodiment of an Automatic Link Establishment system incorporating the inventive radio topology and super-mixer.
  • the system includes an antenna for receiving a RF signal from a remote site, a tunable down converter including one of the inventive super-mixer devices for generating a tuner output signal.
  • This output signal is then digitized by the ADC as already described and then passed to a DSP for further processing.
  • a computer having a processor (CPU) memory connected to the processor for storing data and procedures, and further including a terminal device, display, bulk storage, and one or more input/output devices as is commonly known in the art.
  • the memory is partitioned and defines a data structure of the procedures and data stored therein. Workers having ordinary skill in the art will appreciate that a transmit configuration for the ALE may be provided in analogous manner and is not described further here.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)
  • Transmitters (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Claims (38)

  1. Funkgerät, umfassend:
    einen Empfangsoszillator-Eingangskanal (120) zum Empfangen eines periodischen sinusförmigen Empfangsoszillatorsignals bei einer Empfangsoszillatorfrequenz von einer externen Empfangsoszillatorquelle; eine Mischvorrichtung (32);
    eine Ansteuerungsschaltung (37) zum Erzeugen eines im Wesentlichen rechteckwellenförmigen Zweispannungspegel-Schaltsignals zum Ansteuern der Mischvorrichtung; wobei die Ansteuerungsschaltung ferner enthält:
    (i) mit dem Empfangsoszillator-Eingangskanal (120) gekoppelte Phasentellermittel (38) zum Empfangen des periodischen sinusförmigen Empfangsoszillatorsignals und zum Erzeugen eines ersten und eines zweiten phasengetrennten Signals bei der Empfangsoszillatorfrequenz, welche zueinander einen Phasenunterschied von im Wesentlichen 180° aufweisen;
    (ii) Spannungspotential-Isolationsmittel (39) zum Erzeugen jeweils eines ersten und eines zweiten Differenzsignalpaars bei der Empfangsoszillatorfrequenz von dem ersten und dem zweiten phasengetrennten Signal; und
    (iii) Rechtecksignalerzeugungsmittel (40) zum Erzeugen jeweils eines ersten und eines zweiten schwebenden Rechtecksignals von dem ersten und dem zweiten Differenzsignalpaar, wobei jedes der Rechtecksignale eine vordere und eine hintere Signalflanke mit hoher Anstiegs-/abfallgeschwindigkeit aufweist; und
    ein Eingangs-/Ausgangssignal-Trennmittel (33);
       wobei die Mischvorrichtung (32) eine erste und eine zweite Schaltvorrichtung (36) enthält, zum Multiplizieren eines Eingangssignals erster Frequenz mit dem ersten und dem zweiten schwebenden Rechtecksignal, um ein Mischer-Ausgangssignal dritter Frequenz zu erzeugen, wobei die erste und die zweite Schaltvorrichtung (36) mit der Ansteuerungsschaltung (37) gekoppelt sind, um das erste und das zweite schwebende Rechtecksignal an den Schaltvorrichtungen (36) zu empfangen, so dass eine aus erster und zweiter Schaltvorrichtung (36) exakt dann auf EIN schaltet, wenn die andere aus erster und zweiter Schaltvorrichtung (36) auf AUS schaltet;
       wobei die Eingangs-/Ausgangssignal-Trennmittel (33) zum Trennen des Mischer-Ausgangssignals dritter Frequenz von dem Eingangssignal erster Frequenz und zum Leiten des Ausgangssignals an einen Ausgangskanal vorgesehen ist.
  2. Funkgerät nach Anspruch 1, in welchem die Mischvorrichtung (32) in dem Empfangsabschnitt des Funkgeräts vorgesehen ist und als Abwärtsfrequenzumsetzer (700) arbeitet.
  3. Funkgerät nach Anspruch 1, in welchem die Mischvorrichtung (32) in dem Sendeabschnitt des Funkgeräts vorgesehen ist und als Aufwärtsfrequenzumsetzer (600) arbeitet.
  4. Funkgerät nach einem beliebigen vorhergehenden Anspruch, wobei das Funkgerät ein Heterodyn-Funkgerät ist.
  5. Funkgerät nach einem beliebigen der Ansprüche 1 bis 3, wobei das Funkgerät ein Homodyn-Funkgerät ist.
  6. Funkgerät nach einem beliebigen vorhergehenden Anspruch, welches ferner einen Analog-Digital-Wandler umfasst, der mit dem Ausgangskanal gekoppelt ist, um das Ausgangssignal zu empfangen und eine digitale Entsprechung des Analogmischer-Ausgangssignals dritter Frequenz zu erzeugen.
  7. Funkgerät nach Anspruch 6, in welchem das Funkgerät das Mischerausgangssignal mit einer Ausgangsleistung im Bereich von ungefähr 0,005 Milliwatt bis ungefähr 0,1 Milliwatt bereitstellt, so dass keine weitere Verstärkung nötig ist, um dem Analog-Digital-Wandler die benötigte Leistung bereitzustellen.
  8. Funkgerät nach einem beliebigen vorhergehenden Anspruch, in welchem das Rechtecksignal-Erzeugungsmittel (40) eine bistabile Schaltung umfasst, welche ein Logikgatter (310, 312) enthält, das einen ersten und einen zweiten Ausgangs-Logikpegel aufweist, und welche eine im Wesentlichen konstante erste Amplitudenausgabe in Antwort auf den Empfang einer ersten Eingabe mit einer ersten Eingangsspannungsamplitude im Bereich zwischen einer Spannungsamplitude S1 und einer Spannungsamplitude S2 erzeugt und eine von der ersten Spannungsamplitude verschiedene, zweite im wesentlichen konstante Spannungsarnplitudenausgabe in Antwort auf den Empfang einer zweiten Eingabe mit einer zweiten Eingangsspannungsamplitude im Bereich zwischen einer Spannungsamplitude S3 und einer Spannungsamplitude S4 erzeugt.
  9. Funkgerät nach Anspruch 8, in welchem das Logikgatter (310, 312) ausgewählt ist aus der Gruppe von Gattern, welche besteht aus: UND, NICHT-UND, ODER, NICHT-ODER, EXKLUSIV-ODER, EXKLUSIV-NICHT-ODER und Kombinationen dieser.
  10. Funkgerät nach einem der Ansprüche 8 und 9, in welchem das Logikgatter (310, 312) ein UND-Gatter umfasst.
  11. Funkgerät nach einem beliebigen der Ansprüche 8 bis 10, in welchem die Schalterschaltung eine Mehrzahl von FET's umfasst.
  12. Funkgerät nach einem beliebigen der Ansprüche 8 bis 11, in welchem die Mischvorrichtung (32) eine Mehrzahl von GaAs-FET's umfasst.
  13. Funkgerät nach einem beliebigen der Ansprüche 8 bis 12, in welchem das Logikgatter (310, 312) eine phasenkomplementäre Wellenform erzeugt und in welchem keine Trennungssymmetrieschaltung notwendig ist.
  14. Funkgerät nach einem beliebigen der Ansprüche 8 bis 13, in welchem die Schaltvorrichtung zwei Paare von serieil Quelle-an-Quellegeschalteten FET's umfasst.
  15. Funkgerät nach einem beliebigen der Ansprüche 8 bis 14, in welchem das Eingangssignal ein Hochfrequenz- (RF-) -signal ist und das Ausgangssignal ein Zwischenfrequenz- (IF-) ―signal ist.
  16. Funkgerät nach einem beliebigen der Ansprüche 8 bis 14, in welchem das Eingangssignal ein Zwischenfrequenz- (IF-) ―signal und das Ausgangssignal ein Hochfrequenz- (RF-) ―signal ist.
  17. Funkgerät nach Anspruch 1, in welchem das Rechtecksignalerzeugungsmittel (40) eine bistabile Schaltung umfasst, welche eine im Wesentlichen konstante erste Amplitudenausgabe in Antwort auf den Empfang einer ersten Eingabe mit einer ersten Eingangspannungsamplitude im Bereich zwischen ungefähr -0,5 V und ungefähr +0,5 V erzeugt und eine von der ersten Spannungsamplitude verschiedene, zweite im Wesentlichen konstante Spannungsamplitudenausgabe in Antwort auf den Empfang einer zweiten Eingabe mit einer zweiten Eingangsspannungsamplitude im Bereich zwischen ungefähr 3,5 V und ungefähr 6 V erzeugt.
  18. Funkgerät nach Anspruch 1, in welchem das Mischerausgangssignal ein analoges Mischerausgangssignal ist.
  19. Funkgerät nach einem beliebigen vorhergehenden Anspruch, ferner umfassend einen Abstimmer, welcher enthält:
    eine Niedrigband-Signalverarbeitungsschaltung, welche erste Komponenten eines RF-Eingangssignals über einen ersten Frequenzbereich ohne Frequenzumwandlung direkt empfängt und verarbeitet, um ein Niedrigband-Ausgabesignal zu erzeugen;
    eine Hochband-Signalverarbeitungsschaltung, welche zweite Komponenten des RF-Eingangssignals über einen zweiten Frequenzbereich unter Ausführung einer Frequenzumwandlung der zweiten Komponenten empfängt und verarbeitet, um ein Hochband-Ausgabesignal zu erzeugen;
    eine Signalkombinierschaltung, welche das Niedrigband-Ausgangssignal und das Hochband-Ausgangssignal empfängt und ein zusammengesetztes Ausgangssignal erzeugt; und
    eine Ausgangsverarbeitungsschaltung, welche das zusammengesetzte Ausgangssignal empfängt und das zusammengesetzte Ausgangssignal verstärkt, impedanztransformiert und filtert, um ein analoges Endausgangssignal zu erzeugen.
  20. Funkgerät nach Anspruch 19, in welchem die Hochband-Signalverarbeitungsschaltung umfasst:
    (i) eine als Aufwärtsfrequenzumsetzer arbeitende erste Mischschaltung, welche die Komponenten des zweiten Frequenzbereichs und ein erstes Empfangsoszillatorsignal empfängt und ein erstes Zwischenfrequenzsignal erzeugt;
    (ii) eine Schaltung, welche das erste Zwischenfrequenzsignal verstärkt und einer Bandpassfilterung unterzieht, um ein zweites Zwischenfrequenzsignal zu erzeugen; und
    (iii) eine als Abwärtsfrequenzumsetzer arbeitende zweite Mischschaltung, welche das zweite Zwischenfrequenzsignal und ein zweites Empfangsoszillatorsignal empfängt und das Hochband-Ausgangssignal erzeugt.
  21. Funkgerät nach Anspruch 19 oder Anspruch 20, ferner umfassend eine Analog-Digital-Wandlerschaltung, welche zum Empfangen des analogen Endausgabesignals von der Ausgangsverarbeitungsschaltung angeschlossen ist und ein das analoge Endausgabesignal repräsentierendes digitales Ausgabesignal erzeugt.
  22. Funkgerät nach Anspruch 21, in welchem die Analog-Digital-Wandlerschaltung einen Analog-Digital-Wandler umfasst, welcher eine Auflösung von wenigstens 14 Bit aufweist, um pro Bit des Analog-DigitalWandlers einen Dynamikbereich von ungefähr 6 dB bis ungefähr 9 dB bereitzustellen.
  23. Funkgerät nach einem beliebigen der Ansprüche 19 bis 22, ferner umfassend eine RF-Signaleingangsverarbeitungsschaltung, weiche das RF-Signal von einer externen Quelle empfängt und die ersten RF-Signalkomponenten bzw. die zweiten RF-Signalkomponenten erzeugt und diese jeweils an die Niedrigband- und die Hochband-Signalverarbeitungsschaltungen koppelt.
  24. Funkgerät nach einem beliebigen der Ansprüche 19 bis 23, in welchem der Abstimmer über einem Frequenzbereich von wenigstens ungefähr 0,1 MHz bis ungefähr 32 MHz arbeitet.
  25. Funkgerät nach einem beliebigen der Ansprüche 19 bis 24, in welchem der erste Frequenzbereich im Wesentlichen Frequenzen bis ungefähr 4 MHz abdeckt und der zweite Frequenzbereich im Wesentlichen Frequenzen oberhalb von ungefähr 4 MHz abdeckt.
  26. Funkgerät nach einem beliebigen der Ansprüche 19 bis 25, in welchem der erste Frequenzbereich im Wesentlichen Frequenzen von ungefähr 1 MHz bis ungefähr 4 MHz abdeckt und der zweite Frequenzbereich im Wesentlichen Frequenzen von ungefähr 4 MHz bis ungefähr 32 MHz abdeckt.
  27. Funkgerät nach einem beliebigen der Ansprüche 19 bis 26, in welchem der Abstimmer über einer Bandbreite von 4 MHz einen verzögerungsfreien, störfreien Dynamikbereich von mehr als 95 dB bereitstellt.
  28. Funkgerät nach einem beliebigen der Ansprüche 19 bis 26, in welchem der Abstimmer über einer Bandbreite von 8 MHz einen verzögerungsfreien, störfreien Dynamkibereich von mehr als 95 dB bereitstellt.
  29. Funkgerät nach einem beliebigen der Ansprüche 19 bis 28, in welchem der Abstimmer einen Außerband-IP3 von wenigstens ungefähr +40 dBm und einen Außerband-IP2 von wenigstens ungefähr +80 dBm sowie einen Gesamtdynamikbereich von wenigstens ungefähr 95 dB erreicht.
  30. Funkgerät nach einem beliebigen der Ansprüche 19 bis 29, in welchem das erste Zwischenfrequenzsignal bei einer Mittelfrequenz von ungefähr 70 MHz liegt.
  31. Funkgerät nach einem beliebigen der Ansprüche 19 bis 30, in welchem der Verstärker der Ausgangsverarbeitungsschaltung eine geringe Restausgabe zeigt, sodass irgendwelche, durch den Verstärker eingebracht Restausgaben den störfreien Dynamikbereich (SFDR) des Abstimmers nicht signifikant begrenzen.
  32. Funkgerät nach Anspruch 20, in welchem die erste Mischerschaltung umfasst:
    einen ersten Empfangsoszillator-Eingangskanal zum Empfangen des ersten Empfangsoszillatorsignals, wobei das erste Empfangsoszillatorsignal ein erstes sinusförmiges Empfangsoszillatorsignal bei einer ersten Empfangsoszillatorfrequenz umfasst;
    eine mit dem ersten Empfangsoszillator-Eingangskanal gekoppelte erste Phasentrennschaltung zum Empfangen des ersten Empfangsoszillatorsignals und zum Erzeugen eines ersten und eines zweiten phasengetrennten Signals bei der ersten Empfangsoszillatorfrequenz, welche zueinander einen Phasenunterschied von im Wesentlichen 180° aufweisen;
    eine erste Spannungspotential-Isolationsschaltung zum Erzeugen jeweils eines ersten und eines zweiten Differenzsignalpaares bei der ersten Empfangsoszillatorfrequenz aus dem ersten dem zweiten phasengetrennten Signal;
    eine Rechtecksignal-Erzeugungsschaltung, welche jeweils eine erste und eine zweite schwebende Rechteckwelle von dem ersten und dem zweiten Differenzsignalpaar erzeugt, wobei jedes Rechteckwellensignal vordere und hintere Signalflanken mit hoher Anstiegs-/abfallgeschwindigkeit mit Anstiegs- und Abfallzeiten von weniger als ungefähr 300 Picosekunden aufweist;
    eine erste Frequenzmischvorrichtung, welche das erste und das zweite Rechtecksignal sowie die Komponenten des zweiten Frequenzbereichs empfängt und das erste Zwischenfrequenzsignal erzeugt; und
    eine erste Eingabe-/Ausgabesignal-Trennschaltung zum Trennen des ersten Zwischenfrequenzausgangssignals von dem Eingangssignal der Komponenten des zweiten Frequenzbereichs und zum Leiten des ersten Zwischenfrequenzausgangssignals zu einem ersten Ausgangskanal.
  33. Funkgerät nach Anspruch 32, in welchem die zweite Mischerschaltung umfasst:
    einen zweiten Empfangsoszillator-Eingangskanal zum Empfangen des zweiten Empfangsoszillatorsignals, wobei das zweite Empfangsoszillatorsignal ein zweites sinusförmiges Empfangsoszilletorsignal bei einer zweiten Empfangsoszillatorfrequenz umfasst;
    eine mit dem zweiten Empfangsoszillator-Eingangskanal gekoppelte zweite Phasentrennschaltung zum Empfangen des zweiten Empfangsoszillatorsignals und zum Erzeugen eines dritten und eines vierten phasengetrennten Signals bei der zweiten Empfangsoszillatorfrequenz, welche zueinander einen Phasenunterschied von im Wesentlichen 180° aufweisen;
    eine zweite Spannungspotential-Isolationsschaltung zum Erzeugen jeweils eines dritten und eines vierten Differenzsignalpaares bei der zweiten Empfangsoszillatorfrequenz aus dem dritten und dem vierten phasengetrennten Signal;
    eine zweite Rechtecksignal-Erzeugungsschaltung, welche eine dritte und eine vierte schwebende Rechteckwelle aus dem dritten bzw. vierten Differerizsignalpaar erzeugt, wobei jedes Rechtecksignal eine vordere und hintere Signalflanke mit hoher Anstiegs-/abfallgeschwindigkeit mit Anstiegs- und Abfallszeiten von weniger als ungefähr 300 Picosekunden aufweist;
    eine zweite Frequenzmischvorrichtung, welche das dritte und das vierte Rechtecksignal und das zweite Zwischenfrequenzsignal empfängt und das Hochband-Ausgabesignal erzeugt;
    eine zweite Eingangs-/Ausgangssignal-Trennschaltung zum Trennen des Hochband-Ausgangssignal von dem zweiten Zwischenfrequenzsignal-Eingangssignal und zum Weiterleiten des Hochband-Ausgangssignals an einen zweiten Ausgangskanal.
  34. Funkvorrichtungsabstimmer nach Anspruch 33, in welchem die erste und die zweite Frequenzmischvorrichtung jeweils ein Paar von FETs umfassen, wobei jedes der ersten, zweiten, dritten und vierten Rechtecksignale eine schnell ansteigende/abfallende vordere und hintere Signalflanke mit Anstiegs- und Abfallszeiten von weniger als ungefähr 300 Picosekunden aufweist, sodass einer der FET's jedes Paars exakt dann auf EIN schaltet, wenn der andere der FET's des Paares auf AUS schaltet.
  35. Funkgerät nach Anspruch 1, in welchem vorderen und hinteren Signalflanken mit hoher Anstiegs-/abfallgeschwindigkeit Anstiegs- und Abfallszeiten von weniger als ungefähr 300 Picosekunden sind.
  36. Funkgerät nach Anspruch 1, in welchem die erste und die zweite Schaltvorrichtung (36) eine erste und eine zweite Transistorschaltvorrichtung umfassen.
  37. Funkgerät nach Anspruch 1, in welchem die erste und die zweite Schaltvorrichtung (36) eine erste und eine zweite FET-Schaltvorrichtung umfassen.
  38. Funkgerät nach Anspruch 1, in welchem das Funkgerät, welches das Ausgangssignal bereitstellt, eine Ausgangsleistung im Bereich von ungefähr 0,005 Milliwatt bis ungefähr 0,1 Milliwatt aufweist, sodass keine weitere Verstärkung notwendig ist, um die benötigte Übertragungsleistung bereitszustellen.
EP99905547A 1998-02-01 1999-01-29 Funksystem und -verfahren mit fet-mischer und rechteckspannungsgetriebener schalterschaltung Expired - Lifetime EP0972336B1 (de)

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US16629 1998-02-01
US09/016,629 US6108529A (en) 1998-02-01 1998-02-01 Radio system including FET mixer device and square-wave drive switching circuit and method therefor
PCT/US1999/001986 WO1999039431A1 (en) 1998-02-01 1999-01-29 Radio system including fet mixer device and square-wave drive switching circuit and method therefor

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CA2285563C (en) 2005-11-01
DE69926182T2 (de) 2006-05-24
US6108529A (en) 2000-08-22
JP2001525149A (ja) 2001-12-04
EP0972336A1 (de) 2000-01-19
ATE300120T1 (de) 2005-08-15
WO1999039431A1 (en) 1999-08-05
AU758341B2 (en) 2003-03-20
CA2285563A1 (en) 1999-08-05
US6654595B1 (en) 2003-11-25
AU2568699A (en) 1999-08-16

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