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EP0931352A1 - Gate-controlled thyristor - Google Patents

Gate-controlled thyristor

Info

Publication number
EP0931352A1
EP0931352A1 EP98945056A EP98945056A EP0931352A1 EP 0931352 A1 EP0931352 A1 EP 0931352A1 EP 98945056 A EP98945056 A EP 98945056A EP 98945056 A EP98945056 A EP 98945056A EP 0931352 A1 EP0931352 A1 EP 0931352A1
Authority
EP
European Patent Office
Prior art keywords
thyristor
cell
zone
thyristor according
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98945056A
Other languages
German (de)
French (fr)
Inventor
Jenö Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19732912A external-priority patent/DE19732912C2/en
Priority claimed from DE19739498A external-priority patent/DE19739498C1/en
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0931352A1 publication Critical patent/EP0931352A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/131—Thyristors having built-in components
    • H10D84/138—Thyristors having built-in components the built-in components being FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/40—Thyristors with turn-on by field effect 

Definitions

  • the present invention relates to a gate controlled
  • Thyristor such as a cascode MOS thyristor in which an IGBT (Insulated Gate Bipolar Transistor) le in a first cell h ⁇ and a thyristor are connected in the main cell so that the first cell and the main cell a late- ral-FET with a channel of the first conductivity type.
  • IGBT Insulated Gate Bipolar Transistor
  • Such a cascode MOS thyristor was proposed many years ago (DE-A-30 24 015) and has recently been put up for discussion again as “MCCT” (MOS Controlled Cascode Thyristor) (cf. the report “1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor "by N. Iwamuro, T. Iwaana, Y. Harada and Y. Seki at the ISPSD 97 conference).
  • MCCT MOS Controlled Cascode Thyristor
  • Such a cascode MOS thyristor like general MOS-controlled bipolar structures, such as IGBTs and MCTs (MOS Controlled Thyristor), is preferred over MOSFETs due to its relatively low on-resistance.
  • Known ⁇ Lich to generally lock a very high voltage switch, but when they are switched on or conductive, have a very low resistance.
  • the main cell A consists in particular of an anode electrode 1, a p- (or p + -) conductive zone 2, an n-conductive base zone 3, a p-conductive base zone 5 with an edge 5 'and an n-conductive emitter zone 9 with a Edge 9 '.
  • An insulator layer 8 made of, for example, silicon dioxide is arranged on the emitter zone 9.
  • the first cell B has a gate contact 10 with an edge 10 'of polysilicon, an n + -le ⁇ tende zone 11 with a Kan ⁇ te 11', a p-type region 6 with an edge 6 'and a contact 12 and forms a first IGBT.
  • the second cell C has a gate contact 13 with an edge 13 'made of polycrystalline silicon, an n + -doped zone 14 with an edge 14', a p-doped zone 4 with an edge 4 'and a contact 7 made of aluminum, for example forms a second IGBT.
  • the IGBTs are thus in contact with the cathode electrode, while the thyristor has a channel zone, but has no cathode contact.
  • This cascode MOS thyristor is relatively low, while it can block a high voltage after the gate voltage has been switched off.
  • a gate controlled thyristor which auszeich by a particularly low on- ⁇ net
  • a charge carrier-recombination-enhancing layer devised in a cascode MOS thyristor of the type mentioned in the emitter region m of the thyristor
  • This layer can consist of a metal or silicide, such as aluminum, titanium silicide, etc.
  • a second cell with egg ⁇ nem MOS switch may be connected forming a FET having a channel of the second conductivity type with the main cell.
  • the thyristor cathode When the gate voltage is positive (see FIG. 8), the thyristor cathode is grounded, so that the on-resistance is extremely small. 0 V or a negative gate voltage to, the first cell as the lateral and vertical FET (field effect transistor) is turned off, while the second cell than in ⁇ play, p-channel FET conducts and no current flows.
  • the individual cells can, for example, be arranged next to one another in strips. It is also possible the first
  • the dimensions for the cells can be selected as desired, and only the first cell can be provided together with the main cell.
  • an insulator layer Under the first cell and the second cell can ⁇ given if an insulator layer are positioned, which provides n-conductive for a better flooding of the particular base region with carriers, thereby switching resistor for an even smaller Em-.
  • This insulator layer can optionally extend as far as the p-type base zone of the thyristor or the main cell. In this case, when the insulator layer reaches the p-type base region, there should be an opening in this to increase the effectiveness of the IGBT.
  • An advantage of the present invention is that a gate controlled thyristor can be created, the FETs of which can be designed practically as desired, so that they can be adapted to a wide variety of applications.
  • At least one trench, in which an insulated gate electrode is provided, is introduced into the lateral FET.
  • At least one trench with a gate electrode is advantageously also introduced into the FET of the second cell.
  • the gate-controlled thyristor according to the invention is simple to produce using customary method steps and is even superior to the existing cascode MOS thyristor in terms of its conductivity, since its side wall FETs formed by the trenches have a large channel area.
  • FIG. 1 shows a section through a first exemplary embodiment of the thyristor according to the invention
  • FIG. 5 shows a section through a fourth exemplary embodiment of the thyristor according to the invention, 6 shows a schematic top view of the trench structure,
  • FIG. 8 shows a section through a conventional cascode MOS thyristor.
  • Fig. 1 shows em first exemplary embodiment of the present invention with a gate-controlled thyristor, which has a very low on resistance.
  • the n-type emitter zone 9 is arranged with a layer 15 made of a metal or silicide, such as aluminum or titanium silicide, which increases the charge carrier recombination. If necessary, other silicides or general materials can be selected for this, which increase the recombination rate of the charge carriers.
  • the gate-controlled thyristor m is constructed in a similar manner to the thyristor of FIG. 8, although the IGBT m of the second cell C has no n + -doped zone 14, so that the edge 14 'is also omitted here.
  • Cell B is therefore a normal IGBT source cell with the n -doped zone 11m of the p-doped zone 6 forming a well.
  • the second cell C has no n * in the p-doped zone 4. -dot ⁇ erte zone.
  • the first cell B and the main cell A thus form an n-channel lateral FET, while the second cell C and
  • Main cell A represent a p-channel FET.
  • the epitaxially grown n-type base region 3 and / or the entire structure may be fully or partially filled with a service life Le ⁇ killer, he testified be ⁇ crystal defects doped by irradiation such as gold, platinum or the like.
  • the lateral FETs with trenches 20 filled with insulated gate electrodes are introduced, as can be seen from the top view of FIG. 6; these trenches 20, which are arranged at a distance from one another perpendicular to the plane of the drawing in FIG. 1, permit virtually any configuration of the two FETs (cf. FIG. 7) and ensure a large channel area.
  • the edge 14 ' (shown in broken lines in FIG. 6) is only present if the layer 14 is additionally introduced in the layer 4, as in FIG. 8.
  • an insulator layer 16 can be provided below the two cells B and C, that is to say below the p-type zones 6 and 4, but does not extend as far as the p-type base zone 5, as shown in FIG 2 is shown.
  • This insulator layer 16 ensures an even better “flooding” of the n-conducting zone 3 with charge carriers, which further lowers the switch-on resistance .
  • the "deleted" reference numerals for the respective edges are partially omitted in FIGS. 4 and 5 for the sake of clarity.
  • the insulator layers 16 can extend as far as the p-conducting base zone 5 and in some cases even cover it. In this case, however, m of the p-base zone 5 an opening 17 to be present to the IGBT effect of
  • intermediate zones 19 are relatively weakly doped and either n- or p-conductive.
  • Fig. 5 shows another embodiment of the Invention ⁇ proper gate controlled thyristor, is provided in which a metal layer 18 above the n ⁇ -type emitter zone 9 on the layer 15.
  • FIG. 3 An equivalent circuit diagram for the gate-controlled thyristor of the above exemplary embodiments is shown in FIG. 3. If the gate voltage at gate G is positive, the thyristor cathode is grounded so that the on-resistance is low. However, if there is 0 V or a negative voltage at gate G, the first cell B is switched off as a lateral and vertical FET, while the second cell C is conducting as a p-channel FET and no current flows.
  • the trench 20 is “filled” in the usual way with an insulated gate electrode, for which purpose suitable materials (for example polysilicon as gate electrode, SiO 2 as gate insulator, etc.) can be used.
  • suitable materials for example polysilicon as gate electrode, SiO 2 as gate insulator, etc.
  • the side wall of the trench 20 acts as a channel region of a MOSFET.
  • the invention thus enables a gate-controlled thyristor which has an extremely low on-resistance and is nevertheless able to block high voltages.

Landscapes

  • Thyristors (AREA)

Abstract

In a gated thyristor, an IGBT in a first cell (B) and a thyristor in a main cell (A) are interconnected in such a way that the first cell (B) and the main cell (A) form a lateral FET with a channel of the first conductivity type. A layer (15) for increasing charge carrier recombination is embedded in the emitter zone of the thyristor to reduce the switching-on resistance of the gated thyristor. Pits (20) filled with insulated gate electrodes can be provided in the lateral FET, so that the lateral FET is designed as a side wall FET.

Description

Beschreibungdescription

Gate-gesteuerter ThyristorGate controlled thyristor

Die vorliegende Erfindung betrifft einen Gate-gesteuertenThe present invention relates to a gate controlled

Thyristor, wie z.B. einen Kaskoden-MOS-Thyristor, bei dem ein IGBT (Insulated Gate Bipolar Transistor) in einer ersten Zel¬ le und ein Thyristor in einer Hauptzelle so zusammengeschaltet sind, daß die erste Zelle und die Hauptzelle einen Late- ral-FET mit einem Kanal des ersten Leitfähigkeitstyps bilden.Thyristor, such as a cascode MOS thyristor in which an IGBT (Insulated Gate Bipolar Transistor) le in a first cell h ¬ and a thyristor are connected in the main cell so that the first cell and the main cell a late- ral-FET with a channel of the first conductivity type.

Ein derartiger Kaskoden-MOS-Thyristor wurde bereits vor vielen Jahren vorgeschlagen (DE-A-30 24 015) und ist in letzter Zeit erneut als "MCCT" (MOS Controlled Cascode Thyristor) zur Diskussion gestellt worden (vgl. den Bericht "1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor" von N. Iwamu- ro, T. Iwaana, Y. Harada und Y. Seki auf der Konferenz ISPSD 97). Ein solcher Kaskoden-MOS-Thyristor ist wie auch allgemein MOS-gesteuerte Bipolarstrukturen, wie IGBTs und MCTs (MOS Controlled Thyristor) , infolge seines relativ kleinen Einschaltwiderstandes gegenüber MOSFETs bevorzugt. Bekannt¬ lich sollen Schalter ganz allgemein eine möglichst hohe Spannung sperren, jedoch dann, wenn sie eingeschaltet bzw. leitend sind, einen möglichst geringen Widerstand aufweisen.Such a cascode MOS thyristor was proposed many years ago (DE-A-30 24 015) and has recently been put up for discussion again as "MCCT" (MOS Controlled Cascode Thyristor) (cf. the report "1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor "by N. Iwamuro, T. Iwaana, Y. Harada and Y. Seki at the ISPSD 97 conference). Such a cascode MOS thyristor, like general MOS-controlled bipolar structures, such as IGBTs and MCTs (MOS Controlled Thyristor), is preferred over MOSFETs due to its relatively low on-resistance. Known ¬ Lich to generally lock a very high voltage switch, but when they are switched on or conductive, have a very low resistance.

Fig. 8 zeigt einen Kaskoden-MOS-Thyristor als Stand der Technik mit einer Hauptzelle A, einer ersten Zelle B und einer zweiten Zelle C, wobei die Zellen B und C streifenförmig auf den beiden Seiten der Zelle A angeordnet sind. Die Hauptzelle A besteht insbesondere aus einer Anodenelektrode 1, einer p- (oder p+-) leitenden Zone 2, einer n-leitenden Basiszone 3, einer p-leitenden Basiszone 5 mit einer Kante 5' und einer n- leitenden Emitterzone 9 mit einer Kante 9' . Auf der Emitterzone 9 ist eine Isolatorschicht 8 aus beispielsweise Silizi- umdioxid angeordnet. Die erste Zelle B weist einen Gatekontakt 10 mit einer Kante 10' aus Polysilizium, eine n+-leιtende Zone 11 mit einer Kan¬ te 11', eine p-leitende Zone 6 mit einer Kante 6' und einen Kontakt 12 auf und bildet einen ersten IGBT.8 shows a cascode MOS thyristor as prior art with a main cell A, a first cell B and a second cell C, the cells B and C being arranged in strips on both sides of the cell A. The main cell A consists in particular of an anode electrode 1, a p- (or p + -) conductive zone 2, an n-conductive base zone 3, a p-conductive base zone 5 with an edge 5 'and an n-conductive emitter zone 9 with a Edge 9 '. An insulator layer 8 made of, for example, silicon dioxide is arranged on the emitter zone 9. The first cell B has a gate contact 10 with an edge 10 'of polysilicon, an n + -leιtende zone 11 with a Kan ¬ te 11', a p-type region 6 with an edge 6 'and a contact 12 and forms a first IGBT.

Die zweite Zelle C weist einen Gatekontakt 13 mit einer Kante 13' aus polykristallmem Silizium, eine n+-dotιerte Zone 14 mit einer Kante 14', eine p-dotierte Zone 4 mit einer Kante 4' und einen Kontakt 7 aus beispielsweise Aluminium auf und bildet einen zweiten IGBT.The second cell C has a gate contact 13 with an edge 13 'made of polycrystalline silicon, an n + -doped zone 14 with an edge 14', a p-doped zone 4 with an edge 4 'and a contact 7 made of aluminum, for example forms a second IGBT.

Bei diesem Kaskoden-MOS-Thyristor sind also die IGBTs mit der Kathodenelektrode kontaktiert, wahrend der Thyristor eine Ka- nalzone aufweist, jedoch keinen Kathodenkontakt hat. DerIn this cascode MOS thyristor, the IGBTs are thus in contact with the cathode electrode, while the thyristor has a channel zone, but has no cathode contact. The

Strom wird durch Anlegen einer Gatespannung an den Kontakt 10 bzw. 13 gesteuert, um so sowohl die Kanalzone des Thyristors als auch die Kanalzone der IGBTs zu offnen. Der Einschaltwiderstand dieses Kaskoden-MOS-Thyristors ist relativ niedrig, wahrend er nach Abschalten der Gate-Spannung eine hohe Spannung zu sperren vermag.Current is controlled by applying a gate voltage to contacts 10 and 13, respectively, so as to open both the thyristor channel zone and the IGBTs channel zone. The turn-on resistance of this cascode MOS thyristor is relatively low, while it can block a high voltage after the gate voltage has been switched off.

Es ist nun Aufgabe der vorliegenden Erfindung, einen Gategesteuerten Thyristor zu schaffen, der sich durch einen be- sonders niedrigen Einschaltwiderstand auszeichnet.It is an object of the present invention to provide a gate-controlled thyristor which is distinguished by a particularly low on-resistance.

Diese Aufgabe wird bei einem Gate-gesteuerten Thyristor nach dem Oberbegriff des Patentanspruches 1 erfmdungsgemaß durch die m dessen kennzeichnendem Teil enthaltenen Merkmale ge- lost.This object is achieved in a gate-controlled thyristor according to the preamble of claim 1 according to the invention by the features contained in the characterizing part thereof.

Vorteilhafte Weiterbildungen der Erfindung ergeben sich aus den Unteranspruchen. Um einen Gate-gesteuerten Thyristor zu schaffen, der sich durch einen besonders niedrigen Einschaltwiderstand auszeich¬ net, wird vorgeschlagen, bei einem Kaskoden-MOS-Thyristor der eingangs genannten Art m der Emitterzone des Thyristors eine die Ladungsträger-Rekombination erhöhende Schicht einzubet¬ ten. Diese Schicht kann aus einem Metall oder Silizid, wie beispielsweise Aluminium, Titansilizid usw. bestehen. Außerdem kann neben der Hauptzelle noch eine zweite Zelle mit ei¬ nem MOS-Schalter verbunden sein, die mit der Hauptzelle einen FET mit einem Kanal des zweiten Leitfahigkeitstyps bildet.Advantageous developments of the invention result from the subclaims. In order to provide a gate controlled thyristor, which auszeich by a particularly low on-¬ net, it is proposed in a cascode MOS thyristor of the type mentioned in the emitter region m of the thyristor, a charge carrier-recombination-enhancing layer einzubet ¬ th. This layer can consist of a metal or silicide, such as aluminum, titanium silicide, etc. Moreover, in addition to the main cell is a second cell with egg ¬ nem MOS switch may be connected forming a FET having a channel of the second conductivity type with the main cell.

Bei positiver Gatespannung (vgl. Fig. 8) ist die Thyristorkathode geerdet, so daß der Durchlaßwiderstand extrem klein ist. Liegen 0 V oder eine negative Gatespannung an, so ist die erste Zelle als Lateral- und Vertikal-FET (Feldeffekttransistor) abgeschaltet, wahrend die zweite Zelle als bei¬ spielsweise p-Kanal-FET leitet und kein Strom fließt.When the gate voltage is positive (see FIG. 8), the thyristor cathode is grounded, so that the on-resistance is extremely small. 0 V or a negative gate voltage to, the first cell as the lateral and vertical FET (field effect transistor) is turned off, while the second cell than in ¬ play, p-channel FET conducts and no current flows.

Die einzelnen Zellen können beispielsweise streifenformig ne- benemander angeordnet sein. Auch ist es möglich, die ersteThe individual cells can, for example, be arranged next to one another in strips. It is also possible the first

Zelle und die zweite Zelle konzentrisch um die Hauptzelle anzuordnen. Die Abmessungen für die Zellen sind beliebig wahlbar, wobei auch nur die erste Zelle zusammen mit der Hauptzelle vorgesehen werden kann.Cell and the second cell concentrically to arrange the main cell. The dimensions for the cells can be selected as desired, and only the first cell can be provided together with the main cell.

Unter der ersten Zelle und der zweiten Zelle kann gegebenen¬ falls eine Isolatorschicht angeordnet werden, was für eine bessere Überflutung der insbesondere n-leitenden Basiszone mit Ladungsträgern und dadurch für einen noch kleineren Em- schaltwiderstand sorgt. Diese Isolatorschicht kann gegebenenfalls teilweise bis zu der p-leitenden Basiszone des Thyristors bzw. der Hauptzelle reichen. In diesem Fall, wenn die Isolatorschicht die p-leitende Basiszone erreicht, sollte m dieser eine Öffnung vorhanden sein, um die Wirkung des IGBT zu steigern. Ein Vorteil der vorliegenden Erfindung besteht darin, daß ein Gate-gesteuerter Thyristor geschaffen werden kann, dessen FETs praktisch beliebig gestaltet werden können, so daß sie an die verschiedensten Anwendungen anpaßbar sind.Under the first cell and the second cell can ¬ given if an insulator layer are positioned, which provides n-conductive for a better flooding of the particular base region with carriers, thereby switching resistor for an even smaller Em-. This insulator layer can optionally extend as far as the p-type base zone of the thyristor or the main cell. In this case, when the insulator layer reaches the p-type base region, there should be an opening in this to increase the effectiveness of the IGBT. An advantage of the present invention is that a gate controlled thyristor can be created, the FETs of which can be designed practically as desired, so that they can be adapted to a wide variety of applications.

Hierzu wird m den Lateral-FET mindestens ein Graben eingebracht, m welchem eine isolierte Gate-Elektrode vorgesehen ist. Auch m den FET der zweiten Zelle ist vorteilhafterweise mindestens ein Graben mit Gate-Elektrode eingebracht.For this purpose, at least one trench, in which an insulated gate electrode is provided, is introduced into the lateral FET. At least one trench with a gate electrode is advantageously also introduced into the FET of the second cell.

Der erfmdungsgemaße Gate-gesteuerte Thyristor ist mit blichen Verfahrensschritten einfach herstellbar und hinsichtlich seiner Leitfähigkeit sogar dem bestehenden Kaskoden-MOS- Thyristor überlegen, da seine durch die Graben gebildeten Seitenwand-FETs eine große Kanalflache haben.The gate-controlled thyristor according to the invention is simple to produce using customary method steps and is even superior to the existing cascode MOS thyristor in terms of its conductivity, since its side wall FETs formed by the trenches have a large channel area.

Nachfolgend wird die Erfindung anhand der Zeichnungen naher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:

Fig. 1 einen Schnitt durch ein erstes Ausfuhrungsbeispiel des erfmdungsgemaßen Thyristors,1 shows a section through a first exemplary embodiment of the thyristor according to the invention,

Fig. 2 einen Schnitt durch ein zweites Ausfuhrungs- beispiel des erfmdungsgemaßen Thyristors,2 shows a section through a second exemplary embodiment of the thyristor according to the invention,

Fig. 3 ein Ersatzschaltbild zu dem Thyristor,3 shows an equivalent circuit diagram for the thyristor,

Fig. 4 einen Schnitt durch ein drittes Ausfuhrungs- beispiel des erf dungsgemaßen Thyristors,4 shows a section through a third exemplary embodiment of the thyristor according to the invention,

Fig. 5 einen Schnitt durch ein viertes Ausfuhrungs- beispiel des erf dungsgemaßen Thyristors, Fig. 6 eine schematische Draufsicht auf die Grabenstruktur,5 shows a section through a fourth exemplary embodiment of the thyristor according to the invention, 6 shows a schematic top view of the trench structure,

Fig. 7 em vereinfachtes Prmzipschaltbild der bei- den FETs des Thyristors und7 shows a simplified schematic diagram of the two FETs of the thyristor and

Fig. 8 einen Schnitt durch einen herkömmlichen Kaskoden-MOS-Thyristor .8 shows a section through a conventional cascode MOS thyristor.

In den Figuren werden für einander entsprechende Bauteile die gleichen Bezugszeichen verwendet.The same reference numerals are used in the figures for corresponding components.

Die Fig. 8 ist bereits eingangs erläutert worden.8 has already been explained at the beginning.

Fig. 1 zeigt nun em erstes Ausfuhrungsbeispiel der vorliegenden Erfindung mit einem Gate-gesteuerten Thyristor, der einen sehr kleinen Einschaltwiderstand besitzt. Hierzu ist der n-leitenden Emitterzone 9 eine die Ladungsträger- Rekombination erhöhende Schicht 15 aus einem Metall oder Si- lizid, wie beispielsweise Aluminium oder Titansilizid, angeordnet. Gegebenenfalls können hierfür auch andere Silizide oder allgemein Materialien gewählt werden, die die Rekombinationsrate der Ladungsträger erhohen.Fig. 1 shows em first exemplary embodiment of the present invention with a gate-controlled thyristor, which has a very low on resistance. For this purpose, the n-type emitter zone 9 is arranged with a layer 15 made of a metal or silicide, such as aluminum or titanium silicide, which increases the charge carrier recombination. If necessary, other silicides or general materials can be selected for this, which increase the recombination rate of the charge carriers.

Im übrigen ist der Gate-gesteuerte Thyristor m ähnlicher Weise aufgebaut wie der Thyristor von Fig. 8, wobei allerdings der IGBT m der zweiten Zelle C keine n+-dotιerte Zone 14 hat, so daß hier auch die Kante 14' entfallt.Otherwise, the gate-controlled thyristor m is constructed in a similar manner to the thyristor of FIG. 8, although the IGBT m of the second cell C has no n + -doped zone 14, so that the edge 14 'is also omitted here.

Die Zelle B ist also eine normale IGBT-Source-Zelle mit der n -dotierten Zone 11 m der eine Wanne bildenden p-dotierten Zone 6. Die zweite Zelle C weist, wie bereits erläutert, m der p-dotierten Zone 4 keine n*-dotιerte Zone auf. Die erste Zelle B und die Hauptzelle A bilden somit einen n-Kanal-Lateral-FET, wahrend die zweite Zelle C und dieCell B is therefore a normal IGBT source cell with the n -doped zone 11m of the p-doped zone 6 forming a well. As already explained, the second cell C has no n * in the p-doped zone 4. -dotιerte zone. The first cell B and the main cell A thus form an n-channel lateral FET, while the second cell C and

Hauptzelle A einen p-Kanal-FET darstellen.Main cell A represent a p-channel FET.

Die epitaktisch aufgewachsene n-leitende Basiszone 3 und/oder die gesamte Struktur kann ganz oder teilweise mit einem Le¬ bensdauer-Killer, wie Gold, Platin oder durch Bestrahlung er¬ zeugten Kristallfehlern, dotiert sein.The epitaxially grown n-type base region 3 and / or the entire structure may be fully or partially filled with a service life Le ¬ killer, he testified be ¬ crystal defects doped by irradiation such as gold, platinum or the like.

Erfmdungsgemaß sind die Lateral-FETs mit isolierten Gate- Elektroden gefüllte Graben (trench) 20 eingebracht, wie dies aus der Draufsicht von Fig. 6 zu ersehen ist; diese Graben 20, die im Abstand voneinander senkrecht zur Zeichenebene von Fig. 1 angeordnet sind, lassen eine praktisch beliebige Ge- staltung der beiden FETs (vgl. Fig. 7) zu und sorgen für eine große Kanalflache. Es sei angemerkt, daß die Kante 14' (in Fig. 6 strichliert gezeigt) nur dann vorhanden ist, wenn m der Schicht 4 noch wie m Fig. 8 zusatzlich die Schicht 14 eingebracht ist.According to the invention, the lateral FETs with trenches 20 filled with insulated gate electrodes are introduced, as can be seen from the top view of FIG. 6; these trenches 20, which are arranged at a distance from one another perpendicular to the plane of the drawing in FIG. 1, permit virtually any configuration of the two FETs (cf. FIG. 7) and ensure a large channel area. It should be noted that the edge 14 '(shown in broken lines in FIG. 6) is only present if the layer 14 is additionally introduced in the layer 4, as in FIG. 8.

In einem anderen Ausfuhrungsbeispiel der Erfindung kann unterhalb der beiden Zellen B und C, also unterhalb der p- leitenden Zonen 6 bzw. 4 noch eine Isolatorschicht 16 vorgesehen sein, die aber nicht bis zu der p-leitenden Basiszone 5 reicht, wie dies m Fig. 2 dargestellt ist. Diese Isolatorschicht 16 sorgt für eine noch bessere "Überflutung" der n-leitenden Zone 3 mit Ladungsträgern, was den Einschaltwi¬ derstand weiter erniedrigt. Die "gestrichenen" Bezugszeichen für die jeweiligen Kanten sind m den Fig. 4 und 5 der besse- ren Übersichtlichkeit wegen teilweise weggelassen.In another exemplary embodiment of the invention, an insulator layer 16 can be provided below the two cells B and C, that is to say below the p-type zones 6 and 4, but does not extend as far as the p-type base zone 5, as shown in FIG 2 is shown. This insulator layer 16 ensures an even better “flooding” of the n-conducting zone 3 with charge carriers, which further lowers the switch-on resistance . The "deleted" reference numerals for the respective edges are partially omitted in FIGS. 4 and 5 for the sake of clarity.

In einem weiteren Ausfuhrungsbeispiel der Erfindung, das m Fig. 4 gezeigt ist, können die Isolatorschichten 16 bis zu der p-leitenden Basiszone 5 reichen und diese teilweise sogar überdecken. In diesem Fall sollte aber m der p-Basiszone 5 eine Öffnung 17 vorhanden- sein, um die IGBT-Wirkung derIn a further exemplary embodiment of the invention, which is shown in FIG. 4, the insulator layers 16 can extend as far as the p-conducting base zone 5 and in some cases even cover it. In this case, however, m of the p-base zone 5 an opening 17 to be present to the IGBT effect of

Hauptzelle A zu erreichen. Sogenannte Zwischenzonen 19 sind relativ schwach dotiert und entweder n- oder p-leitend.To reach main cell A. So-called intermediate zones 19 are relatively weakly doped and either n- or p-conductive.

Fig. 5 zeigt ein weiteres Ausführungsbeispiel des erfindungs¬ gemäßen Gate-gesteuerten Thyristors, bei dem eine Metallschicht 18 oberhalb der nτ-leitenden Emitterzone 9 auf der Schicht 15 vorgesehen ist.Fig. 5 shows another embodiment of the Invention ¬ proper gate controlled thyristor, is provided in which a metal layer 18 above the n τ -type emitter zone 9 on the layer 15.

Ein Ersatzschaltbild für den Gate-gesteuerten Thyristor der obigen Ausführungsbeispiele ist in Fig. 3 dargestellt. Bei positiver Gatespannung an Gate G ist die Thyristorkathode geerdet, so daß der Durchlaßwiderstand niedrig ist. Liegen aber 0 V oder eine negative Spannung an Gate G so ist die erste Zelle B als Lateral- und Vertikal-FET abgeschaltet, während die zweite Zelle C als p-Kanal-FET leitet und kein Strom fließt.An equivalent circuit diagram for the gate-controlled thyristor of the above exemplary embodiments is shown in FIG. 3. If the gate voltage at gate G is positive, the thyristor cathode is grounded so that the on-resistance is low. However, if there is 0 V or a negative voltage at gate G, the first cell B is switched off as a lateral and vertical FET, while the second cell C is conducting as a p-channel FET and no current flows.

Der Graben 20 ist in üblicher Weise mit einer isolierten Ga- te-Elektrode "gefüllt" wozu geeignete Materialien (z.B. PolySilizium als Gateelektrode, Si02 als Gateisolator usw.) herangezogen werden können. Dadurch wirkt die Seitenwand des Grabens 20 als Kanalgebiet eines MOSFETs.The trench 20 is “filled” in the usual way with an insulated gate electrode, for which purpose suitable materials (for example polysilicon as gate electrode, SiO 2 as gate insulator, etc.) can be used. As a result, the side wall of the trench 20 acts as a channel region of a MOSFET.

Die Erfindung ermöglicht also einen Gate-gesteuerten Thyristor, der einen extrem niedrigen Einschaltwiderstand besitzt und dennoch hohe Spannungen zu sperren vermag. The invention thus enables a gate-controlled thyristor which has an extremely low on-resistance and is nevertheless able to block high voltages.

BezugszeichenlisteReference list

1 Anodenelektrode1 anode electrode

2 p-Zone2 p zone

3 n-Zone3 n zone

4 p-Zone4 p zone

4' Kante der Zone 44 'edge of zone 4

5 p-Basiszone5 p base zone

5' Kante der Basiszone 55 'edge of base zone 5

6 p-Zone6 p zone

6' Kante der Zone 66 'edge of zone 6

7 Kontakt7 contact

8 Isolierschicht8 insulating layer

9 Emitterzone9 emitter zone

9' Kante der Emitterzone 99 'edge of emitter zone 9

10 Gatekontakt10 gate contact

10' Kante des Gatekontakts 1010 'edge of the gate contact 10

11 n+-Zone11 n + zone

11' Kante der Zone 1111 'edge of zone 11

12 Kontakt12 contact

13 Kontakt13 contact

13' Kante des Kontakts 1313 'edge of contact 13

14 n+-Zone14 n + zone

14' Kante der Zone 1414 'edge of zone 14

15 Schicht15 layer

16 Isolierschicht16 insulating layer

17 Öffnung17 opening

18 Metallsch.icht18 metal layer

19 Zwischenzone19 intermediate zone

20 Graben A Hauptzelle20 trenches A main cell

B Erste ZelleB First cell

C Zweite ZelleC Second cell

G Gate-ElektrodeG gate electrode

D Drain-ElektrodeD drain electrode

V-FET Vertikal-FET V-FET vertical FET

Claims

Patentansprüche ^ Claims ^ 1. Gate-gesteuerter Thyristor, bei dem em IGBT m einer er- sten Zelle (B) und em Thyristor m einer Hauptzelle (A) so zusammengeschaltet sind, daß die erste Zelle (B) und die Hauptzelle (A) einen Lateral-FET mit einem Kanal eines ersten Leitungstyps bilden, d a d u r c h g e k e n n z e i c h n e t , daß m die Emitterzone (9) des Thyristors eine die Ladungsträger-Rekombination erhöhende Schicht (15) eingebettet ist.1. Gate-controlled thyristor in which an IGBT m of a first cell (B) and an thyristor m of a main cell (A) are connected together in such a way that the first cell (B) and the main cell (A) form a lateral FET form with a channel of a first conductivity type, characterized in that m the emitter zone (9) of the thyristor is embedded in a layer (15) which increases the charge carrier recombination. 2. Thyristor nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß m den Lateral-FET mindestens em Graben (20) eingebracht ist, m welchem eine isolierte Gate-Elektrode vorgesehen ist.2. Thyristor according to claim 1, d a d u r c h g e k e n n z e i c h n e t that m the lateral FET at least one trench (20) is introduced, with which an insulated gate electrode is provided. 3. Thyristor nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die die Ladungsträger-Rekombination erhöhende Schicht (15) aus einem Metall oder Silizid, insbesondere Aluminium und/oder Titansilizid, gebildet ist.3. Thyristor according to Claim 1 or 2, that the charge carrier recombination-increasing layer (15) is formed from a metal or silicide, in particular aluminum and / or titanium silicide. 4. Thyristor nach Anspruch 1, 2 oder 3, d a d u r c h g e k e n n z e i c h n e t , daß mit der Hauptzelle (A) noch eine zweite Zelle (C) mit einem MOS-Schalter verbunden ist, die mit der Hauptzelle (A) einen FET mit einem Kanal eines zweiten Leitungstyps bildet.4. Thyristor according to claim 1, 2 or 3, characterized in that with the main cell (A) a second cell (C) is connected to a MOS switch, which with the main cell (A) is an FET with a channel of a second conduction type forms. 5. Thyristor nach Anspruch 4, d a d u r c h g e k e n n z e i c h n e t , daß auch m den FET der zweiten Zelle mindestens em Graben mit Gate-Elektrode eingebracht ist. 5. Thyristor according to claim 4, characterized in that m the FET of the second cell at least em trench with gate electrode is introduced. 6. Thyristor nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß unter wenigstens einer Zelle aus der ersten und der zwei¬ ten Zelle (B, C) eine Isolatorschicht (16) angeordnet ist.6. Thyristor according to one of claims 1 to 5, characterized in that an insulator layer (16) is arranged under at least one cell from the first and the two ¬ th cell (B, C). 7. Thyristor nach Anspruch 6, d a d u r c h g e k e n n z e i c h n e t , daß die Isolatorschicht (16) bis unter die Hauptzelle (A) reicht .7. Thyristor according to claim 6, d a d u r c h g e k e n n z e i c h n e t that the insulator layer (16) extends below the main cell (A). 8. Thyristor nach Anspruch 7, d a d u r c h g e k e n n z e i c h n e t , daß die p-Basisschicht (5) des Thyristors mit einer Öffnung (17) versehen ist.8. Thyristor according to claim 7, d a d u r c h g e k e n n z e i c h n e t that the p-base layer (5) of the thyristor is provided with an opening (17). 9. Thyristor nach einem der Ansprüche 1 bis 8, d a d u r c h g e k e n n z e i c h n e t , daß die n-leitende Basiszone (3) epitaktisch aufgewachsen und mit Rekombinationszentren versehen ist.9. Thyristor according to one of claims 1 to 8, d a d u r c h g e k e n n z e i c h n e t that the n-conducting base zone (3) has grown epitaxially and is provided with recombination centers. 10. Thyristor nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t , daß ein Teil der n-leitenden Basiszone (3) mit den Rekombinationszentren, insbesondere Gold, Platin oder durch mit Be- Strahlung erzeugten Kristallfehlern, versehen ist.10. Thyristor according to claim 9, d a d u r c h g e k e n n z e i c h n t that part of the n-type base zone (3) with the recombination centers, in particular gold, platinum or by crystal defects generated with radiation, is provided. 11. Thyristor nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t , daß der gesamte Halbleiterkörper des Thyristors ganz oder teilweise mit den Rekombinationszentren, insbesondere Gold, Platin oder durch mit Bestrahlung erzeugten Kristallfehlern, versehen ist. 11. Thyristor according to claim 9, d a d u r c h g e k e n n z e i c h n e t that the entire semiconductor body of the thyristor is provided in whole or in part with the recombination centers, in particular gold, platinum or by crystal defects generated with radiation.
EP98945056A 1997-07-30 1998-07-29 Gate-controlled thyristor Withdrawn EP0931352A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19732912A DE19732912C2 (en) 1997-07-30 1997-07-30 Cascode MOS thyristor
DE19732912 1997-07-30
DE19739498A DE19739498C1 (en) 1997-09-09 1997-09-09 Cascade MOS thyristor
DE19739498 1997-09-09
PCT/DE1998/002154 WO1999007020A1 (en) 1997-07-30 1998-07-29 Gate-controlled thyristor

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JP3571353B2 (en) * 1998-09-10 2004-09-29 三菱電機株式会社 Semiconductor device
WO2007135694A1 (en) * 2006-05-18 2007-11-29 Stmicroelectronics S.R.L. Three- terminal power device with high switching speed and manufacturing process

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DE3024015A1 (en) * 1980-06-26 1982-01-07 Siemens AG, 1000 Berlin und 8000 München CONTROLLABLE SEMICONDUCTOR SWITCH
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