EP0892990A1 - Semiconductor component with a split floating gate - Google Patents

Abstract

In a semiconductor component, in particular an EEPROM, an avalanche breakdown from the buried channel (14) to the substrate (10) is avoided by a local thickening of the gate dielectric (insulating structure 22) at the transition to the tunnel dielectric (18). As a potential barrier is thus created, the gate and tunnel dielectrics may have the same thickness. The space required by such a cell is reduced.

Description

description

Semiconductor device with a split floating gate

The invention relates to a semiconductor component with a first and a second doped region of a first line type, which are arranged in a semiconductor substrate of a second line type, and with a channel region in the semiconductor substrate between the two doped regions, in particular it relates to EEPROM memory cells.

EEPROM cells (electrically erasable and programmable read only memories) play an increasingly important role among memory types. For example, memory blocks of the FLOTOX cell type (floating gate tunnel oxide) are used for chip card applications and are integrated in a microcontroller environment (embedded memories). There is a need for ever smaller cells. A limiting factor is the shrinkability of the tunnel window with the associated electrical connection area (buried channel). This limit is primarily determined by the properties of the device, as described below and in the application “Semiconductor component with adjustable current gain based on a tunnel current-controlled avalanche breakdown” by the same applicant and filing date.

In Fig. 1, an EEPROM cell of the FLOTOX type is shown schematically. In a p-doped semiconductor substrate 1 there are two n-doped regions 2, 3 as source and drain. A floating gate 6 is arranged on the intermediate substrate surface and is separated from the substrate by a gate dielectric 7 or a tunnel dielectric 8. The floating gate is “connected” to the drain via the tunnel dielectric (so-called tunnel window) and via an n-doped region 4 referred to as buried channel. The region below the gate oxide of the memory transistor, the so-called channel region 5, is weakly p-doped. The gate dielectric 7 not only covers the channel region 5, but also an edge region 4 'of the

Buried Channel 4. A control gate 9 with a connection 10 is arranged above the floating gate 6. The following voltages are set for programming:

Ucontrolgate = ov

U _Dr ain = + 15V

Usable floating electrons can get from the floating gate through the potential barrier in the oxide into the conduction band of the oxide and then into the substrate, this is shown as a band diagram in FIG. They absorb enough energy to generate electron-hole pairs in the substrate. (Holes tend to run along the upper edge of the valence band to a higher potential - i.e. upwards in the drawing, since this corresponds to a lower potential for holes.)

FIG. 3 shows the potential curve along the interface perpendicular to the drawing plane of FIG. 2 (that is, along the axis III-III 'in FIG. 1) with a large lateral extent of the edge region 4' for different values of U _bU riβd Channel. The pn junction between buried channel 4 (n-doped) and substrate (p-doped) is polarized in the reverse direction at the voltages mentioned. This leads to a large potential gradient. At the tunnel-to-gate dielectric transition, a small potential barrier Pb is formed in both the conduction and valence bands, since the potential at the interface depends on the thickness of the dielectric above: the hole potential in the tunnel oxide region is higher than in the gate oxide region. The hole potential drop Pa to the p-area only sets with the drop in concentration. Endowment. If the height of this potential barrier is always (for holes) above the buried channel potential, holes cannot escape from the buried channel region 4. 4: If the lateral extent of the edge region 4 'under the gate dielectric 7 is not sufficient, the hole potential drop Pa starts earlier. The barrier Pb lies in the falling branch and falls below the buried channel level. Therefore, the holes generated by the tunnel electrons can escape from the area under the tunnel dielectric 8 and pass through the hole potential gradient to the channel area 5. Holes are no longer kept in the buried channel area. Additional electron-hole pairs are generated by impact ionization. Charge multiplication occurs so that the current from buried channel 4 to channel region 5, ie into substrate 1, is many orders of magnitude (10 ⁴ to 10 ⁶ ) above the tunnel current. The charge pump for generating the programming voltage cannot supply this current. The cells cannot be programmed by a few milliseconds in the required time. The parasitic current generated by the charge multiplication also loads the tunnel oxide and thus reduces the cyclical strength.

The height of the potential barrier is of crucial importance for the programming process and the electrical reliability of the component. It can be set: by the lateral extension of the edge region 4 '- by the thickness ratio of tunnel dielectric to gate dielectric by the lateral doping profile around the gate oxide tunnel oxide edge.

In order to obtain a sufficient expansion of the edge area 4 'under the gate dielectric 7, a high lateral out-diffusion of the n-doping element (mostly phosphorus) is necessary. This can be achieved by a high implantation dose. The distance between the gate oxide and tunnel oxide edge to the source region must be large enough so that the channel length of the storage chertransistor is not too short due to the lateral diffusion. A high buried channel concentration also has an unfavorable effect on the quality of the tunnel oxide. Furthermore, the sufficient extent of the edge region 4 'is usually ensured by using two different masks to define the buried channel 4 and the tunnel window, that is to say the implantation mask for the buried channel has a larger opening than the etching mask for the tunnel window.

Another way to avoid avalanche breakdown is a large thickness ratio of gate to tunnel dielectric (> 4). If this ratio is to be reduced, the lateral shrink boundaries of the component are encountered.

The object of the invention is therefore to create an EPROM with a small footprint and high electrical reliability. This object is achieved by a semiconductor component with the features of patent claim 1. Further training is the subject of subclaims.

In the case of the invention, the potential barrier Pb which prevents avalanche breakdown can be set by locally increasing the layer thickness of the gate dielectric at the transition from tunnel dielectric to gate dielectric. The tunnel electrode and channel gate electrode are therefore separated at least on their surface facing the tunnel dielectric or the gate dielectric by an insulation structure which is arranged on the gate dielectric. The dimensions and the position of this insulation structure determine the potential barrier. The insulation structure can be arranged above an edge region of the buried channel, preferably covering it completely and reaching the pn junction, it can also extend over a part of the channel region, that is to say covering the pn junction. The tunnel electrode and the channel gate electrode can be connected to one another outside the insulation web, for example on their surface facing away from the tunnel dielectric or the gate dielectric. This connection can have the same layer thickness as the electrodes. The insulation web can, however, also completely separate the two electrodes from one another, an external connection of the two gates is then preferably provided.

Since the isolation barrier achieves the potential barrier, the layer thicknesses of the gate dielectric and tunnel dielectric can be chosen freely and are not critical with regard to avoiding an avalanche breakdown. Both dielectrics can also have the same layer thickness, which simplifies the manufacturing process.

The tunnel gate electrode and the channel gate electrode can be produced from the same conductive layer, the insulation structure preferably being generated beforehand. Alternatively, they can be produced from layers applied one after the other, the insulation web can then be formed by a spacer.

The invention is explained in more detail below on the basis of exemplary embodiments which are illustrated in the drawings. Show it

1 shows a cross section through a semiconductor substrate with a known EEPROM memory cell,

2 - 4: the potential profile in the semiconductor substrate along predetermined axes, FIG. 5: a cross section through a semiconductor substrate with a memory cell according to the invention, FIG. 6: a further embodiment of the invention, 7 shows a cross section through a semiconductor substrate, on which a manufacturing method is illustrated.

5: A p-doped silicon semiconductor substrate 11 contains a first n-doped region 14, which is usually referred to as a buried channel, and a second n-doped region 12. The substrate region between these doped regions referred to as channel area 15. A gate oxide 17 covers the surface of the channel region 15, a tunnel oxide 18 partially covers the surface of the buried channel 14; A gate electrode is arranged as a floating gate above these dielectrics. In this respect, the memory cell corresponds to that in FIG. 1.

According to the invention, an insulation structure 22 is provided at the transition from the tunnel to the gate dielectric, which is arranged above the edge region 14 'of the buried channel and represents a local thickening of the gate dielectric, so that the necessary potential barrier is achieved. It separates the gate electrode into a tunnel gate electrode 19 above the tunnel oxide 18 and into a channel gate electrode 20 above the gate oxide. In this example, the tunnel and gate electrodes are not completely separated, but are connected to one another above the insulation web. The layer thicknesses of tunnel and gate oxide are the same and are around 8 mm.

The rest of the structure corresponds to that of a known EEPROM

Cell: Above the floating gate 19, 20, a control gate (24) with a connection 25 is arranged in isolation, the gates are covered on all sides with an insulating layer 23. The buried channel region 14 can be connected directly or via an n-doped region (drain) 13. This arrangement could, for example, be used with FLOTOX and flash type EEPROMs. When a flash cell is deleted ⁽ < ^u _S ource ^{= + 8v and U} _CG ⁼ ~ ^8V) , electrons tunnel from the floating gate into the source area. Without the insulation structure, there would be no potential barrier (or, with different thicknesses of tunnel oxide and gate oxide, the risk of an insufficient). With each extinguishing process, a charge multiplication is started and hot charge carriers are generated. This stresses the thin tunel oxide (or gate oxide) and considerably reduces the number of write-erase cycles.

With FLOTOX cells, insulation can be used instead of the transition from the tunnel dielectric to the gate dielectric with short-circuited electrodes. As explained at the beginning, the outdiffusion of the first doped region (buried channel) can thereby be greatly reduced, as a result of which smaller cells can be realized.

6 shows, as a further embodiment, a memory cell in which the insulation structure 22 completely divides the floating gate into tunnel gate 19 and channel gate 20. The two gates can be connected to one another in an externally conductive manner by further interconnects. The tunnel oxide 18 is, for example, approximately half as thick as the gate oxide 17. The reference numbers are chosen as in FIG. 5.

FIG. 7 explains a simple method for producing the floating gate of a flash or a FLO-TOX cell shown in FIG. 6.

The gate oxide 17 is produced on the silicon substrate 11 using known methods, on which a first conductive layer 30, for example a polysilicon layer, is applied. The polysilicon layer becomes corresponding to the channel gate electrode 20 structured, and using conventional methods, an isolating spacer is produced which represents the isolating web 22. Now the Buried Channel 14 is implanted using a photo mask. Possibly. If the gate oxide is removed - the same photomask as used for the buried channel implantation can be used - and a tunnel oxide 18 is applied, then a second conductive layer 31 (preferably polysilicon) is deposited. This is structured in accordance with the floating gate 19, 20. The further process steps (implantations, gate insulation, etc.) can be carried out in a known manner.

The floating gate produced in this way consists of a tunnel gate electrode 19, which consists of the second conductive layer 31, and a channel gate electrode 20, which is composed of both conductive layers 30, 31. Both electrodes are connected to one another via the second conductive layer 31.

Analogously, such a method can be used to produce an arrangement in which the channel gate electrode 20 consists of the second conductive layer 31 and the tunnel electrode 19 is composed of two conductive layers 30, 31.

Claims

claims 1. Semiconductor component with - a first (14, buried channel) and a second doped region (12) of a first conductivity type, which are arranged in a semiconductor substrate (11) of a second conductivity type, - a channel region (15) in the semiconductor substrate between the two doped regions (12, 14), a tunnel dielectric (18) which partially covers a surface of the first doped region (14), a gate dielectric (17) which covers a surface of the channel region (15) and an edge region (14 ') of the first doped region (14), - a tunnel gate electrode (19) on the tunnel dielectric, - A channel gate electrode (20) on the gate dielectric, in which the tunnel gate electrode (19) and the channel gate electrode (20) are separated by an insulation structure (22) at least on their surface facing the tunnel dielectric or the gate dielectric. 2. The semiconductor component according to claim 1, wherein the insulation structure (22) completely separates the tunnel gate electrode (19) and the channel gate electrode (20) from one another. 3. The semiconductor component as claimed in claim 1, in which the tunnel gate electrode (19) and the channel gate electrode (20) are conductively connected to one another on their surface facing away from the tunnel dielectric or the gate dielectric. 4. Semiconductor component according to one of claims 1-3, wherein the tunnel dielectric (18) and the gate dielectric (17) have the same layer thickness. 5. Semiconductor component according to one of claims 1-4, wherein the channel gate electrode (20) from a first (30) and a second conductive layer (31), the tunnel gate electrode (19) from the second conductive layer (31) and the Isolati¬ on structure (22) consist of a spacer. 6. Semiconductor component according to one of claims 1-4, wherein the tunnel gate electrode (19) from a first (30) and a second conductive layer (31), the channel gate electrode (20) from the second conductive layer (31) and the Isolation structure (22) consist of a spacer. 7. Semiconductor component according to one of claims 1-6, wherein the insulation structure covers the edge region (14 ') of the first doped region.