EP0890266A1

EP0890266A1 - Real-time high resolution video capture system

Info

Publication number: EP0890266A1
Application number: EP97917079A
Authority: EP
Inventors: Jeffery D. Belote; Jeff S. Ford
Original assignee: Intergraph Corp
Current assignee: Intergraph Corp
Priority date: 1996-03-27
Filing date: 1997-03-27
Publication date: 1999-01-13
Also published as: WO1997036428A1

Abstract

A system for real-time capture and playback of high resolution compressed and uncompressed digital video data received upon a JPEG video board (10) over an input line (D1). This input is converted into YUV, and may be scaled and adjusted for color, contrast, hue and saturation. A bus interface (16) is in communication with the video input to provide a high resolution digital video data stream. A transient memory (20) communicates with the interface (16) over a first data path (11), and a digital storage medium (31, 35, 36, 40) communicates with the transient memory over a second data path (12), where the first and second data paths are configured to permit real-time storage of the data stream under microprocessor control.

Description

Rβal-Time High Resolution Video Capture System

DESCRIPTION

This application claims priority from provisional application serial number 60/014, 226 filed March 27, 1996, entitled "Video Capture and Playback Board for Use in a Computer Graphics System, which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention generally relates to the processing of video data, and more particularly to a system and apparatus that supports real-time capture and playback of high resolution compressed and uncompressed digital video data.

BACKGROUND ART

In the field of video processing, a user usually wants a computer graphics system that captures and plays back both compressed and uncompressed video data.

A Digital Disk Recorder (DDR) may process either compressed or uncompressed data, but not both. The capturing of uncompressed video data also is problematic because of bus bandwidth limitations when using single bus designs. And the systems that will process uncompressed data may not be compatible with some file systems. Furthermore, the use of proprietary file formats and the cost of such systems, make them of limited use in the industry.

It also is desirable that the capture and playback functions, as well as editing, be performed on a single board within the system. There are some systems that do a portion of what is required but not everything on one Peripheral Component Interconnect (PCI) board. For example, in many systems, the capture function will be performed on one board and the playback function on another board. Moreover, in current systems where there is a single board, there is often no scaling feature or means to do other video editing, e.g., color correction, and adjusting of brightness, hue, and saturation. Although there are some products that will scale video, currently none do so in real-time for uncompressed video data.

Therefore, what is needed is a system that will perform real-time processing of digital video data using a single board that performs both capture and playback of compressed and uncompressed digital video data, memory to memory compression and decompression which is required for editing, as well as other features that will be explained in the detail in the remainder of this specification.

SUMMARY OF THE INVENTION

The present invention, in a preferred embodiment, is a real-time high resolution video capture and playback system which comprises a digital video input; a bus interface in communication with the video input providing a high resolution digital video data stream; a transient memory in communication with the interface over a first data path; and a digital storage medium in communication with the transient memory over a second data path, wherein the first and second data paths are configured to permit real-time storage of the data stream under microprocessor control.

The first data path may comprise a first data bus and the second data path may comprise a second data bus . The bus interface is preferably DMA. The digital storage medium may be a plurality of disk drives, for example, a redundant array of inexpensive disks.

In a preferred embodiment, the digital video signal is processed by a Joint Photographic Experts Group (JPEG) digital video board which is a single PCI board that supports real-time video capture and playback, and video editing of a digital video data stream on a computer graphics workstation. The video data stream may either be compressed or uncompressed.

In a preferred embodiment, the board comprises: a digital video input for receiving a video data stream; a YUV coding device in communication with the video input for processing the video data stream into a YUV data stream; a formatter in communication with the YUV coding device for processing the YUV data stream; a plurality of lookup tables in communication with the YUV coding device for adjusting contrast and brightness of the YUV data stream; a sealer in communication with the YUV coding device for scaling the YUV data stream; a bus interface in communication with the lookup tables for communicating the YUV data stream across the first data bus to system memory; a JPEG device in communication with the YUV decoding device for compressing an uncompressed video stream; and a composite video encoder in communication with the YUV coding device for encoding the video data stream into an analog format.

The board allows full 60 fields capture and playback of CCIR-601 sampled video using the Dl transmission standard. This provides the highest possible video quality into and out of the workstation. The resultant video quality is limited only by the available disk bandwidth. Captured video may be optionally scaled down from full size to reduce the data volume or processing time during editing sessions. The finished video may be scaled up on playback, if necessary, to full frame size. The board supports memory-to-memory compression and decompression services required during video editing, as well as unsealed and uncompressed video capture and playback. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a preferred embodiment of a real-time high resolution video capture and playback system of the present invention.

FIG. 2 is a functional block diagram of the flow of video data in a preferred embodiment of a video board of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to FIG. 1 which shows a block diagram of a preferred embodiment of a real-time high resolution video capture and playback system of the present invention. High resolution means at least 720 x 486 for National Television System Committee (NTSC) or 720 x 576 for Phase-Alternation Line (PAL) . Video Board 10, preferably a JPEG board, receives or captures a digital video data stream on video input line Dl. The video data stream is processed in accordance with the path of FIG. 2 (explained in detail below) .

Thereafter the video data stream is communicated across a first data path using a bus interface. In a preferred embodiment, the first data path is PCI bus 11 and the bus interface is a PCIDMA chip 16. PCIDMA Chip 16 allows the board 10 to transfer data directly to and from the system memory using the PCI bus 11. Next, the video stream is stored in a transient memory that communicates with PCIDMA chip 16. The transient memory is found on a microprocessor chip 20, preferably of the Intel Chipset type. The video data stream is then communicated across a second data path to digital storage mediums such as Redundant Array of Inexpensive Disks (RAID) 31, 35, 36 and 40. FIG. 1 only shows 2 RAIDS per RAID controllers 30 and 41 for illustration purposes only. It should be understood by those of ordinary skill in the art, that there may be a plurality of RAIDS per RAID controller. In a preferred embodiment, the second data path is PCI bus 12.

Using two PCI buses 11 and 12 to communicate the captured video data from video input Dl throughout the system provides the additional bus bandwidth needed to process high resolution uncompressed video data. When processing compressed video data, the JPEG Codec or JPEG device 15 of board 10 processes the data before it is transferred to transient memory using PCI bus 11. Finally a bridge chip 50, preferably a DEC bridge chip, is used to provide communication to other peripheral devices (not shown) within the system.

Referring now to FIG. 2, the capturing of compressed video data will be discussed first, then uncompressed video data. During the capturing of compressed video data on board 10, in a preferred embodiment, video data is received on the Dl input line and is decoded and formatted into a YUV data stream using a YUV decoding device 1 and a formatter 2, respectively. In a preferred embodiment, the data stream is formatted into a 10-bit, 27 MHZ YUV 4:2:2 data stream according to Society Of Motion Picture And Television Engineers (SMPTE) 125M and Consultative Committee of International Radio (CCIR) 656 specifications for 10-bit parallel video transmission. The YUV data stream is then processed by a plurality of lookup tables (LUT) 3.

In a preferred embodiment, the 10-bit luma (Y) data is adjusted for contrast and brightness in a plurality of Look-Up Tables (LUT) . The 9-bit output of the luma LUT is then truncated to 8 bits and sent to a sealer 4 input first-in, first-out (FIFO) . The 10-bit chroma (Cb and Cr) data is rounded to 9 bits and adjusted for hue and saturation in a different LUT. The 18-bit output of the chroma LUT is then multiplexed and truncated to 8 bits before it is sent to the sealer 4 input FIFO. The 9-bit per component data out of the luma and chroma LUTs 3 are simultaneously re-encoded into a SMPTE 125M video stream using formatter 2 and transmitted on the Dl output line. The LUT modified 10-bit SMPTE125M stream is also sent to a composite video encoder 6 which encodes the stream into a composite or S-Video analog format. In a preferred embodiment , the composite video encoder 6 is an NTSC/PAL video encoder.

The 16-bit luminance/chrominance (YUV) 4:2:2 video data may be scaled down in both the horizontal and vertical dimensions using the sealer 4. The resultant scaled video must have horizontal and vertical dimensions which are an integer multiple of 8 in order for the JPEG compression algorithm to be applied by the JPEG device 15.

In a preferred embodiment, each field of the scaled video is then placed into one of two field buffers. The double-buffered field Random Access Memories (RAMs) decouple the sporadic JPEG compressor of JPEG device 15 accesses from the constant rate video stream. The JPEG compressor pulls data out of the frame buffer, through the data router 5, and puts it into the line buffer RAM which acts as a local data buffer for the compressor. After compression, the data is sent to the host memory via a Direct Memory Access (DMA) transfer controlled by the PCIDMA chip 16. The board 10 compresses each field of video as a separate entity. Even if the video fields are not scaled down, they still pass through the sealer, and for NTSC, the bottom of each field is padded with 5 replicated lines to fill out the field to an integer multiple of 8 lines. If the compressor cannot keep up with the scaled video data, scaled fields are dropped by writing over the last received field until the compressor is finished with the field it is processing.

When uncompressed video capture is selected, the board 10 works in the same manner aε described in the paragraph above, except that the data router 5 is configured to send the scaled (or unsealed) video data from the field store to the uncompressed FIFO to be DMA'd into system memory. JPEG device 15 is not involved in this process. The sealer 4 may be configured to produce either YUV 4:2:2 data or Red, Green, Blue (RGB) 4:4:4 data, but if RGB data is selected, it cannot be played back to the Dl outputs without color-space conversion to YUV by the Central Processing Unit (CPU) 21. The luma and chroma Lookup Tables (LUTs) 3 are double buffered to allow the user to modify the brightness, contrast, hue, and saturation in real time, either before or during a capture operation. The user may view the results of an adjustment as it is being made on the Dl, composite, or S-Video outputs.

Now, turning to compressed video playback. During compressed video playback, compressed data is DMA'd from system memory into the JPEG device 15 for decompression. In a preferred embodiment, the decompressed data is sent through the data router 5 and FIFO to the sealer 4, where it is scaled to full size (720 x 486 for NTSC or 720 x 576 for PAL) and put into the field buffer. The double- buffered field buffer decouples the sporadic JPEG decompression stream from the constant rate video stream. The video is taken out of the field buffers through the data router 5 to the LUT. The 8-bit luma (Y) data is adjusted for contrast and brightness in a Look-Up Table (LUT) . The 8-bit chroma (Cb and Cr) data is adjusted for hue and saturation in a different LUT. The 18-bit output of the chroma LUT is then multiplexed together with the 9-bit luma LUT output, formatted according to SMPTE125M and CCIR 656 10-bit parallel video standards, then encoded into a Dl video stream which is transmitted on the Dl output. The LUT modified 10-bit SMPTE125M stream is also sent to the NTSC/PAL video encoder which encodes the stream into a composite or S-Video analog format. If the decompressor cannot keep up with full rate video playback, the last full field received is retransmitted (replicated) until the decompressor finishes the current field.

When uncompressed video playback is selected, the board 10 works in the same manner as described in the paragraph above, except that the data router 5 is configured to send the scaled (or unsealed) video data from the uncompressed FIFO to the sealer 4 input FIFO. The JPEG device 15 is not involved in this process . The video data format is preferably YUV 4:2:2 for uncompressed video playback.

The luma and chroma LUTs 3 are double buffered to allow the user to modify the brightness, contrast, hue, and saturation in real-time, either before or during a playback operation. The user may view the results of an adjustment as it is being made on the Dl, composite, or S-Video outputs.

The reference input allows the outgoing video to be field-locked to a black burst or other stable composite reference input. In one embodiment, the reference input preferably has no more than 63.5 μs of jitter between vertical syncs to obtain a stable video output.

In addition, the board 10 may be configured to do memory to memory compression of either scaled or unsealed fields. Scaled fields must be in YUV 4:2:2 format, and the compressed field size must be an integer multiple of 8 in both x and y. The following formats are available for unsealed compression: • RGB (packed, unpacked)

CMYK

• grayscale

• YUV 4:2:2

All data will be compressed with no loss or insertion of fields in memory to memory compression mode, since the data is not required to be processed at a fixed rate as in video capture.

Furthermore, the board 10 may be configured to do memory to memory scaled or unsealed decompression. Decompressed, scaled fields may be in either the YUV

4:2:2 or RGB 4:4:4 (packed or unpacked) formats. The following formats are available for unsealed compression:

• RGB (packed, unpacked) CMYK • grayscale

YUV 4:2:2 All data will be decompressed with no loss or insertion of fields in memory to memory decompression mode, since the data is not required to be processed at a fixed rate as in video playback.

Of course, it should be understood that various changes and modifications to the preferred embodiment described above will be apparent to those skilled in the art. Therefore, such changes may be made without departing from the spirit and the scope of the invention and without diminishing its attendant advantages. It is therefore intended that such changes and modifications be covered by the following claims.

Claims

What is claimed is:

1. A real-time high resolution video capture system comprising: a digital video input; a bus interface in communication with the video input providing a high resolution digital video data stream; a transient memory in communication with the interface over a first data path; and a digital storage medium in communication with the transient memory over a second data path, wherein the first and second data paths are configured to permit real-time storage of the data stream under microprocessor control .

2. The video capture system of claim 1 wherein the first data path comprises a first data bus and the second data path comprises a second data bus .

3. The video capture system of claim 1 wherein the bus interface is direct memory access.

4. The video capture system of claim 1 wherein the storage medium is a plurality of disk drives.

5. The video capture system of claim 4 wherein the plurality of disk drives is a redundant array of inexpensive disks.

6. The video capture system of claim 1 wherein disposed between the video input and the first data path is a YUV coding device in communication with the video input for processing the video data stream into a YUV data stream; a formatter in communication with the YUV coding device for processing the YUV data stream; a plurality of lookup tables in communication with the YUV coding device for adjusting contrast and brightness of the YUV data stream; and a sealer in communication with the YUV coding device for scaling the YUV video data stream.

7. The video capture system of claim 6 wherein the data stream is an uncompressed video data stream.

8. The video capture system of claim 7 further comprising a JPEG device in communicating with the YUV decoding device for compressing an uncompressed video stream.

9. The video capture system of claim 8 wherein the bus interface is also in communication with the JPEG device for communicating the uncompressed video data stream across the first data bus to system memory.

10. The video capture system of claim 9 further comprising a further comprising a composite video encoder in communication with the YUV coding device for encoding the video data stream into an analog format.

11. A video board for use in a computer graphics system, the system having memory, first and second data buses and a storage medium, the board comprising: a digital video input for receiving a video data stream; a YUV coding device in communication with the video input for processing the video data stream into a YUV data stream; a formatter in communication with the YUV coding device for processing the YUV data stream; a plurality of lookup tables in communication with the YUV coding device for adjusting contrast and brightness of the YUV data stream; a sealer in communication with the YUV coding device for scaling the YUV video data stream; and a bus interface in communication with the lookup tables for communicating the YUV data stream across the first data bus to system memory.

12. The board of claim 11 wherein the data stream is an uncompressed video data stream.

13. The board of claim 12 further comprising a JPEG device in communicating with the YUV decoding device for compressing an uncompressed video stream.

14. The board of claim 13 wherein the bus interface is also in communication with the JPEG device for communicating the uncompressed video data stream across the first data bus to system memory.

15. The board of claim 11 further comprising a composite video encoder in communication with the YUV coding device for encoding the video data stream into an analog format .

16. The board of claim 11 wherein the YUV data stream is further communicated across the second data bus to the storage medium.

17. The board of claim 14 wherein the uncompressed video data stream is further communicated across the second data bus to the storage medium.