Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
  • G06K19/07745—Mounting details of integrated circuit chips
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
  • G06K19/07745—Mounting details of integrated circuit chips
  • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/481—Disposition
  • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73265—Layer and wire connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• the present invention relates to an electronic memory device and a method for assembling this device according to the claims.
• the present invention aims to provide a solution to these various problems by an electronic memory device of a particularly reliable and flexible construction in its applications.
• a miniaturized electronic memory device comprising a housing serving both as a housing and means for fixing an electronic sub-assembly to supports.
• Said electronic sub-assembly comprises an interconnection interface, on which is mounted at least one memory integrated circuit with read or read / write / write superimposed on the power supply.
• This box can be more or less fully incorporated into a support. It can assume more or less complex loads, it can be integrated mechanically, electronically and functionally.
• Said interconnection interface is fixed inside one end of the housing. Preferably, this fixing is carried out by insertion.
• the interface is crimped at least partially with one end of said housing.
• the interface comprises metallized zones arranged so as to ensure, after assembly, the connections between the terminals of an electrical current supply of at least one integrated circuit. These electrical contacts are located on said interconnection interface (central contacts). These electronic contacts can also be located on the housing (peripheral contacts).
• At least one memory integrated circuit is electrically and mechanically connected to surfaces of the interconnection interface, thus forming an electronic sub-assembly.
• at least one memory integrated circuit can be electrically and mechanically connected to one or two surfaces of the interconnection interface.
• an additional component can, for example be another memory integrated circuit or it can be a power supply.
• at least one terminal of at least one memory integrated circuit is electrically connected to at least one central contact of said interconnection interface and at least two terminals of an electrical power supply are electrically connected to at least two contacts central.
• the device is characterized in that one of the ends of said housing is formed so as to be able to fix said electronic sub-assembly to it by means of a fixing means.
• said housing comprises at least one tubular part making it possible to fix the housing in a pendant of said support.
• This pendant can, for example be a hole made in the support. This hole can be blind or through.
• the housing is preferably of tubular shape, but it can have any shape, provided that the shape is adapted to the function, for example by means of fixing or of the dimension of the electronic sub-assembly.
• this support is of electrically conductive material, but it can also be of purely dielectric material or of purely conductive material. Said fixing of the tubular part is carried out by way of example by deformation of another end of said housing or for example by screwed contact of a threaded zone of the housing. After being fixed on a support of electrically conductive material, this box can allow electrical contact between the subassembly and said support.
• This construction makes it possible to produce a robust miniaturized memory device, independently and universally usable, which can be mounted using the housing on a large sample of various supports.
• the housing serves both as mechanical protection, as a means of attachment to a support and as an electrical contact for the memory device.
• the memory device according to the invention can, given its reduced dimensions and its variable fixing means, be incorporated into a good number of objects without having any drawbacks by virtue of its presence.
• the device can be fully integrated in a support. It can for example assume functionally significant loads on this support. But it is also conceivable that the device is electronically isolated from this support, that it is even hidden or incorporated in .) -
• the casing can be covered, for example, by a detachable cover or by a detachable ad hoc clamp, so as to be able to temporarily cover the memory device.
• the memory device may contain information relating to the object in which it is incorporated or to the person carrying the object. This information can give indications as to the provenance or the belonging of the object or the person. This information can also give indications as to the identity or state of the object or the person.
• the device serves as a curriculum vitae of the support or the object of which this support is part. During the entire lifetime of this support or this object, it can store important data or information. More generally, the device serves as a memory keeper for elements located in its environment.
• the memory device is specially adapted to be incorporated in printed circuit boards as a support. It is not necessary to incorporate the device, it can be simply fixed to an object.
• the memory device is thus accessible to writing / reading and to the supply of electric current, so that said device keeps information relating to the state of these printed cards during their production process and during their use. future. Thanks to the detachable cover or to the detachable ad hoc clamp, the memory device remains protected during passages in hostile environments during the production process of printed cards or during their future use.
• FIG. 1 is a schematic side view and shows a first preferred embodiment of a memory device according to the invention with an electronic sub-assembly comprising a single integrated memory circuit.
• FIG. 2 is a schematic side view and shows a second preferred embodiment of a memory device according to the invention with an electronic sub-assembly comprising two integrated memory circuits.
• FIG. 3 is a schematic side view and shows a third preferred embodiment of a memory device according to the invention with an electronic sub-assembly comprising an integrated memory circuit and an additional component.
• FIG. 4 is a schematic side view and shows a fourth preferred embodiment of a memory device according to the invention with an electronic sub-assembly comprising a single integrated memory circuit.
• FIG. 5 is an elevational view of the first preferred embodiment of a memory device according to Figure 1 to show the partial insertion of the interconnection interface of the electronic sub-assembly.
• - Figure 6 is a side view of the first preferred embodiment of a memory device according to Figure 1 and after riveting the housing on a support.
• - Figure 7 is a side view of a memory device according to the invention with a fifth preferred embodiment with an integrated memory circuit and after screwing the housing on a support.
• FIG. 8 is a side view of the fifth preferred embodiment of a memory device mounted on a support according to Figure 7 with a detachable cover.
• FIG. 9 is a side view (left) and in elevation (right) of the first preferred embodiment of a memory device mounted on a support according to Figure 6 with a detachable ad hoc clamp.
• FIG. 1 is shown in side schematic view a first preferred embodiment of a memory device according to the invention.
• a box 1 there is an interconnection interface 3 and on said interconnection interface 3 is electrically and mechanically connected an integrated memory circuit 2.
• the interconnection interface 3 and the integrated memoi ⁇ re circuit 2 form a electronic sub-assembly 17.
• the interconnection interface 3 is set with the housing 1.
• the memory integrated circuit 2 is located inside the said housing 1 on the upper surface of the interconnection interface 3 and is covered with 'a protective layer 21.
• Said housing 1 serves as a housing for said integrated memory circuit 2.
• the housing 1 is of electrically conductive material.
• the housing 1 is for example metallic or it is of dielectric material with electrical conduits or it is of dielectric material without electrical conduits.
• the housing 1 has a circular symmetry (see FIG. 5) and is arranged with a clearance 14.
• the housing 1 has a low deformable end 4 with a larger diameter compared to a high deformable end 9 with a smaller diameter.
• the low deformable end 4 serves to insert the electrical subassembly using the interconnection interface 3,
• the high deformable end 9 serves to fix at least one tubular part due to the housing 1 in a pendant of support. This pendant can, for example be a hole made in the support.
• This hole can be blind or through. Note that this very compact and robust configuration allows the device according to the invention to be used for realizing very miniaturized executions.
• the diameter of said housing 1 is approximately 4mm 2, however its height is approximately 1.6mm.
• This tubular casing 1 can be obtained for example by a forming method known to those skilled in the art.
• Said interconnection interface 3 can be a printed circuit comprising metallized zones on its two surfaces.
• the integrated memory circuit 2 is mounted on the upper surface 3.1.
• the interconnection interface 3 is made at the base of plastic material and therefore consists, for example, of a thin sheet of polyimide with layers of metallized zones.
• Said integrated memory circuit 2 includes terminals which make it possible to provide, by electrical wires (bonding), the connections between the integrated circuit 2 and the metallized zones of the interconnection interface 3. These connections could also be made by thermocompression (bumps). ) or any other known method.
• integrated memory circuits 2 of EEPROM (Electrically Erasable Programable Read-Only Memory) type are known which can be read, or even read and written, directly on the power supply terminals.
• EEPROM Electrical Erasable Programable Read-Only Memory
• a first supply pole of the integrated memory circuit 2 is connected to a central contact 7 on the lower surface 3.2 via a metallized hole 16.
• a second supply pole of the integrated memory circuit 2 is connected to a part 6 and a peripheral contact 700 which is electrically conductive and accessible from outside the housing 1. In this configuration, a reading system will therefore be able to access the two electrical current supply terminals of the integrated memory circuit 2 by establishing two contacts , one with the central contact 7 of the interconnection interface 3, the other with the peripheral contact 700 of the housing 1.
• Said interconnection interface 3 is set with at least one fixing part 5 of a low deformable end 4 of said housing 1. This insertion can be done after having made the connections between the integrated memory circuit 2 and the metallized areas of the interconnection interface 3.
• the interconnection interface 3 is partially crimped by a tubular part of the housing 1 (see FIG. 5).
• a ductile electrical contact material 6, for example gold or silver the electrical contacts 6 are established almost automatically under pressure during insertion and without welding being carried out. is necessary.
• the integrated memory circuit 2 can be covered with a protective layer 21.
• This protective layer 21 may, for example consist of a drop of glue or resin hardened.
• the memory device according to the invention represents several advantages in comparison with a similar memory device published in the application. of international patent PCT / CH93 / 00133 of May 24, 1993.
• This electronic label does not have the advantages of a tublaire housing and shows the disadvantage of a complicated assembly process, requiring a quantity of glue attachment for link the various elements.
• the present invention also has the advantage that the entire lower surface 3.2 of the interconnection interface 3 is accessible from the outside. This allows in the realization of several metallized holes through the interconnection interface 3 accessible from the outside (see Figures 2, 3 and 4).
• the box 1 plays both an electrical role by serving as an electrical contact, and it plays a mechanical role by ensuring the rigidity of the assembly of the memory integrated circuit 2 and of the central contact 7.
• its role in terms of mechanical and electronic is not limited to this, which is apparent from the following figures.
• Figure 2 is shown in side schematic view a second preferred embodiment of a memory device according to the invention with an integrated memory circuit and an additional component, which represents a second integrated memory circuit.
• the first and second preferred embodiments are similar in most details. Thus we refer for these details to the description of Figure 1 and discuss only the differences from the first preferred embodiment according to Figure 1 below.
• the additional component can be any electronic element, active or passive. In this preferred embodiment it is by way of example a second integrated memory circuit 20, but it can also be. a control circuit or an input / output interface in silicon. Said two integrated memory circuits 2.20 are mounted by thermocompression on the opposite surfaces of the interconnection interface 3, the integrated memory circuit 2 is mounted on the upper surface 3.1, the integrated memory circuit 20 is mounted on the lower surface 3.2. The two integrated memory circuits 2.20 are each covered with a protective layer 21. Said two integrated memory circuits 2.20 and the interconnection interface 3 form an electronic sub-assembly 17.
• the two power supply poles of the first integrated circuit treat ⁇ moire 2 of the upper surface 3.1 are connected to two central contacts 7,70 on the upper surface 3.1 .
• the second integrated memory circuit 20 of the lower surface 3.2 its two supply poles are connected to two central contacts 7,70 respectively on the lower surface 3.2.
• These two central contacts 7,70 are in turn connected by means of the two metallized holes 16,160 with respectively two central contacts 7,70 on the upper surface 3.1.
• These central contacts 7.70 on the upper surface 3.2 are connected to two parts 6.60 and to two peripheral contacts 700.7000 respectively, separated from each other and electrically conductive and accessible from outside the housing 1.
• FIG. 3 is shown in side schematic view a third preferred embodiment of a memory device according to the invention with an integrated cir ⁇ cooked memory and an additional component, which represents a power supply.
• Said integrated memory circuit 2 and said electric current supply 22 are mounted on the opposite surfaces of the interconnection interface 3, the integrated memory circuit 2 is mounted on the upper surface 3.1, the additional component 22 is mounted on the lower surface 3.2. They are both covered with a protective layer 21. Said integrated memory circuit 2, the power supply 22 and the interconnection interface 3 form an electronic sub-assembly 17.
• the two supply poles of the integrated memory circuit 2 of the upper surface 3.1 are connected to two central contacts 7, 70 on the upper surface 3.1. These two central contacts 7,70 are connected via the two metallized holes 16,160 with respectively two central contacts 7,70 on the lower surface 3.2. These two central contacts 7.70 on the upper surface 3.2 are additionally connected to two parts 6.60 and to two peripheral contacts 700.7000 respectively, separated from each other and electrically conductive and accessible from the outside. of the housing 1. As for the supply of electric current 22 to the lower surface 3.2, its two power supply poles are also connected to the two central contacts 7.70 on the lower surface 3.2. Thus, a reading system will therefore be able to access the two electrical power supply terminals of said memory integrated circuit 2 and the electrical power supply 22 by establishing two contacts, one with the peripheral contact 700 and the other with the peripheral contact 7000 of said housing 1.
• an electric current supply 22 can for example be simply a coil as a source of electricity or it can for example be a accumulator with a system for stabilizing the electric current.
• an electric current supply 22 can for example be simply a coil as a source of electricity or it can for example be a accumulator with a system for stabilizing the electric current.
• the integrated memory circuit 2 can be supplied with electric current by this power supply, which increases the performance and independence of the device with memory according to the invention, because the integrated memory circuit 2 can now be supplied with the electric current supply 22.
• peripheral contacts 700, 7000 of said box 1 it is possible not to make the peripheral contacts 700, 7000 of said box 1 and to supply the electric current supply for example by an RF coil, which thus serves both as a source of electricity and as a means of reading. / writing from the outside, so that said memory device can document information relating to the curriculum vitae of this medium 8.
• Figure 4 is shown in schematic side view a fourth preferred embodiment of a memory device according to the invention with a circuit baked integrated memory.
• an integrated memory circuit 2 and the interconnection interface 3 form an electronic sub-assembly 17.
• the two power supply poles of the integrated circuit memory 2 of the upper surface 3.1 are rehesed with two cen ⁇ traux contacts 7.70 on the upper surface 3.1.
• These two central contacts 7,70 are connected via the two metallized holes 16,160 with respectively two central contacts 7,70 on the lower surface 3.2.
• These two central contacts 7.70 on the lower surface 3.1 are separated from each other electrically and from the housing 1. They are accessible from the outside through the central contacts 7.70 of the interconnection interface 3, thus allow the supply of electric current and the access of a read / write system to the integrated circuit 2.
• FIG. 5 is shown in elevation view the first preferred embodiment of a memory device according to FIG. 1 to show the insertion of the electronic sub-assembly 17 using the interface d 'interconnection.
• This side view clearly shows that the interconnection interface 3 can, for example, be partially crimped by a tubular fixing part 5 of a low deformable end 4 of the housing 1.
• This fixing part 5 represents for example claws , which allow crimping the interconnection interface 3.
• This insertion is a method known to those skilled in the art. It is proven, robust and durable.
• Figure 6 is shown in side view of the first preferred embodiment of a memory device according to Figure 1 and after riveting as a means of fixing the housing on a support.
• Said housing 1 is arranged with a clearance 14 to facilitate the fixing of said memory device on said support 8 and that said housing 1 is arranged with a high deformable end 9 to be riveted on said support 8.
• this support 8 is of electrically conductive material.
• the housing 1 allows electrical contact between the interconnection interface 3 and said support 8 made of electrically conductive material.
• the fixing means F therefore consists in a deformation of said high deformable end 9 in a hole 15 made in said support 8.
• a riveting is a method known to the skilled person.
• Figure 7 is shown in side view a memory device according to the invention with a fifth preferred embodiment with an integrated memory circuit and after screwing as a means of fixing the housing on a support.
• the first and fifth preferred embodiments are similar in most details. We refer for these details to the description of FIG. 1 and subsequently discuss only the differences with respect to the first preferred embodiment according to FIG. 1.
• the housing 1 is arranged with a threaded area 11 to be screwed dasn a tapped hole 12 on a support 8, preferably on a support 8 of electrically conductive material.
• the screwing as fixing means F thus allows electrical contact between the interconnection interface 3 and said support 8 of electrically conductive material through the housing 1.
• the housing 1 and its thread 11 can, for example, be obtained by turning.
• This bar turning as thread manufacturing as well as screwing as F fixing moven are methods known to those skilled in the art.
• the memory device according to the invention can, in view of its reduced dimensions and its variable fixing means, be incorporated into a good number of objects without having any drawbacks due to its presence. It is thus possible, as shown in FIG. 7, to drown the memory device entirely in the support 8, so that the memory device is concealed in the support 8.
• FIG. 8 is shown in side view a fifth preferred embodiment of a memory device mounted on a support according to FIG. 7 with a detachable cover, in order to be able to temporarily cover the memory device.
• This detachable cover 13 is for example metallic or plastic.
• the detachable cover 13 has a circular symmetry and is arranged in such a way as to be able to contain the memory device almost completely while being easily detachable.
• Said memory device is miniaturized robust, independently and universally usable and is mounted using the housing 1 on a large sample of various supports 8.
• the fact that the detachable cover 13 can cover a memory device results in at least two advantages:
• the memory device can be concealed almost completely with this detachable cover 13.
• the memory device thus concealed may contain information relating to an object in which it is incorporated or to a person carrying the object. This information can give indications as to the provenance or the belonging of the object or the person. This information can also give indications as to the identity or the state of the object or the person.
• the memory device can be provided with an additive protection with this detachable cover 13. This additive protection can be of great importance, for example when using the memory device as an indicator incorporated in memory cards. printed circuits during their production process. In this indicator function, the device can keep information relating to the state of these printed cards during their production process. Additional protection is necessary, since the production of printed boards also includes passages of the device in hostile environments, for example during component welding operations, wave welding, passage through the oven, etc.
• the detachable cover 13 can easily be detached to access the memory device.
• the invention therefore claims the use of an electronic memory device, characterized in that said memory device is incorporated in a printed circuit board as a support 8, that said memory device is accessible for writing / reading and to the power supply, so that said memory device keeps information relating to the state of these printed cards during their production processes and during their future use.
• FIG. 9 is shown in lateral view (on the left) and in elevation (on the right) a first preferred embodiment of a memory device mounted on a support according to FIG. 6 with a detachable ad hoc clamp 10, in order to be able to temporarily cover the memory device.
• This detachable ad hoc clamp 10 is for example metallic or dielectric or plastic.
• the detachable cover 10 has a circular symmetry and is arranged in such a way as to be able to contain the memory device almost completely and to be easily, for example using a detachable incorporated spring function.
• this detachable ad hoc clamp 10 it is similar to that of the detachable cover 13 and we thus refer to the description of the detachable cover 13 according to FIG. 8.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• Credit Cards Or The Like (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Semiconductor Memories (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=4203886

Family Applications (1)

Country Status (6)

Families Citing this family (9)

Family Cites Families (17)

• 1995
  • 1995-04-07 US US08/557,027 patent/US5703395A/en not_active Expired - Fee Related
  • 1995-04-07 EP EP95913841A patent/EP0704092A1/de not_active Withdrawn
  • 1995-04-07 CA CA002165169A patent/CA2165169A1/en not_active Abandoned
  • 1995-04-07 KR KR1019950705762A patent/KR960703275A/ko not_active Withdrawn
  • 1995-04-07 WO PCT/CH1995/000079 patent/WO1995028713A1/fr not_active Application Discontinuation
  • 1995-04-07 JP JP7526597A patent/JPH09501533A/ja active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events