[go: up one dir, main page]

EP0522413A3 - A high impedance technique for testing interconnections in digital systems - Google Patents

A high impedance technique for testing interconnections in digital systems Download PDF

Info

Publication number
EP0522413A3
EP0522413A3 EP19920111025 EP92111025A EP0522413A3 EP 0522413 A3 EP0522413 A3 EP 0522413A3 EP 19920111025 EP19920111025 EP 19920111025 EP 92111025 A EP92111025 A EP 92111025A EP 0522413 A3 EP0522413 A3 EP 0522413A3
Authority
EP
European Patent Office
Prior art keywords
high impedance
digital systems
impedance technique
testing interconnections
interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19920111025
Other versions
EP0522413A2 (en
Inventor
William D. Farwell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0522413A2 publication Critical patent/EP0522413A2/en
Publication of EP0522413A3 publication Critical patent/EP0522413A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP19920111025 1991-07-03 1992-06-30 A high impedance technique for testing interconnections in digital systems Withdrawn EP0522413A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72513491A 1991-07-03 1991-07-03
US725134 1991-07-03

Publications (2)

Publication Number Publication Date
EP0522413A2 EP0522413A2 (en) 1993-01-13
EP0522413A3 true EP0522413A3 (en) 1993-03-03

Family

ID=24913294

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19920111025 Withdrawn EP0522413A3 (en) 1991-07-03 1992-06-30 A high impedance technique for testing interconnections in digital systems

Country Status (4)

Country Link
US (1) US5473617A (en)
EP (1) EP0522413A3 (en)
JP (1) JPH05256921A (en)
KR (1) KR930002938A (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715254A (en) * 1994-11-21 1998-02-03 Texas Instruments Incorporated Very low overhead shared resource boundary scan design
US5715255A (en) * 1994-11-21 1998-02-03 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5732091A (en) * 1994-11-21 1998-03-24 Texas Instruments Incorporated Self initializing and correcting shared resource boundary scan with output latching
US6694465B1 (en) * 1994-12-16 2004-02-17 Texas Instruments Incorporated Low overhead input and output boundary scan cells
EP0717287B1 (en) * 1994-12-16 2004-10-13 Texas Instruments Incorporated Input and output boundary scan cells
US5847561A (en) * 1994-12-16 1998-12-08 Texas Instruments Incorporated Low overhead input and output boundary scan cells
US5701307A (en) * 1994-12-16 1997-12-23 Texas Instruments Incorporated Low overhead input and output boundary scan cells
GB9502646D0 (en) * 1995-02-10 1995-03-29 Texas Instruments Ltd Bus maintenance circuit
US5706296A (en) * 1995-02-28 1998-01-06 Texas Instruments Incorporated Bi-directional scan design with memory and latching circuitry
US5938783A (en) * 1995-04-28 1999-08-17 Texas Instruments Incorporated Dual mode memory for IC terminals
US5880595A (en) * 1995-04-28 1999-03-09 Texas Instruments Incorporated IC having memoried terminals and zero-delay boundary scan
US6055659A (en) * 1999-02-26 2000-04-25 Texas Instruments Incorporated Boundary scan with latching output buffer and weak input buffer
US5656953A (en) * 1995-05-31 1997-08-12 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5828827A (en) * 1995-09-25 1998-10-27 Motorola, Inc. Data processing system for performing a test function and method therefor
US5666071A (en) * 1995-12-01 1997-09-09 Advanced Micro Devices, Inc. Device and method for programming high impedance states upon select input/output pads
US5719879A (en) * 1995-12-21 1998-02-17 International Business Machines Corporation Scan-bypass architecture without additional external latches
US5717701A (en) * 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
US5892778A (en) * 1997-06-30 1999-04-06 Sun Microsystems, Inc. Boundary-scan circuit for use with linearized impedance control type output drivers
JPH11265597A (en) * 1998-01-16 1999-09-28 Mitsubishi Electric Corp Semiconductor integrated circuit device
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6370664B1 (en) * 1998-10-29 2002-04-09 Agere Systems Guardian Corp. Method and apparatus for partitioning long scan chains in scan based BIST architecture
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6380724B1 (en) 1999-11-16 2002-04-30 Advanced Micro Devices, Inc. Method and circuitry for an undisturbed scannable state element
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6574758B1 (en) 2000-03-10 2003-06-03 Cisco Technology, Inc. Testing a bus coupled between two electronic devices
US6898749B2 (en) * 2000-09-20 2005-05-24 Texas Instruments Incorporated IC with cache bit memory in series with scan segment
US6411152B1 (en) 2001-09-24 2002-06-25 Broadcom Corporation Conditional clock buffer circuit
EP1308735A1 (en) * 2001-11-02 2003-05-07 Siemens Aktiengesellschaft Electronic component with output buffer control
US6971038B2 (en) 2002-02-01 2005-11-29 Broadcom Corporation Clock gating of sub-circuits within a processor execution unit responsive to instruction latency counter within processor issue circuit
US6950973B2 (en) 2002-04-22 2005-09-27 Broadcom Corporation Dynamic scan circuitry for A-phase
US6686775B2 (en) 2002-04-22 2004-02-03 Broadcom Corp Dynamic scan circuitry for B-phase
US6639443B1 (en) 2002-04-22 2003-10-28 Broadcom Corporation Conditional clock buffer circuit
US20060156098A1 (en) * 2004-11-30 2006-07-13 Bawany Mahuammad A Method and apparatus for testing an electronic device
JP2007003338A (en) * 2005-06-23 2007-01-11 Nec Electronics Corp Semiconductor device, and testing method therefor
US7779372B2 (en) 2007-01-26 2010-08-17 Apple Inc. Clock gater with test features and low setup time
US8073996B2 (en) * 2008-01-09 2011-12-06 Synopsys, Inc. Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof
TWI437243B (en) 2010-12-30 2014-05-11 Test Research Inc Electrical connection defect simulation test method and system of the same
CN102565603B (en) * 2010-12-30 2015-08-12 德律科技股份有限公司 Electrical Connection Defect Simulation Test Method and System
KR20150073635A (en) * 2013-12-23 2015-07-01 에스케이하이닉스 주식회사 Stack chip and testing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
EP0364925A1 (en) * 1988-10-14 1990-04-25 Nec Corporation Semiconductor integrated circuit having i/o terminals allowing independent connection test
US5029133A (en) * 1990-08-30 1991-07-02 Hewlett-Packard Company VLSI chip having improved test access
US5115191A (en) * 1990-06-12 1992-05-19 Kabushiki Kaisha Toshiba Testing integrated circuit capable of easily performing parametric test on high pin count semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298173A (en) * 1987-05-29 1988-12-05 Matsushita Electric Ind Co Ltd Integrated circuit
JPH081457B2 (en) * 1989-09-29 1996-01-10 株式会社東芝 Testability circuits in digital integrated circuits.
JP3226293B2 (en) * 1991-04-24 2001-11-05 株式会社日立製作所 Semiconductor integrated circuit
US5202625A (en) * 1991-07-03 1993-04-13 Hughes Aircraft Company Method of testing interconnections in digital systems by the use of bidirectional drivers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
EP0364925A1 (en) * 1988-10-14 1990-04-25 Nec Corporation Semiconductor integrated circuit having i/o terminals allowing independent connection test
US5115191A (en) * 1990-06-12 1992-05-19 Kabushiki Kaisha Toshiba Testing integrated circuit capable of easily performing parametric test on high pin count semiconductor device
US5029133A (en) * 1990-08-30 1991-07-02 Hewlett-Packard Company VLSI chip having improved test access

Also Published As

Publication number Publication date
KR930002938A (en) 1993-02-23
EP0522413A2 (en) 1993-01-13
JPH05256921A (en) 1993-10-08
US5473617A (en) 1995-12-05

Similar Documents

Publication Publication Date Title
EP0522413A3 (en) A high impedance technique for testing interconnections in digital systems
EP0492944A3 (en) A high density connector system
GB2271477B (en) High-density coaxial interconnect system
GB2261075B (en) Impedance meter
GB9202996D0 (en) Apparatus for sorting tablets
EP0540464A3 (en) Piece-good sorting apparatus
EP0447038A3 (en) A system for establishing a communication path in a closely coupled computer system
TW303050U (en) Stepped multilayer interconnection apparatus and the method for making the same
GB2256332B (en) Testing telephone systems
GB2267629B (en) Signal error reduction in receiving apparatus
EP0415644A3 (en) Superconducting interconnection apparatus
GB2258173B (en) Sorting apparatus
EP0472833A3 (en) Serial link in an i/o system
EP0554626A3 (en) Time division multiplexer chip in a voice processing system
GB8805120D0 (en) Testing digital circuits
GB2254890B (en) Dredging apparatus
GB9121424D0 (en) Digital communications system and a receiving apparatus for use in the system
EP0565170A3 (en) Apparatus for use in a system for interconnecting appliances
EP0540155A3 (en) Digital limit checking system
GB8901623D0 (en) Apparatus for sorting coins
EP0513515A3 (en) Shielding system, in particular for a gammagraphy device
AU9148691A (en) A system for imaging objects in alternative geometries
GB8827996D0 (en) Improvements in cleaning equipment
EP0351356A3 (en) Sorting apparatus
EP0526726A3 (en) Connection device for use in an electrical circuitry system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19930824

17Q First examination report despatched

Effective date: 19960514

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19960725