EP0518714A1 - Current source adapted to rapid variations in the output voltage - Google Patents

Abstract

The invention relates to a current source delivering a constant current despite the violent voltage variations which may be applied at its output. This current source comprises two parallel branches, one a generating branch (Q5, R5), the other a reference branch (Q6, R6). The output current (Is) is held constant by keeping the potential difference at the terminals of the resistors (R5) of the generating branch constant, by means of a differential amplifier. All the transistors are of NPN type. Application to power supply for fast analog circuits. <IMAGE>

Description

The present invention relates to a current source which supports rapid voltage variations on its output without passing them on to the current output. This source owes this characteristic partly to its structure and partly to its production in NPN type transistors.

A current source is by definition a circuit which must supply stable current to another electronic circuit. But in fact, during operation, it sometimes happens that this second circuit, by changes of states, undergoes rapid variations in current, which are reflected on the output of the current source.

If the current source has a low impedance, it can supply the necessary current, but due to the low impedance there is a reaction which destabilizes the output current. If, on the contrary, the current source is at high impedance, it is more stable but cannot respond to rapid variations.

The diagram of a current source according to the known art is given in FIG. 1. It is very simple and includes a current mirror formed by the transistors Q1 and Q2 and by the current source Q3: this is controlled at starting from a reference voltage which is established at the terminals of a resistor Rref, and controlled in temperature by the standard V _BG and by the transistor Q _ref The transistor Q4 is mounted in mirror with the transistor Q3.

If R3 = R4 and if the transistors Q3 and Q4 have the same geometries, they debit the same currents and in particular Q3 debit a current equal to I _ref . If on the contrary, the transistor Q1 has a geometry "n" times larger than that of Q2, it flow "n" times more: for example if n = 5, the output current I _S is 6 times greater than the reference current I _ref (1I _ref through Q2 + 5I _ref through Q1).

This architecture has the advantage of being very simple, of requiring only a few transistors and of having a low consumption. It is improved in that the current mirror Q1 + Q2, in NPN transistors, which ensures the amplification makes it possible to overcome variations in current gain in transistor Q3, which is a PNP.

In fact, in fast bipolar technology, PNP transistors generally have more dispersion. gain than NPN transistors.

In addition, PNP transistors such as Q3 and Q4 have much lower dynamic performance than NPN transistors such as Q1 and Q2, because the stray capacitances of a PNP are greater than those of an NPN. Under these conditions, a rapid variation of the output current I _S (or of the voltage V _S at output) is not transmitted instantaneously on the basis of PNP Q3, because of its parasitic collector base capacity, and Q3 does not react. fast enough to correct this variation.

Finally, the modulation of the collector current I _C as a function of the collector-emitter voltage, known as the voltage "d"'Early", is very low for a PNP, which results in a dependence on the output current. I _S with the output voltage V _S hence a static imprecision.

• de réaliser une source de courant en utilisant exclusivement des transistors NPN
• de modifier l'architecture de cette source de courant, notamment en remplaçant le miroir de courant par un amplificateur différentiel, qui fonctionne de telle façon qu'il maintient une différence de potentiel constante aux bornes d'une résistance, ce qui assure un courant débité constant, quel que soit le potentiel sur la sortie La conséquence en est que la source de courant selon l'invention peut supporter des variations rapides de tension sur sa section : elle ne les repercute pas et continue de fournir un courant de sortie I_S stable.

To remedy these drawbacks, the invention proposes:

• to realize a current source using exclusively NPN transistors
• to modify the architecture of this current source, in particular by replacing the current mirror with a differential amplifier, which operates in such a way that it maintains a constant potential difference across a resistance, which ensures a constant current flow, whatever the potential on the output The consequence is that the current source according to the invention can withstand rapid voltage variations on its section: it does not repercussion and continues to provide a stable output current I _S.

More precisely, the invention relates to a current source adapted to rapid variations in voltage on its output, comprising a branch generating the output current formed by a first transistor in series with a first resistance, this current source being characterized in that it includes means keeping the potential difference across said resistance constant.

• figure 1 : schéma électrique d'une source de courant selon l'art connu, exposé précédemment ;
• figure 2 : schéma électrique d'lune source de courant selon l'invention ;
• figures 3 à 5 : courbes de comparaison, pour une variation imposée (figure 3), entre la réponse de la source selon l'art connu (figure 4) et la réponse de la .source selon l'invention (figure 5).

The invention will be better understood from the more detailed description which now follows, in conjunction with the appended figures, which represent:

• Figure 1: electrical diagram of a current source according to the known art, exposed above;
• Figure 2: electrical diagram of a current source according to the invention;
• Figures 3 to 5: comparison curves, for an imposed variation (Figure 3), between the response of the source according to known art (Figure 4) and the response of the source according to the invention (Figure 5).

FIG. 2 gives the electrical diagram of the source, of current according to the invention.

Fed between a positive voltage + V _DC and a negative voltage - V _EE , the branch which supplies a reference current I _ref is substantially the same as that of FIG. 1: a transistor Q _ref and a resistor R _ref , controlled by temperature by a voltage source V _BG , control the current flowing through a transistor Q6, in series with a resistor R6 located between the emitter of Q6 and the collector of Q _ref .

The branch which constitutes the current source proper comprises a transistor Q5, connected to the + V _DC power _supply , in series with a resistor R5, the free end of which constitutes the output terminal of the circuit. The bases of the transistors Q5 and Q6 are joined together, and polarized from V _CC by a resistor R8.

The basis of the invention is to maintain a constant potential difference across the resistor R5, which ensures a constant flow current I _S whatever the output potential V _S. This is obtained by means of a differential amplifier, formed by the transistors Q7 and Q8. The transistor Q7 has its base joined at the low point V _S , free end of the resistor R5 and its collector connected to the power supply. The transistor Q8 has its base joined at the low point V _B of the resistor R6, and its collector joined at the point V _H common to the resistor R8 and at the bases of the transistors Q5 and Q6.

The transmitters of the differential amplifier Q7 + Q8 are connected to a bias source, which draws a current I _pol towards the supply -V _EE .

We can observe the symmetry of the diagram, apart from the reference Q _ref + R _ref , as well as the supply of Q7 from V _CC and that of Q8 from V _H. But the voltage at point V _H corresponds, to an emitter / base junction of Q5 near, to the voltage at a first "high" end of R5, and the voltage at point V _B corresponds, through the differential amplifier, to the voltage at a second "low" end of R5, which is also the output voltage V _S.

This scheme could work, with adaptation, with PNP type transistors, but, to achieve the objective which is that the current I _S remains constant if the voltage V _S fluctuates, it is imperative to carry it out exclusively with NPN transistors, that have less basic stray capacity.

In operation, the reference current source Q _ref + R _ref ensures a constant potential difference V _H - V _B across the resistor R6 (at a junction near), and, at equilibrium, the voltage at point V _B is controlled by the output voltage at point V _S , or voltage at the "low" point of R5.

But simultaneously, the voltage at the high point V _H of R5 (at a junction near) is slaved to the output potential V _S , through the differential amplifier looped back in unity gain. Thus, if the output voltage V _S fluctuates , as a result of operation, the voltage in V _H accompanies it in its fluctuation, and as the difference V _H - V _B is constant, the difference V _H - V _S is also constant, and the output current I _S is constant .

The current amplification is obtained by the geometry of the symmetrical components Q5 + R5 and Q6 + R6. If the current I _S must be equal to "n" times the current I _ref the geometric dimensions of the transistor Q5 are equal to "n" times those of the transistor Q6, and the value of the resistance R5 is equal to "1 / n" times that of resistance R6. Thus, purely by way of explanation, to output 3 mA with a reference current of 500 A, as in the example in Figure 1, it is necessary that Q5 has a geometry equal to 6 times that of Q6, and that R5 = R6 / 6.

• en dynamique, on s'affranchit des effets capacitifs de la base de Q7 sur la sortie V_S. Seul subsiste un effet capacitif sur le transistor Q_ref, mais il n'intervient pas sur la sortie et il peut être réduit en diminuant la géométrie de Q_ref ;
• en statique, la variation de I_S en fonction de V_S depend de l'effet early du transistor Q_ref, qui est réduite parce qu'un transistor NPN a une tension d'early plus grande qu'un PNP, ainsi que de l'offset de l'amplificateur utilisé.

The exclusive use of NPN transistors which have less basic parasitic capacitance leads to two types of advantages:

• in dynamics, one overcomes the capacitive effects of the base of Q7 on the output V _S. Only a capacitive effect remains on the transistor Q _ref , but it does not intervene on the output and it can be reduced by reducing the geometry of Q _ref ;
• in static, the variation of I _S as a function of V _S depends on the early effect of the transistor Q _ref , which is reduced because an NPN transistor has an early voltage higher than a PNP, as well as offset of the amplifier used.

The curves of FIGS. 3 to 5 illustrate the advantage of the NPN transistors, and of the circuit according to the invention, compared with the known art.

The curve of figure 3 represents the form of tension which one forces on the exit V _S : it varies from 2 V in 1 ns, that is to say a variation of 2000 V / µS, better known under the name of "slew-rate" We observe how the current source reacts in the two cases of variation, rising edge and falling edge.

In the case of the known art, in FIG. 4, the quasi-straight line 1 gives the reaction of the reference current I _ref , amplified to be brought to the level of the output current I _S. The current I _ref is very constant, but the output current in curve 2 undergoes two rebounds, better known under the name of "overshoot", one on the rising edge, the other on the falling edge. For a pulse at 2000 V / µS, the overshoot reaches 115%, and it takes 4.8 ns for the circuit to return to equilibrium + 5%.

Curves 3 and 4 in FIG. 5 give the correspondents of the previous curves, but for the current source according to the invention. For the same 2 V pulse, with a slew-rate of 2000 V / µS, we see that the reference current (curve 3) undergoes a very slight disturbance, but the output current (curve 4) is much less disturbed than in known art. The overshoot is limited to 9% and the disturbance lasts only 1.5 ns.

$${\text{C}}_{\text{d}}\text{= 0, 15 pF}$$

ce qui revient à diviser par 15, 3 la capacité de la source, et donc à améliorer son temps de réponse, permettant ainsi que le courant débité soit indépendant des variations de la tension de sortie.This very significant improvement is due to the exclusive use in the current source according to the invention of NPN type transistors, which have less stray capacitances. A current source can be modeled, in the form of a current generator (I _d ), in parallel with a resistor (R _S ) and with a capacitance (C _d ). For the same generated current I _d = 3 mA, the current source of FIG. 1 (known art) has a resistance R _S = 10 k ohm and a capacity parasitic C _d = 2.3 pF, while the current source according to the invention has: $${\text{R}}_{\text{S}}\text{= 100k ohm}$$

$${\text{VS}}_{\text{d}}\text{= 0.15 pF}$$

This amounts to dividing the capacity of the source by 15.3, and therefore improving its response time, thus allowing the current output to be independent of variations in the output voltage.

Claims (4)

Current source adapted to rapid voltage variations (V _S ) on its output, comprising a branch generating the output current (I _S ) formed by a first transistor (Q5) in series with a first resistor (R5), this source current being characterized in that it comprises means maintaining constant the potential difference across said resistor (R5). Current source according to claim 1, further comprising a reference branch formed by a reference voltage source (Q _ref + R _ref + V _BG ) in series with a second resistor (R6) and with a second transistor (Q6) , the bases of the first and second transistors (Q5, Q6) being joined and polarized through a resistor (R8) joined to a power supply (+ V _DC ), this current source being characterized in that said means consist of a third and a fourth transistor (Q7, Q8) mounted as a differential amplifier, the third transistor (Q7) having its collector connected to the positive power supply (+ V _DC ) and its base connected to the output (V _S ), while the fourth transistor (Q8) has its collector connected to the common "high" point (V _H ) at the bases of the first and second transistors (Q5, Q6) and to its base connected to the common point "low" (V _B ) between the second resistor ( R6) and said reference voltage source . Current source according to claim 2, characterized in that the transistors are of the NPN type. Current source according to claim 2, characterized in that the variations in the output voltage (V _S ) are copied by the differential amplifier (Q7, Q8) at the common "low" point (V _B ) of the reference branch as well as at the common point "high" (V _H ), keeping the potential difference across the terminals of the first resistor constant (R5).

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