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EP0481507A2 - Anordnung und Verfahren zur Steuerung der Eingabe von Zellen für ein ATM-Netzwerk - Google Patents

Anordnung und Verfahren zur Steuerung der Eingabe von Zellen für ein ATM-Netzwerk Download PDF

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Publication number
EP0481507A2
EP0481507A2 EP91117816A EP91117816A EP0481507A2 EP 0481507 A2 EP0481507 A2 EP 0481507A2 EP 91117816 A EP91117816 A EP 91117816A EP 91117816 A EP91117816 A EP 91117816A EP 0481507 A2 EP0481507 A2 EP 0481507A2
Authority
EP
European Patent Office
Prior art keywords
cell
memory
cells
buffer
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91117816A
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English (en)
French (fr)
Other versions
EP0481507A3 (en
Inventor
Tetsuo c/o Fujitsu Limited Tachibana
Eisuke c/o Fujitsu Limited Iwabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0481507A2 publication Critical patent/EP0481507A2/de
Publication of EP0481507A3 publication Critical patent/EP0481507A3/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
    • H04L2012/5637—Leaky Buckets

Definitions

  • the present invention generally relates to ATM (Asynchronous Transfer Mode) networks, and more particularly to an apparatus and method for controlling cells which are input to an ATM network.
  • ATM Asynchronous Transfer Mode
  • One of such high-speed communication networks is an ATM network.
  • a subscriber requests a band (frequency range) used by the subscriber to the ATM network when setting up a call.
  • the ATM network calculates a necessary band based on the requested band, and determines, on the calculated band, whether or not the call from the subscriber should be permitted. If the number of cells which are input to the ATM network greatly deviates from the number of cells corresponding to the requested band due to an evil intention or an unexpected matter, some of the input cells will be frequently destroyed in the ATM network. This will affects other calls transferred via the ATM network.
  • an ATM exchange l0 includes a subscriber interface unit l3 and an ATM switch 14.
  • the subscriber interface unit l3 is composed of a subscriber line terminating unit 11 and a cell input control unit l2.
  • the cell input control unit l2 which corresponds to the above-mentioned supervisory device, discards input cells if the number of input cells greatly deviates from the requested number of cells.
  • the cell input control unit l2 monitors the number of input cells which are supplied to the ATM switch 14. When the number of input cells is smaller than the requested number of cells, the cell input control unit 12 transfers the input cell from the subscriber line terminating unit 11 to the ATM switch 14.
  • the cell input control unit 12 operates in the following banner
  • the cell input control unit l2 includes a counter, which increases the counter value by "1" each time one input cell is received.
  • the counter value in the counter decreases by "1" each time a predetermined time elapses.
  • the input cell is discarded.
  • FA(t) ⁇ ( ⁇ is a tolerable value)
  • the input cell is permitted to be input to the ATM switch 14.
  • FA(t) > ⁇ the input cell is discarded.
  • the ATM network has a characteristic such that a plurality of calls exist in one interface.
  • the conventional cell input control unit 12 is not designed to process a plurality of calls in one channel.
  • An object of the present invention is to provide an apparatus and method capable of processing cells related to a plurality of calls in each channel.
  • an apparatus for controlling cells which are to be input to an ATM switch comprising: buffer means for storing a cell directed to the ATM switch; first memory means for storing, for each of different calls, the number of cells which are in the ATM switch; periodic calculation means, coupled to the first memory means, for periodically changing the number of cells for each of the different calls by an operation value; and control means, coupled to the first memory means, for determining whether the cell stored in the buffer means should be output to the ATM switch or discarded by referring to the number of cells which is stored in the first memory means and related to the cell stored in the buffer means.
  • the above object of the present invention is also achieved by a method for controlling cells which are to be input to an ATM switch, the method comprising the steps of; (a) storing a cell directed to the ATM switch in a buffer memory; (b) storing, for each of different calls, the number of cells which are in the ATM switch in a first memory; (c) periodically changing the number of cells for each of the different calls by an operation value; and (d) determining whether the cell stored in the buffer memory should be output to the ATM switch or discarded by referring to the number off cells which is stored in the first memory and related to the cell stored in the buffer memory.
  • FIG.2 is a block diagram of an ATM network system to which the present invention is applied.
  • the ATM network system shown in FIG.2 is composed of a broad band customer station network l00 and an ATM exchange 200. Terminal devices, such as a video phone and a data terminal equipment, are connected to a network terminal equipment NT via optical buses OB.
  • the network l00 and the exchange 200 are mutually connected via an optical subscriber line OSL.
  • the ATM exchange 200 is composed of a plurality of subscriber interface units IF, an ATM switch, an interface unit INTF and a call control processor CP.
  • FIG.3 shows a cell input control unit according to a first preferred embodiment of the present invention.
  • the cell input control unit shown in FIG.3 is composed of a cell input controller 15, a periodic subtraction unit l6, a timer 18, a memory access concurrence arbitration unit 19, a delay unit (buffer memory or register) 20, a cell counter memory 2l, an empty (dummy) cell pattern generator 22, a selector 23, a CPU interface unit 24 and a CPU 25 (which corresponds to the call control processor CP shown in FIG.2).
  • the cell input control unit is substituted for the cell input controller 12 shown in FIG.l.
  • An input cell transferred via an input highway from a subscriber line terminating unit as shown in FIG.1 is temporarily stored in the delay unit 20 formed with, for example, a buffer memory.
  • the cell input controller l5 discriminates the received call by using a virtual channel identifier (VCI) contained in a header area of the input cell.
  • VCI virtual channel identifier
  • a counter value in the cell counter memory 2l is read out from an area thereof specified by a memory address in which a cell counter value corresponding to the input cell (call) is stored.
  • the readout counter value is input to the arbitration unit 19, which determines whether or not the counter value is equal to or greater than a predetermined threshold value. If the result of this decision is affirmative, the input cell is discarded. If the result of the decision is negative, the input cell is output to the ATM switch, and then the counter value in the cell counter memory 21 is increased by +l under the control of the arbitration unit 19.
  • the periodic subtraction unit l6 sequentially supplies all memory addresses to the attribution unit l9 in response to a clock signal which is generated at predetermined intervals by the timer 18.
  • the all memory addresses are input to the cell counter memory 2l via the attribution unit 19, and the counter values stored in areas respectively indicated by the memory addresses are decreased by "1". Then, the updated counter values are written into the same areas via the attribution unit l9.
  • the cell input controller 15 When the cell input controller l5 determines that the cell counter value is smaller than the predetermined threshold value, the cell input controller 15 causes the selector 23 to select the input cell which is temporarily stored in the delay unit 20. The selected input cell is input to the ATM switch l4 (FIG.l). When it is determined by the cell input controller 15 that the cell counter value is equal to or greater than the predetermined threshold value, the cell input controller 15 makes the selector 23 select the empty cell pattern generator 22. The empty cell passes through the selector 23 and is then input to the ATM switch. Thereby, the input cell in the delay unit 20 is discarded.
  • FIG.4 shows the structure of the cell counter memory 2l, which has a storage area for each VCI.
  • the memory cell access concurrence arbitration unit 19 accesses the cell counter memory 2l and the periodic subtraction unit l6.
  • the periodic subtraction unit l6 sequentially generates the memory addresses in response to the periodical subtraction request.
  • the arbitration unit 19 outputs the received memory addresses to the cell counter memory 2l, and outputs the cell counter values read out from the cell counter memory 2l to the periodic subtraction unit 16.
  • the arbitration unit l9 subtracts "l" from the respective cell counter values, and writes the updated cell counter values into the cell counter memory 21.
  • the above-mentioned procedure is also carried out in response to a call to the cell counter memory 2l from the cell input controller 15.
  • FIG.5 shows the operation of the cell input controller l5.
  • the cell input controller l5 determines whether or not an input cell has been received.
  • step S1 is repeatedly executed.
  • step S2 the cell input controller l5 reads the cell counter value corresponding to the VCI of the received input cell from the cell counter memory 21.
  • step S3 the cell input controller l5 determines whether or not the received cell counter value is equal to or greater than the predetermined threshold value ( ⁇ ).
  • the cell input controller l5 controls the selector 23 so that the input cell is discarded. Then, the procedure returns to step Sl.
  • step S5 the cell input controller 15 instructs the selector 23 to pass the input cell in the delay unit 20.
  • the cell input controller l5 increases the cell counter value related to the call (VCI) being processed by "l”.
  • step S7 the cell input controller l5 writes the increased cell counter value in the corresponding area of the cell counter memory 2l. Then, the procedure returns to step Sl.
  • FIG.6 shows the operation of the periodic subtraction unit 16, which starts to operate in response to the clock signal which is generated by the timer l8 when it measures a predetermined time.
  • the periodic subtraction unit 16 sets an address A to 0.
  • the periodic subtraction unit 16 reads out the cell counter value specified by the address A from the cell counter memory 2l.
  • the periodic subtraction unit 16 subtracts "l" from the readout cell counter value, and determines, at step S11, whether or not the address A being considered is the last address of the cell count memory 21.
  • the periodic subtraction unit 16 increases the address A by "l" at step S12. Then, the procedure returns to step S9.
  • the result at step S11 is YES (VCI equal to "XX" has been accessed)
  • the periodic subtraction unit 16 ends the procedure shown in FIG.6 activated in response to the pulse signal from the timer 18.
  • the first preferred embodiment of the present invention it is possible to control cells related to different calls by storing the cell counter values corresponding to the respective VCIs.
  • the first embodiment of the present invention should be improved for the following reasons.
  • a second preferred embodiment of the present invention is intended to satisfy the above requirements.
  • FIG.7 is a block diagram of the second preferred embodiment of the present invention.
  • the second embodiment shown in FIG.7 is composed of a cell input controller 31, a timer 32, a periodic subtraction unit 33, a cell counter memory 34, a subtracted cell number memory 35, and a CPU interface 36 in addition to the aforementioned delay unit 20, the supply cell pattern generator 22, the selector 23 and the CPU 25.
  • the control procedure executed by the CPU 25 shown in FIG.7 is different from that by the CPU 25 shown in the previously described figures.
  • the cell input controller 3l, the periodic subtraction unit 33, the cell counter memory 34, the subtracted cell number memory 35 and the CPU interface unit 36 are mutually connected via an address line L1.
  • the cell input controller 3l, the periodic subtraction unit 33, the CPU interface unit 36 and the cell counter memory 34 are mutually connected via a counter line L2.
  • the cell input controller 31, the periodic subtraction unit 32, the CPU interface unit 36 and the subtracted cell number memory 35 are mutually connected via a cell subtraction line L3.
  • the timer 32 is connected to the cell input controller 3l, the periodic subtraction unit 33 and the CPU interface unit 36.
  • the CPU 25 is connected to the CPU interface unit 36.
  • the cell input controller 31 subtracts N x (t/T1) from the cell counter value in the cell counter memory 34 each time the input cell is received.
  • the resultant cell counter value (corrected cell counter value) is used or determining whether the input cell should be passes or discarded.
  • FlB(t) is the cell counter value
  • ⁇ is the tolerable value (the number of cells)
  • G(t) denotes the number of cells obtained during time t
  • T1 denotes the subtraction period of the periodic subtraction unit 33.
  • the number N which is to be subtracted from the cell counter value can be a fixed number, or a variable number which varies for each terminal or each call.
  • the subtracted cell numbers for the respective VCIs are stored in the subtracted cell number memory 35.
  • the memory address which is generated by the periodic subtraction unit 33 and which corresponds to the VCI contained in the header portion of the input cell is applied to not only the cell counter memory 34 but also the subtracted cell number memory 35. Thereby, the cell counter value corresponding to the input cell is read out from the cell counter memory 34, and the subtracted cell number (the number off cells to be subtracted) corresponding to the input cell is read out from the subtracted cell number memory 35.
  • the periodic subtraction unit 33 subtracts, for every period T1, the variable number from the cell counter value, which is written into the cell counter memory 34.
  • FIG.8 shows the structure of the cell counter memory 34
  • FIG.9 shows the structure of the subtracted cell number memory 35.
  • the cell counter memory 34 has storage areas corresponding to the respective VCIs
  • the subtracted cell number memory 35 has storage areas corresponding to the respective VCIs.
  • the memory address supplied in common to the memories 34 and 35 indicates the storage areas of the memories 34 and 34 corresponding to the same VCI.
  • a cell counter value A(0) is stored in the storage area of the cell counter memory 34 corresponding to the VCI "0”
  • a subtracted cell number B(0) is stored in the storage area of the subtracted cell number memory 35 corresponding to the VCI "0".
  • Identical subtracted cell numbers B( ) or different subtracted cell numbers B( ) can be defined for the respective VCIs.
  • each of the memories 34 and 35 has four storage areas corresponding to four VCIs for the sake of simplicity, the present invention is not limited to four storage areas. Since each time the call is received, the CPU 35 stores the corresponding subtracted cell number in the memory 35 via the input cell controller 31 and the CPU interface 36.
  • FIG.10 shows the header of the cell processed by the ATM exchange.
  • One cell is composed of 53 octets, each consisting of eight bits.
  • Octet "l” has a busy field, a request field (REQ) and a VPI field.
  • Octet "2" has a VPI (Virtual Pass Identifier) field and a VPI/VCI field.
  • Octet "3” has a VCI field.
  • Octet "4" has a VCI field, a PR field and a PT field.
  • Octet '5" has an HEC field.
  • the header of the cell is composed of octets "1" through "5".
  • the basic cell subtraction period corresponds to a time necessary for two cells to pass through the structure shown in FIG.7.
  • the subtraction period of the cell counter memory 34 corresponds to a time necessary for four cells to pass through the structure shown in FIG.7.
  • the tolerable (threshold) value ⁇ is 2.
  • cells are transmitted via the input and output highways at predetermined identical intervals (cell period), as shown in FIG.ll.
  • the timer 32 operates in synchronism with the input cell, and is a l2-nary counter which executes the count operation in synchronism with a clock signal having a period equal to l/3 the cell period.
  • FIG.ll is a timing chart showing the operation of the apparatus shown in FIG.7 which operates under the above-mentioned conditions.
  • the cell count number is 0, and the subtracted cell number is 2.
  • FIG.l2 shows the operation of the periodic subtraction unit 33.
  • the timer 32 activates the periodic subtraction unit 33 when it shows "3N + l".
  • the address E is supplied to the cell counter memory 34 and the subtracted cell number memory 35, and the cell counter value A(E) and the subtracted cell number B(E) are read out from the memories 34 and 35, respectively.
  • the periodic subtraction unit 33 subtracts the subtracted cell number B(E) from the cell counter value A(E).
  • the cell subtraction unit 33 determines whether or not the updated cell counter value A(E) is smaller than zero, that is, whether or not the updated cell counter value A(E) has a negative value. When it is determined, at step S23, that the cell counter value A(E) is a positive value, the procedure ends. When it is determined that the cell counter value A(E) is a negative value, the cell counter value is set to zero at step S24 in order to prevent it from having the minus sign.
  • the cell input controller 3l calculates the correction value from the subtracted cell number and the timer value indicated by the timer 32. In the example being considered, the correction value is equal to 0. Thus, the cell input controller 32 determines that the input cell in the delay unit 20 should be output to the ATM switch. At this time, the cell input controller 31 increments the cell counter value by l, and writes the incremented cell counter value into the cell count memory 34. Further, the cell input controller 3l instructs the selector 23 to select the delay unit 20.
  • FIG.l3 shows the operation of the cell input controller 3l.
  • the cell input controller 3l determines whether or not an input cell is received. Step 3l is repeatedly carried out until an input cell has been received.
  • the cell input controller 3l obtains the correction value, labeled D, by calculating INT[B(N) x (tl/Tl)] .
  • the cell input controller 3l determines whether or not (A(N) - D + 1) > ⁇ .
  • the cell input controller 3l instructs the selector 23 to select the empty cell pattern generator 22, so that the input cell in the delay unit 20 is discarded.
  • the cell input controller 3l instructs the selector 23 to select the delay unit 20.
  • the cell input controller 3l increases the cell counter value A(N) by l, and writes the increased cell counter value into the corresponding storage are of the cell counter memory 34. Then, the procedure returns to step S31. In the above-mentioned manner, it is determined whether the input cell should be discarded or passed each time the input cell is received.
  • the cell counter value is l
  • the subtracted cell number is 1
  • the correction value is 1
  • the corrected subtracted cell number is 1.
  • the cell input controller 3l determines that the input cell can be output to the ATM switch, and instructs the selector 23 to select the delay unit 20. Then, the cell input controller 3l increases the cell counter value by 1 and writes the increased cell counter value into the cell counter memory 34.
  • the cell counter value is 2
  • the subtracted cell number is 1
  • the correction value is l
  • the corrected subtracted cell number is 2.
  • the cell input controller 31 instructs the selector 23 to select the empty cell pattern generator 22, so that the empty cell pattern is output to the ATM switch.
  • the periodic subtraction unit 33 is periodically activated, more specifically, one time per one cell. According to the procedure shown in FIG.13, the periodic subtraction unit 33 decreases the cell counter value corresponding to the VCI. For example, the cell counter value corresponding to the VCI "0" is decreased at times tl and t9.
  • the periodic subtraction unit 33 is activated by the timer 32, and operates as follows.
  • the periodic subtraction unit 33 reads out the cell counter value corresponding to VCI "0" from the cell counter memory 34 and reads out the subtracted cell number corresponding to VCI "0" from the subtracted cell number memory 35. Then, the periodic subtraction unit 33 subtracts the subtracted cell number from the cell counter value.
  • FIG.l4 A description will now be given of a third preferred embodiment of the present invention with reference to FIG.l4.
  • the apparatus shown in FIG.l4 is composed of a cell input controller 43, a periodic subtraction counter 44, a cell counter memory 45, an input cell number gathering unit 46 and a timer 47 in addition to the aforementioned delay unit 20, the empty cell pattern generator 22, and the selector 23.
  • the input cell is input to the delay unit 20 and the cell input controller 43.
  • the periodic subtraction counter 44 increases its counter value by, for example, 1 in response to the timer value indicated by the timer 47.
  • the cell input controller 43 discriminates the VCI contained in the input cell, and reads out the cell counter value corresponding to the discriminated VCI from the cell counter memory 45. Then, the cell input controller 43 subtracts the counter value in the periodic subtraction counter 44 from the readout cell counter value. Then, the cell input controller 43 determines whether or not the result of this subtraction is equal to or greater than a tolerable value ⁇ . When the result of this determination is affirmative, the cell input controller 43 controls the selector 23 to select the empty cell pattern generator 22, so that the input cell is discarded.
  • the cell input controller 43 instructs the selector 23 to select the delay unit 20. In this case, the cell input controller 43 increases the cell counter value corresponding to the discriminated VCI by 1, and writes the increased cell counter value in the cell counter memory 45.
  • FIG.15 shows a variation of the configuration shown in FIG.l4.
  • a subtraction memory 48 is added to the configuration shown in FIG.14, and a cell input controller 50 is substituted for the cell input controller 43 in FIG.l4.
  • the subtraction memory 48 stores subtraction multiplying factors C(N) corresponding to the respective VCIs.
  • the periodic subtraction unit 44 periodically increases its counter value by l in response to the timer value indicated by the timer 47.
  • the cell input controller 50 discriminates the VCI of the input cell. Then, the cell input controller 50 calculates the number of cells which is to be subtracted by multiplying the subtraction multiplying factor C(N) by the current counter value D(t) in the periodical subtraction counter 44. After that, the input cell controller 50 calculates the the following: A(N) - D(t) x C(N) The input cell controller 50 compares the resultant value with the tolerable value ⁇ in order to determine whether the input cell should be passed or discarded.
  • the cell input number gathering unit 46 used in each of the configurations shown in FIGS.l4 and 15 reads the contents of the cell counter memory 45 in response to an instruction signal from a charging information management unit (not shown in FIG.l5) under the control of the processor CP (FIG.2).
  • the readout contents of the cell counter memory 45 can be used for the charging procedure or the traffic management.
  • FIG.16 shows the structure shown in FIG.15 in more detail.
  • a charge information management device 49 is connected to the input cell number gathering unit 46.
  • the cell input controller 50 is connected, via a line L4, the cell counter memory 45, the cell input number gathering unit 46 and the subtraction memory 48.
  • the memory address corresponding to the VCI of the input cell is transferred via the line L4.
  • the cell input controller 50 is connected to the cell counter memory 45 and the cell input number gathering unit 46 via a line L5.
  • the cell counter value is transferred via the line L5.
  • the cell input controller 50 is connected to the subtraction memory 48 via a line L6 through which the subtraction multiplying factor is transferred.
  • FIG.17 shows the structure of the cell counter memory 45
  • FIG.l8 shows the structure of the subtraction memory 48
  • the cell counter memory 45 has four storage areas respectively related to VCI “0" - "3".
  • the cell counter numbers A(0) - A(3) respectively related to the VCI “0” - VCI “3” are stored in the respective storage areas.
  • the subtraction memory 48 has four storage areas respectively related to VCI “0” - VCI "3".
  • the subtraction multiplying factors C(0) - C(3) respectively related to the VCI "0" - VCI "3” are stored in the respective storage areas.
  • the subtraction multiplying factors C(0) - C(3) are determined on the basis of the average band and/or maximum band declared by the respective subscribers when generating calls.
  • the input cell controller 50 determines whether or not A(N) - C(N) x D(t) ⁇ ⁇ .
  • the input cell controller 50 controls the selector 23 so that it selects the empty cell pattern generator 22. Hence, the input cell in the delay unit 20 is discarded. Then, the procedure returns to step S4l.
  • the cell input controller 50 instructs the selector 23 to select the delay unit 20, so that the input cell is transferred to the ATM switch.
  • the input cell controller 50 increases the cell counter value A(N) by l, and writes the increased cell counter value A(N) into the corresponding storage area of the cell counter memory 45.
  • the apparatus shown in FIG.16 has four VCIs (in actuality, 64k virtual channels are provided).
  • the periodic subtraction counter 44 has a period during which two cells can pass. The period of the periodic subtraction counter 44 corresponds to the interval between consecutive timer output signals which activate the count-up operation.
  • the tolerable value ⁇ 2.
  • the initial virtual channel is "0".
  • cells are transferred via the input and output highways at predetermined intervals.
  • the subtraction multiplying factor B(N) is equal to the period of the periodic subtraction counter 44, that is, "1".
  • the apparatus is initialized and the control procedure shown in FIG.l9 starts from time tl.
  • the input cell controller 50 reads out the cell counter value A(0) from the cell counter memory 45 and the subtraction multiplying factor C(0) from the subtraction memory 48.
  • the cell counter value is 0, and thus cell #l is output to the ATM switch.
  • cells #2, #3 and #4 are processed.
  • the periodic subtraction counter 44 increases its counter value by 1 at the interval during which two cells pass.
  • cell #5 is input to the delay unit 20 and the cell input controller 50.
  • the cell counter value A(0) is 4 and the periodic subtraction counter 44 indicates 2.
  • 4 - 2 x 1 2 , which coincides the tolerable value ⁇ equal to 2.
  • the input cell controller 50 passes the cell #5.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
EP19910117816 1990-10-19 1991-10-18 Apparatus and method for controlling cells input to atm network Withdrawn EP0481507A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP280882/90 1990-10-19
JP2280882A JPH04156138A (ja) 1990-10-19 1990-10-19 セル流入規制回路

Publications (2)

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EP0481507A2 true EP0481507A2 (de) 1992-04-22
EP0481507A3 EP0481507A3 (en) 1994-11-17

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EP19910117816 Withdrawn EP0481507A3 (en) 1990-10-19 1991-10-18 Apparatus and method for controlling cells input to atm network

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EP (1) EP0481507A3 (de)
JP (1) JPH04156138A (de)
AU (1) AU634426B2 (de)
CA (1) CA2053729C (de)

Cited By (4)

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Publication number Priority date Publication date Assignee Title
EP0566961A2 (de) * 1992-04-23 1993-10-27 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum Überprüfen der Einhaltung vorgegebener Übertragungsbitraten in einer ATM- Vermittlungseinrichtung
EP0711055A1 (de) * 1994-11-03 1996-05-08 Alcatel STR AG Verfahren und Vorrichtung zur Messung charakteristischer Grössen eines Stroms von Datenpaketen fester Länge in einem digitalen Übertragungssystem
US5528763A (en) * 1993-09-14 1996-06-18 International Business Machines Corporation System for admitting cells of packets from communication network into buffer of attachment of communication adapter
WO1996029804A1 (en) * 1995-03-17 1996-09-26 Telecom Finland Oy Method for rejecting cells at an overloaded node buffer

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EP0566961A2 (de) * 1992-04-23 1993-10-27 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum Überprüfen der Einhaltung vorgegebener Übertragungsbitraten in einer ATM- Vermittlungseinrichtung
EP0566961A3 (en) * 1992-04-23 1993-12-01 Siemens Ag Method and circuit to enforce the preassigned transmission rate in an atm switching equipment
US5402426A (en) * 1992-04-23 1995-03-28 Siemens Aktiengesellschaft Method and arrangement for checking the observance of prescribed transmission bit rates in an ATM switching equipment
US5528763A (en) * 1993-09-14 1996-06-18 International Business Machines Corporation System for admitting cells of packets from communication network into buffer of attachment of communication adapter
EP0711055A1 (de) * 1994-11-03 1996-05-08 Alcatel STR AG Verfahren und Vorrichtung zur Messung charakteristischer Grössen eines Stroms von Datenpaketen fester Länge in einem digitalen Übertragungssystem
US5768259A (en) * 1994-11-03 1998-06-16 Alcatel N.V. Method and device for measuring characteristic magnitudes of a stream of fixed length data packets in a digital transmission system
WO1996029804A1 (en) * 1995-03-17 1996-09-26 Telecom Finland Oy Method for rejecting cells at an overloaded node buffer

Also Published As

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CA2053729C (en) 1998-11-17
CA2053729A1 (en) 1992-04-20
EP0481507A3 (en) 1994-11-17
AU634426B2 (en) 1993-02-18
JPH04156138A (ja) 1992-05-28
AU8598191A (en) 1992-06-04

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