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EP0480819A1 - Columns driving circuit for a display screen, comprising single-ended test means - Google Patents

Columns driving circuit for a display screen, comprising single-ended test means Download PDF

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Publication number
EP0480819A1
EP0480819A1 EP91402683A EP91402683A EP0480819A1 EP 0480819 A1 EP0480819 A1 EP 0480819A1 EP 91402683 A EP91402683 A EP 91402683A EP 91402683 A EP91402683 A EP 91402683A EP 0480819 A1 EP0480819 A1 EP 0480819A1
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EP
European Patent Office
Prior art keywords
test
circuit
output
cebj
sampler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91402683A
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German (de)
French (fr)
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EP0480819B1 (en
Inventor
Patrice Senn
Alan Lelah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sagem SA
Orange SA
Original Assignee
France Telecom SA
Sagem SA
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Publication of EP0480819A1 publication Critical patent/EP0480819A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation

Definitions

  • the present invention relates to a circuit for controlling the columns of a display screen, comprising single output test means. It finds a privileged application in the control of display screens, in particular liquid crystal.
  • a liquid crystal display screen generally takes the form illustrated in FIG. 1.
  • the screen proper ECR consists of rows L and addressing columns C, of a matrix of pixels P, each connected to a TFT transistor whose state is controlled by the line L and the associated column C.
  • Such a screen is controlled by a line control circuit CCL, which sequentially applies an addressing voltage to the lines (for example a few tens of volts) and by a column control circuit CCC, which applies, to all of the columns, voltages reflecting the light intensity of the points to be displayed on the addressed line.
  • the overall image is thus displayed line by line.
  • the column control circuit CCC receives a video signal SV delivered by a video circuit CV.
  • This signal generally consists of three components corresponding to the three primary components of a color image.
  • the circuit CCC comprises 162 elementary column control circuits, arranged in parallel, and 162 outputs connected to the different columns.
  • Each elementary column control circuit also called “driver” column “in the technical literature) includes a sample-and-hold circuit, the function of which is to sample the video signal at a determined instant, corresponding to the column to be controlled, and to maintain this sample on the column for the entire duration of addressing a line ("sample-and-hold" function in Anglo-Saxon terminology).
  • the object of the present invention is to remedy this drawback.
  • the invention proposes a control circuit provided with its own test means, the result of the tests appearing on a single output.
  • the circuit of the invention will have only one test output (and not 162), on which the 162 test signals of the 162 sample-and-hold will appear successively. and this under the control of a single control signal.
  • the circuit represented in FIG. 2 comprises samplers-blockers referenced CEB with an index j (respectively j-1 and j + 1), this index representing the rank of the sampler-blocker in the overall circuit.
  • a sample-and-hold circuit CEBj schematically comprises a transistor Tj controlled by a sampling signal ECHj, a sampling capacitor Cej and an amplifier Aj.
  • the input of the sampler-blocker is connected to a BV video bus.
  • the input of the gate Pj which is intended to receive the test command pulse is also connected to ground by a resistor Rj.
  • this circuit is as follows. When it is desired to test the operation of the sample-and-hold circuits, a test pulse is applied to the test command pad CT. All logic gates (whatever j) therefore receive this signal on one of their inputs. When the gate Pj associated with the sampler-blocker CEBj also receives, on its second input, the sampling signal ECHj specific to the circuit CEBj, the output of this door changes state and commands the closing of the switch Ij. The output of the CEBj sampler-blocker (and of this one only) is then connected to the general LST test line. The output voltage of the sampler-blocker therefore appears on the test output pad ST.
  • FIG. 3 illustrates an embodiment of a circuit for controlling the 162 columns of a display screen, which implements the invention.
  • This circuit CCC includes a shift register R DEC with 162 cells, successively delivering 162 sampling pulses to 162 sample-and-hold circuits CEB1, CEB2, ..., CEB162. These sampler-blockers are connected to three video buses BV1, BV2 and BV3, themselves connected to a video circuit CV.
  • a polarization circuit POL provides the polarizations of the various components, in particular of the amplifiers of the sample and hold units.
  • the circuit includes 162 output pads S1, S2, ..., S162 intended to be connected to the 162 columns CI, C2, ..., C162.
  • the circuit includes a CT test control pad, an output pad ST test line and two general lines which cross the entire circuit in its lower part, namely the LCT test command line and the LST test output line.
  • switch Ij and the gate with two inputs Pj can be technologically produced in a single electronic switch component with two inputs (MOS transistor called "double gate” in the technical literature), while obeying the same operation as that described above.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

These test means comprise a test control line (LCT), a test output line (LST) and, at the output of each sample-and-hold circuit (CEBj), a gate (Pj) and a switch (Ij). The output voltage of the sample-and-hold circuits is transmitted on a test output terminal (ST). …<??>Application to the control of display screens, especially liquid crystal display screens. …<IMAGE>…

Description

La présente invention a pour objet un circuit de commande des colonnes d'un écran d'affichage, comprenant des moyens de test à sortie unique. Elle trouve une application privilégiée dans la commande des écrans d'affichage notamment à cristal liquide.The present invention relates to a circuit for controlling the columns of a display screen, comprising single output test means. It finds a privileged application in the control of display screens, in particular liquid crystal.

Un écran d'affichage à cristal liquide se présente généralement sous la forme illustrée sur la figure 1. L'écran proprement dit ECR est constitué de lignes L et de colonnes C d'adressage, d'une matrice de pixels P, chacun relié à un transistor TFT dont l'état est commandé par la ligne L et la colonne C associées.A liquid crystal display screen generally takes the form illustrated in FIG. 1. The screen proper ECR consists of rows L and addressing columns C, of a matrix of pixels P, each connected to a TFT transistor whose state is controlled by the line L and the associated column C.

Un tel écran est commandé par un circuit de commande de lignes CCL, qui applique séquentiellement aux lignes une tension d'adressage (par exemple quelques dizaines de volts) et par un circuit de commande colonnes CCC, qui applique, à la totalité des colonnes, des tensions reflétant l'intensité lumineuse des points à afficher sur la ligne adressée. L'image globale est ainsi affichée ligne par ligne.Such a screen is controlled by a line control circuit CCL, which sequentially applies an addressing voltage to the lines (for example a few tens of volts) and by a column control circuit CCC, which applies, to all of the columns, voltages reflecting the light intensity of the points to be displayed on the addressed line. The overall image is thus displayed line by line.

Le circuit de commande de colonnes CCC reçoit un signal vidéo SV délivré par un circuit vidéo CV. Ce signal est en général constitué de trois composantes correspondant aux trois composantes primaires d'une image en couleur.The column control circuit CCC receives a video signal SV delivered by a video circuit CV. This signal generally consists of three components corresponding to the three primary components of a color image.

Si l'écran ECR posséde 162 colonnes, le circuit CCC comprend 162 circuits élémentaires de commande de colonne, disposés en parallèle, et 162 sorties reliées aux différentes colonnes. Chaque circuit élémentaire de commande de colonne (appelé encore "driver colonne" dans la littérature technique) comprend un circuit échantillonneur-bloqueur dont la fonction est d'échantillonner le signal vidéo à un instant déterminé, correspondant à la colonne à commander, et de maintenir cet échantillon sur la colonne pendant toute la durée d'adressage d'une ligne (fonction "sample-and-hold" en terminologie anglo-saxonne).If the ECR screen has 162 columns, the circuit CCC comprises 162 elementary column control circuits, arranged in parallel, and 162 outputs connected to the different columns. Each elementary column control circuit (also called "driver" column "in the technical literature) includes a sample-and-hold circuit, the function of which is to sample the video signal at a determined instant, corresponding to the column to be controlled, and to maintain this sample on the column for the entire duration of addressing a line ("sample-and-hold" function in Anglo-Saxon terminology).

Pour vérifier le bon fonctionnement d'un tel circuit de commande de colonnes, au moment de sa fabrication, on effectue des mesures de tensions à l'aide de pointes qui sont mises en contact avec divers points du circuit intégré.To verify the proper functioning of such a column control circuit, at the time of its manufacture, voltage measurements are made using tips which are brought into contact with various points of the integrated circuit.

Cette technique traditionnelle de tests sous pointes présente l'inconvénient d'être d'autant plus difficile à mettre en oeuvre que le nombre de points à tester est grand.This traditional technique of testing under points has the disadvantage of being all the more difficult to implement as the number of points to be tested is large.

La présente invention a pour but de remédier à cet inconvénient. A cette fin, l'invention propose un circuit de commande muni de ses propres moyens de test, le résultat des tests apparaissant sur une sortie unique. Ainsi, s'il y a 162 circuits échantillonneurs-bloqueurs, le circuit de l'invention n'aura qu'une seule sortie de test (et non pas 162), sur laquelle apparaîtront successivement les 162 signaux de test des 162 échantillonneurs-bloqueurs et ceci sous la commande d'un signal de commande unique.The object of the present invention is to remedy this drawback. To this end, the invention proposes a control circuit provided with its own test means, the result of the tests appearing on a single output. Thus, if there are 162 sample-and-hold circuits, the circuit of the invention will have only one test output (and not 162), on which the 162 test signals of the 162 sample-and-hold will appear successively. and this under the control of a single control signal.

A cette fin, le circuit de commande de l'invention comprend :

  • une première ligne générale de sortie de test reliée à un plot de sortie de test,
  • une seconde ligne générale de commande de test reliée à un plot de commande de test,
  • à la sortie de chaque circuit échantillonneur-bloqueur, un circuit de test comprenant un interrupteur disposé entre la sortie de l'échantillonneur-bloqueur et la ligne de sortie de test, une porte logique dont une entrée est reliée à la ligne de commande de test et dont l'autre entrée reçoit le signal d'échantillonnage correspondant au circuit échantillonneur-bloqueur, la sortie de cette porte commandant l'état de l'interrupteur électronique.
To this end, the control circuit of the invention comprises:
  • a first general test output line connected to a test output pad,
  • a second general test control line connected to a test control pad,
  • at the output of each sample and hold circuit, a test circuit comprising a switch arranged between the output of the sampler-blocker and the test output line, a logic gate, one input of which is connected to the test command line and the other input of which receives the signal d 'sampling corresponding to the sample-and-hold circuit, the output of this door controlling the state of the electronic switch.

De toute façon, les caractéristiques et avantages de l'invention apparaîtront mieux à la lumière de la description qui va suivre. Cette description porte sur des exemples de réalisation donnés à titre explicatif et nullement limitatif et elle se réfère à des dessins annexés, sur lesquels :

  • la figure 1, déjà décrite, montre un écran d'affichage à matrice active selon l'art antérieur,
  • la figure 2 montre un circuit de commande conforme à l'invention,
  • la figure 3 illustre un exemple de réalisation d'un circuit de commande de 162 colonnes.
In any case, the characteristics and advantages of the invention will appear better in the light of the description which follows. This description relates to exemplary embodiments given by way of explanation and in no way limiting, and it refers to the attached drawings, in which:
  • FIG. 1, already described, shows an active matrix display screen according to the prior art,
  • FIG. 2 shows a control circuit according to the invention,
  • FIG. 3 illustrates an exemplary embodiment of a control circuit of 162 columns.

Le circuit représenté sur la figure 2 comprend des échantillonneurs-bloqueurs référencés CEB avec un indice j (respectivement j-1 et j+1), cet indice représentant le rang de l'échantillonneur-bloqueur dans le circuit global.The circuit represented in FIG. 2 comprises samplers-blockers referenced CEB with an index j (respectively j-1 and j + 1), this index representing the rank of the sampler-blocker in the overall circuit.

Un circuit échantillonneur-bloqueur CEBj comprend, de manière schématique, un transistor Tj commandé par un signal d'échantillonnage ECHj, un condensateur d'échantillonnage Cej et un amplificateur Aj. L'entrée de l'échantillonneur-bloqueur est reliée à un bus vidéo BV.A sample-and-hold circuit CEBj schematically comprises a transistor Tj controlled by a sampling signal ECHj, a sampling capacitor Cej and an amplifier Aj. The input of the sampler-blocker is connected to a BV video bus.

A la sortie de l'ensemble d'échantillonneur-bloqueur on trouve :

  • une première ligne générale de sortie de test LST reliée à un plot de sortie de test ST,
  • une seconde ligne générale de commande de test LCT reliée à un plot de commande de test CT,
  • à la sortie de chaque circuit échantillonneur-bloqueur CEBj, un circuit de test comprenant un interrupteur électronique Ij disposé entre la sortie de l'échantillonneur-bloqueur CEBj et la ligne générale de sortie de test LST, une porte logique Pj dont une entrée est reliée à la ligne générale de commande de test LCT et dont l'autre entrée reçoit le signal d'échantillonnage ECHj correspondant au circuit échantillonneur-bloqueur CEBj, la sortie de cette porte Pj commandant l'état de l'interrupteur électronique Ij.
At the exit of the sampler-blocker assembly we find:
  • a first general LST test output line connected to a test output pad ST,
  • a second general LCT test control line connected to a CT test control pad,
  • at the output of each sample and hold circuit CEBj, a test circuit comprising an electronic switch Ij disposed between the output of the sample and hold CEBj and the general test output line LST, a logic gate Pj of which an input is connected to the general test command line LCT and the other input of which receives the sampling signal ECHj corresponding to the sample-and-hold circuit CEBj, the output of this gate Pj controlling the state of the electronic switch Ij.

L'entrée de la porte Pj qui est destinée à recevoir l'impulsion de commande de test est par ailleurs reliée à la masse par une résistance Rj.The input of the gate Pj which is intended to receive the test command pulse is also connected to ground by a resistor Rj.

Le fonctionnement de ce circuit est le suivant. Lorsqu'on désire tester le fonctionnement des circuits échantillonneurs-bloqueurs, une impulsion de test est appliquée sur le plot CT de commande de test. Toutes les portes logiques (quel que soit j) reçoivent donc ce signal sur l'une de leurs entrées. Lorsque la porte Pj associée à l'échantillonneur-bloqueur CEBj reçoit en outre, sur sa seconde entrée, le signal d'échantillonnage ECHj propre au circuit CEBj, la sortie de cette porte change d'état et commande la fermeture de l'interrupteur Ij. La sortie de l'échantillonneur-bloqueur CEBj (et de celui-ci seulement) est alors reliée à la ligne générale de test LST. La tension de sortie de l'échantillonneur-bloqueur apparaît donc sur le plot de sortie de test ST.The operation of this circuit is as follows. When it is desired to test the operation of the sample-and-hold circuits, a test pulse is applied to the test command pad CT. All logic gates (whatever j) therefore receive this signal on one of their inputs. When the gate Pj associated with the sampler-blocker CEBj also receives, on its second input, the sampling signal ECHj specific to the circuit CEBj, the output of this door changes state and commands the closing of the switch Ij. The output of the CEBj sampler-blocker (and of this one only) is then connected to the general LST test line. The output voltage of the sampler-blocker therefore appears on the test output pad ST.

Ainsi, lorsque le signal de commande de test est appliqué, à chaque impulsion d'échantillonnage apparaît, sur le plot ST, une tension qui est celle de la sortie de l'échantillonneur-bloqueur commandé par cette impulsion d'échantillonnage. La vérification du bon fonctionnement de l'ensemble du circuit est donc immédiate.Thus, when the test control signal is applied, at each sampling pulse appears, on the pad ST, a voltage which is that of the output of the sampler-blocker controlled by this sampling pulse. Verification of the proper functioning of the entire circuit is therefore immediate.

En l'absence du signal de commande de test appliqué sur le plot CT, toutes les portes Pj sont fermées et les interrupteurs Ij sont tous ouverts. La sortie des échantillonneurs-bloqueurs est donc dirigée uniquement sur les plots de sortie Sj.In the absence of the test command signal applied to the pad CT, all the doors Pj are closed and the switches Ij are all open. The output of the sampler-blockers is therefore directed only to the output pads Sj.

La figure 3 illustre un mode de réalisation d'un circuit de commande des 162 colonnes d'un écran d'affichage, qui met en oeuvre l'invention. Ce circuit CCC comprend un registre à décalage R DEC à 162 cellules, délivrant successivement 162 impulsions d'échantillonnage à 162 circuits échantillonneurs-bloqueurs CEB1, CEB2, ..., CEB162. Ces échantillonneurs-bloqueurs sont reliés à trois bus vidéo BV1, BV2 et BV3, eux-mêmes reliés à un circuit vidéo CV. Un circuit de polarisation POL assure les polarisations des différents composants, notamment des amplificateurs des échantillonneurs-bloqueurs. Le circuit comprend 162 plots de sortie S1, S2, ..., S162 destinés à être reliés aux 162 colonnes CI, C2, ..., C162.FIG. 3 illustrates an embodiment of a circuit for controlling the 162 columns of a display screen, which implements the invention. This circuit CCC includes a shift register R DEC with 162 cells, successively delivering 162 sampling pulses to 162 sample-and-hold circuits CEB1, CEB2, ..., CEB162. These sampler-blockers are connected to three video buses BV1, BV2 and BV3, themselves connected to a video circuit CV. A polarization circuit POL provides the polarizations of the various components, in particular of the amplifiers of the sample and hold units. The circuit includes 162 output pads S1, S2, ..., S162 intended to be connected to the 162 columns CI, C2, ..., C162.

Conformément à l'invention, le circuit comprend un plot de commande de test CT, un plot de sortie de test ST et deux lignes générales qui traversent l'ensemble du circuit dans sa partie inférieure, à savoir la ligne de commande de test LCT et la ligne de sortie de test LST.According to the invention, the circuit includes a CT test control pad, an output pad ST test line and two general lines which cross the entire circuit in its lower part, namely the LCT test command line and the LST test output line.

Il faut noter que dans d'autres types de réalisation l'interrupteur Ij et la porte à deux entrées Pj peuvent être technologiquement réalisés en un seul composant interrupteur électronique à deux entrées (transistor MOS dit "à double gate" dans la littérature technique), tout en obéissant au même fonctionnement que celui décrit précédemment.It should be noted that in other types of embodiment the switch Ij and the gate with two inputs Pj can be technologically produced in a single electronic switch component with two inputs (MOS transistor called "double gate" in the technical literature), while obeying the same operation as that described above.

Claims (2)

Circuit de commande des colonnes (CCC) d'un écran d'affichage (ECR), cet écran comprenant des lignes (L) et des colonnes (C) d'adressage, ce circuit de commande comprenant autant de circuits échantillonneur-bloqueurs (CEBj) que l'écran comprend de colonnes (Cj), chaque échantillonneur étant commandé par un signal d'échantillonnage qui lui est propre (ECHj), ce circuit de commande étant caractérisé par le fait qu'il comprend, en outre, des moyens de test comprenant : - une première ligne générale de sortie de test (LST) reliée à un plot de sortie de test (ST), - une seconde ligne générale de commande de test (LCT) reliée à un plot de commande de test (CT), - à la sortie de chaque circuit échantillonneur-bloqueur (CEBj), un circuit de test comprenant un interrupteur électronique (Ij) disposé entre la sortie de l'échantillonneur-bloqueur (CEBj) et la ligne générale de sortie de test (LST), une porte logique (Pj) dont une entrée est reliée à la ligne générale de commande de test (LCT) et dont l'autre entrée reçoit le signal d'échantillonnage (ECHj) correspondant au circuit échantillonneur-bloqueur (CEBj), la sortie de cette porte (Pj) commandant l'état de l'interrupteur électronique (Ij). Column control circuit (CCC) of a display screen (ECR), this screen comprising rows (L) and addressing columns (C), this control circuit comprising as many sampler-blocker circuits (CEBj ) that the screen includes columns (Cj), each sampler being controlled by its own sampling signal (ECHj), this control circuit being characterized by the fact that it further comprises means for test including: - a first general test output line (LST) connected to a test output pad (ST), - a second general test control line (LCT) connected to a test control pad (CT), - at the output of each sampler-blocker circuit (CEBj), a test circuit comprising an electronic switch (Ij) disposed between the output of the sampler-blocker (CEBj) and the general test output line (LST), a logic gate (Pj), one input of which is connected to the general test command line (LCT) and the other input of which receives the sampling signal (ECHj) corresponding to the sample-and-hold circuit (CEBj), the output of this door (Pj) controlling the state of the electronic switch (Ij). Circuit de commande selon la revendication 1, caractérisé par le fait que, dans chaque circuit de test, l'interrupteur électronique (Ij) et la porte logique (Pj) sont réalisés en un seul composant à deux entrées.Control circuit according to Claim 1, characterized in that, in each test circuit, the electronic switch (Ij) and the logic gate (Pj) are produced in a single component with two inputs.
EP91402683A 1990-10-09 1991-10-08 Columns driving circuit for a display screen, comprising single-ended test means Expired - Lifetime EP0480819B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9012419 1990-10-09
FR9012419A FR2667718B1 (en) 1990-10-09 1990-10-09 CIRCUIT FOR CONTROLLING THE COLUMNS OF A DISPLAY SCREEN COMPRISING SINGLE-OUTPUT TEST MEANS.

Publications (2)

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EP0480819A1 true EP0480819A1 (en) 1992-04-15
EP0480819B1 EP0480819B1 (en) 1995-02-15

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EP91402683A Expired - Lifetime EP0480819B1 (en) 1990-10-09 1991-10-08 Columns driving circuit for a display screen, comprising single-ended test means

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EP (1) EP0480819B1 (en)
JP (1) JPH052377A (en)
DE (1) DE69107394T2 (en)
FR (1) FR2667718B1 (en)

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EP0644523A2 (en) * 1993-08-30 1995-03-22 Sharp Kabushiki Kaisha Data signal line structure in an active matrix liquid crystal display

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US5377030A (en) * 1992-03-30 1994-12-27 Sony Corporation Method for testing active matrix liquid crystal by measuring voltage due to charge in a supplemental capacitor
JP2758103B2 (en) * 1992-04-08 1998-05-28 シャープ株式会社 Active matrix substrate and manufacturing method thereof
JP2672260B2 (en) * 1994-06-07 1997-11-05 トーケン工業株式会社 TFT-LCD inspection method
US5528256A (en) * 1994-08-16 1996-06-18 Vivid Semiconductor, Inc. Power-saving circuit and method for driving liquid crystal display
KR200204617Y1 (en) * 1996-07-12 2000-12-01 윤종용 Apparatus for control of vertical size in lcd monitor
US5754156A (en) * 1996-09-19 1998-05-19 Vivid Semiconductor, Inc. LCD driver IC with pixel inversion operation

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EP0480819B1 (en) 1995-02-15
DE69107394T2 (en) 1995-10-05
FR2667718A1 (en) 1992-04-10
JPH052377A (en) 1993-01-08
US5262720A (en) 1993-11-16
DE69107394D1 (en) 1995-03-23
FR2667718B1 (en) 1992-11-27

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