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EP0410777B1 - Circuit logique et méthode de réarrangement pour une mémoire d'affichage de graphiques vidéos - Google Patents

Circuit logique et méthode de réarrangement pour une mémoire d'affichage de graphiques vidéos Download PDF

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Publication number
EP0410777B1
EP0410777B1 EP19900308245 EP90308245A EP0410777B1 EP 0410777 B1 EP0410777 B1 EP 0410777B1 EP 19900308245 EP19900308245 EP 19900308245 EP 90308245 A EP90308245 A EP 90308245A EP 0410777 B1 EP0410777 B1 EP 0410777B1
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EP
European Patent Office
Prior art keywords
circuit
memory
data
pixel
bits
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19900308245
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German (de)
English (en)
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EP0410777A3 (en
EP0410777A2 (fr
Inventor
Karl M. Guttag
Ian J. Sherlock
Richard D. Simpson
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Texas Instruments Inc
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Texas Instruments Inc
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Priority claimed from US07/387,568 external-priority patent/US5233690A/en
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Publication of EP0410777A3 publication Critical patent/EP0410777A3/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • This invention relates to block-write graphic control data memory write systems and more particularly to an arrangement which allows for the economical reordering of data prior to controlling the block-write function.
  • European Patent Application 0 071 744 discloses a method, carried out by a microprocessor under the control of software, of writing a character to a colour graphics frame buffer.
  • a bit map of each possible character is held in a memory with each bit representing the presence or absence of a pixel at a point in a grid.
  • a row of the bit map is read and a word is formed in which each bit of the row occurs twice consecutively.
  • Another word is formed in which the two bit code for the desired colour for the character is repeated.
  • the two words are then ANDed together and the result is written into the frame buffer at the location for that row. The process is repeated for each row of the character.
  • the International patent application WO88/07235 discloses a bit map graphics system in which the pixels making up a frame are stored in a memory in an order which is suitable for accessing sets of pixels, which, in the displayed frame, make up a block several pixels high and several wide, which is useful for drawing vectors and characters on the display.
  • the special order of the pixels in the memory is achieved by permuting the bits of the (X,Y) addresses of the pixels, where X and Y are the coordinates of the pixels in the displayed frame, and applying the permuted addresses to the memory. For some operations on the pixel data is read out of the memory and permuted into an order suitable for that operation before the operation is performed and is then permuted again and is stored back in the memory.
  • United States Patent No. 4 807 189 discloses a bit map graphics system having a multiplexer connected to select, for the value to be stored in the frame buffer for a selected pixel, between the value on the data bus and the value stored in a colour register. Storing a value in the colour register allows that value to be conveniently written to a number of locations in the frame buffer addressed in turn.
  • Microprocessors intended for graphics applications must be able to move pixel information between memory bit maps as quickly as possible.
  • the transfer may be speeded up by using a block-write feature.
  • a block-write is created by associating a color register with each VRAM, filling the color register with bits to determine the desired color value of selected portions of the VRAM, and then using both the address bits of the VRAM as well as the data bus input to the VRAM to determine the locations within the VRAM where the color represented by the value in the color register will appear. This technique does not burden the data bus with multiple copies of the same pixel value and thus increases the available memory bandwidth, again speeding up data transfers.
  • the block-write can be used to advantage is the fill, which transfers the same pixel value into a defined area of memory.
  • some forms of data expansion are well suited to the application of block-write techniques.
  • the 1's and 0's can represent the presence or absence of a pixel and block-writes can be used to decompress the bit map.
  • this sort of expansion is applied to character fonts which are often stored in compressed form to save memory.
  • the second bit (bit 1) would represent pixel position two and the third bit (bit 2) would represent pixel position three.
  • the bits on the bus in this example would represent the pixel positions one for one, such that bus bit position zero would contain data for the first pixel, while bus position three would contain data for the fourth pixel.
  • the data must be reordered before presentation to the VRAMS.
  • the VRAMS are four bits wide (four planes) with a 32 bit wide data bus.
  • the data bus would have bus positions 0-3 connected to the first VRAM which in turn can control bits 0-3 of the first pixel in a normal write situation.
  • the compressed data in bus bit position 1 (the second position) which should be destined to control the second pixel will end up being communicated to the second input of the first VRAM, which with a normal access be associated with the ninth pixel and not the required second pixel.
  • a bit order rearrangement is necessary when functioning in the block-write mode.
  • a further problem is encountered since the nature of a data swizzle depends on the size of the pixel. Several different swizzles must be made to accommodate a broad range of pixel sizes and VRAM configurations. Thus, it is fair to say that the block-write mode of the video RAMs can only be reasonably used for filling areas in exact multiples of the block size. The nature of the VRAM's block-write function results in a scrambled writing to the pixels within a block unless some data reordering is accomplished.
  • the present invention provides a video graphics circuit comprising:
  • the reordering circuit may be a swizzle circuit having a plurality of inputs and a like plurality of outputs, said swizzle circuit comprising: a like plurality of latches, each controlling one input and one or more outputs; and circuitry for controlling which output to which any input is connected at any instant of time.
  • the reordering circuit may be a multiplex circuit.
  • the reordering circuit may include a memory having a look-up table.
  • the video graphics circuit may include circuitry for shifting bits presented at the first data input terminals before they are applied to the expansion circuit.
  • the memory may be organised in planes and bits of a pixel are stored on respective planes.
  • the memory may comprise one or more VRAMS.
  • the video graphics circuit may include circuitry for determining the number of the VRAMS containing the same pixel information and for controlling said expansion circuitry in accordance with said determination.
  • the expansion circuitry may be arranged for controlling the expansion when said graphics memory is configured with any number of VRAMS controlling said pixels.
  • a graphics processing system may comprise the video graphics circuit.
  • each VRAM has four data input paths (one for each bit of the pixel)
  • compressed bus bit 0 goes to post swizzle position 0, while bus bit 1 goes to post swizzle position 4.
  • compressed bus bit 2 goes to post swizzle position 8 and compressed bus bit 3 goes to post swizzle position 12. This continues for 7 compressed bit positions with compressed bit 7 going to post swizzle position 28. The next compressed bit, bit 8, goes to post swizzle position 1, while compressed bit 9 goes to post-swizzle position 5. This discontinuous sequence continues for the full bus width.
  • the expansion requires a different algorithm, namely the reordering of the ordinate position of the compressed bits by 8 positions. It is recognized that all VRAMs comprising the same pixel are preferably provided the same identical control signal. Thus, for a 2 VRAM pixel (for example, 8 bits) two positions of the bus preferably reflect the same compressed bit value.
  • the memory addressing is adjusted to correspond to the larger amount of data being written to the VRAM when performing a series of block-write accesses (such as filling a large screen area). Effectively, the 4 data bits going to a VRAM are expanded internally by a factor of 4 in the block-write mode. Thus a 32-bit data bus is expanded to 128 bits inside the VRAMs in block-write mode. Therefore, to step efficiently from one addressable location to the next adjacent one requires that the address be incremented/decremented (depending on direction) by 128 (in terms of the bit address) rather than 32 as would be done in regular addressing.
  • the swizzle operation in one example is realized by the proper connection of a multiplexer function for each given bit position.
  • the multiplexing would select between the normal (or straight pass) mode and one or more swizzle functions as needed.
  • FIGURE 1 a brief discussion of the memory structure of a typical graphics memory system is in order before progressing to the actual detailed description of the functioning of the embodiment of this invention. While there are many memory structures and systems which could be used, in the preferred embodiment it is typical to use a structure such as shown in FIGURE 1 which uses eight VRAM memories 200, 201, etc. in an array. Each VRAM memory or unit has a 4 bit data port which can be treated as having planes 11, 12, 13 and 14. The construction of each plane is such that a single data lead is used to write information to that plane. These leads are labeled 0, 1, 2, and 3 for each plane. In a system that uses a 32 bit data bus, such as data bus 20, there would be 8 VRAM memories (two of which are shown in FIGURE 1) each memory having four data leads connected to the data bus.
  • VRAM memory 200 would have its four data leads connected to data bus leads 0, 1, 2, 3, respectively.
  • VRAM memory 201 would have its four leads 0, 1, 2, 3 connected to data bus leads 4, 5, 6, 7, respectively. This continues for the remaining six VRAM's such that the last VRAM has its leads connected to leads 28, 29, 30, 31 of bus 20. The full set of connections is shown in FIGURE 2.
  • the memories are arranged such that the pixel information for the graphics display is stored serially across the planes in the same row. Assuming a four bit per pixel system, then successive pixels are stored in successive VRAMs. In such a situation pixel 0 would be in VRAM 200, and pixel 1 would be in VRAM 201. The pixel storage for pixels 2 through 7 are not shown in FIGURE 1 but are shown in FIGURE 2. The pixel information for pixel 8 then would be stored in VRAM 200, still in row 1 but in column 2 thereof. The reason for this arrangement of pixel information will be more fully appreciated from an understanding of how information is retrieved from the memory.
  • each VRAM plane has a serial register 16 for shifting out information from a row of memory.
  • the outputs from these registers are connected to data out bus 15 in the same manner as the data input leads are connected to the data input bus.
  • data from a row of memory say row 1
  • bit information per pixel is 4 bits. If the pixel information were to be, say 8 bits, then two 4 bit wide VRAMs would have to be used for each pixel. This would change the bit patterns somewhat. This aspect of the invention will be discussed in further detail hereinafter. Also, it should be noted that memory sizes and structures continue to vary and the size and structure shown are only for illustrative purposes and this invention can be used with many different memory configurations and with different pixel sizes.
  • FIGURES 2 through 5 is a one-dimensional representation of what is conceptually a three-dimensional array as shown in FIGURE 1. Therefore, from this point, on the term "row” refers to the set of pixels addressed at any one time from the bus.
  • FIGURE 2 a full eight VRAM memory arrangement is shown with the information for controlling pixels 0-7 contained in the top row of VRAMs 200 through 207, while pixels 8 through 15 are in row 2, and pixels 16 through 23 are in row 3, and pixels 24 through 31 are in row 4. This arrangement continues for each additional row of memory.
  • bits of data are received over data bus 20.
  • the position of the information on the bus determines where the data is to be stored in the VRAMs.
  • a bit on lead 0 of bus 20 goes onto lead 0 of VRAM 200.
  • information in ordinate positions 0-3 of data word 21 can go, via bus 20, to one of many pixels 0, 8, 16, 24, 32, etc.
  • the actual storage location will depend upon other concurrent addressing to the VRAMs, all of which is not shown here but is well known in the art.
  • the method of presentation of data as described above requires 22 bits of data, and a full memory write cycle for each row (8 pixels). In some situations, for example, when a background color is to be painted on a screen, many pixels will have the same information written to them.
  • the block-write method of loading a VRAM has been devised to handle this situation. This operation, which is well known in the art, uses a special register on each VRAM, such as register 210 shown in conjunction with VRAM 200, which contains bits for transfer to selected pixel locations within memory. These bits are loaded prior to the start of any block-write operation.
  • each bit controls the transfer of the special register bits to a particular memory row in that VRAM.
  • VRAM 200 assume it is desired to load pixels 0, 8 and 24 with the bits from register 210 while leaving pixel 16 unchanged. In this situation, leads 0, 1, 3 would have logical 1's thereon while lead 2 would contain a logical 0. This same situation would prevail for the entire 32 bit bus in that the ordinate position of the bits would determine whether or not information is to be transferred into a corresponding pixel in a corresponding VRAM memory row.
  • This, it will be appreciated, is different from the normal loading of data where the data itself comes from the data bus.
  • the data comes from the special registers associated with each VRAM and the bits on the data bus merely give on-off or load-not load control depending upon their position on the various leads of the bus.
  • the data word that controls this operation is then said to be in compressed format such that the ordinate position of each bit being either a 1 or 0 controls a function. Also it should be noted that 1 and 0 representing on and off, respectively, is merely illustrative and the reverse may be true also.
  • compressed data word 39 has ordinate positions 0-31 which must be presented to the VRAMs to control various pixels in accordance with the ordinate position of the data in the word.
  • pixel 0 is to be controlled by compressed data bit 0
  • pixel 1 is to be controlled by compressed data bit 1.
  • compressed data bit 31 should then control pixel 31. This is easier said than done.
  • Pixel 0 is easy since it is controlled by lead 0 of VRAM 200 which is connected to compressed bit 0.
  • the bit in position 1 of compressed data word 39 begins the problem.
  • this non-compressed bit is connected to pin 1 of VRAM 200.
  • the bit in compressed data ordinate position 1 is used to control the writing of information from the special register into pixel 1.
  • Pixel 1 is controlled, in turn, by a 1 or 0 on lead 1 of VRAM 201. This lead, in turn, is connected to lead 4 of bus 20.
  • a comparison of FIGURES 2 and 3 will show that in one situation bit position 1 of the input data word goes to lead 1 of bus 20 while in the other situation it goes to lead 4.
  • a reordering of bits is necessary when compressed words are used to control data transfer in the block-write mode.
  • swizzle circuit 32 which is interposed between the compressed data input and the actual data bus. Swizzle circuit 32 is controlled by the processor to allow data to flow straight through, as would be the situation for FIGURE 2, or to reorder the leads in a certain pattern as is required for FIGURE 3. This arrangement does not require processor time to rearrange information, but rather establishes a pattern based on the physical structure of the memory bus arrangement and calls upon that structure whenever a block-write operation is invoked.
  • the swizzle circuit could be hard wired or could be software controlled within or outside of the processor.
  • FIGURE 9 shows a schematic diagram of how a simple multiplexer would achieve the required swizzle for output bits 0, 1, and 2 for supporting the 4 plane and 8 plane modes of the preferred embodiment.
  • the multiplexer function simply passes the corresponding bit position from input to output (i.e. 0 to 0, 1 to 1, and 2 to 2).
  • the input to output connections are made as outlined in FIGURE 4 (0 to 0, 8 to 1, 16 to 2).
  • the connections are made as outlined in FIGURE 5 (0 to 0, 0 to 4, 8 to 2).
  • FIGURE 9 shows a schematic diagram of how a simple multiplexer would achieve the required swizzle for output bits 0, 1, and 2 for supporting the 4 plane and 8 plane modes of the preferred embodiment.
  • the multiplexer function simply passes the corresponding bit position from input to output (i.e. 0 to 0, 1 to 1, and 2 to 2).
  • the input to output connections are made as outlined in FIGURE 4 (0 to 0, 8 to 1, 16 to 2).
  • the connections are made as outlined in FIGURE 5 (0
  • the swizzle function is performed by multiplexer hardware function, other means such as a software based table lookup method could be used to perform the swizzle.
  • FIGURE 5 it is seen that expanding the compressed word by duplicating each bit corresponding to the number of VRAMs used per pixel will result in the ability to use the same swizzle circuit for different memory/pixel configurations.
  • This solution, as performed by duplicating/expansion circuit 52 has the effect of also activating both VRAMs of a given pixel, since the color information must be provided to all pixel bits even when these bits are positioned within two VRAMs.
  • the essence of the operation is the fact that the duplication and expansion occurs prior to the swizzle operation, thereby allowing the same swizzle configuration for both operations.
  • the same configuration would be used for any given system and thus only one determination of duplication/expansion need be made.
  • situations may arise where more than one VRAM system configuration is controlled by the same processor, and thus dynamic control can be required. This can easily be achieved by arranging duplicate/expansion circuit 52 to function under control of the system processor on a case by case basis.
  • Duplicate/expansion circuit 52 can be any type of register circuit or processor that can reorder and pad numbers. This can be operated by microcode under control of the main processor or by a special processor or can be performed by a host processor if desired. The function performed by circuit 52 is mathmatical in nature and thus one skilled in the art can easily devise many arrangements to perform the desired function.
  • Circuit 52 can be system adaptable to change the duplicating and expansion function on a dynamic basis in response to received data or in response to a flag in a register to allow for changing pixel/memory configurations.
  • a pixel size of 16 bits and a VRAM of the same size as shown in FIGURE 1 namely four bits
  • four VRAMS would be used for each pixel and thus the expansion would be by four bits.
  • expanded word 61 would have the data from compressed bit ordinate position 0 expanded into ordinate positions 0, 1, 2, 3 of the expanded word.
  • the data from compressed ordinate position 1 would be expanded into ordinate bit positions 4, 5, 6, 7, and so forth.
  • the compressed word is provided in a register such that it can be rotated through all 32 bits for any given memory clock cycle regardless of how many bits are expanded. This allows for continuous system operation without regard to pixel size. This also allows for total flexibility of memory storage to allow for starting and stopping at any given pixel boundary.
  • FIGURE 7 shows the input to output correspondence of swizzle circuit 32 when the swizzle circuit is in the swizzle modes It should be realized that each input has two possible outputs: the swizzle output, as shown, and the straight-through output, which is not shown. Of course, the straight-through output has input 0 connected to output 0, with input 1 connected to output 1, input 2 connected to output 2, and so forth. A switching circuit is used to switch between the straight-through arrangement of the swizzle circuit and the swizzle mode of the swizzle circuit.
  • FIGURE 8 shows one embodiment of the swizzle circuit 32 where registers 0 and 1 are shown for positions 0 and 1.
  • the input bus has 32 leads, and the output bus also has 32 leads. Between these leads are a number of latches, two of which, 800 and 801, are shown. Each latch has a single input connected to an individual input bus lead and two outputs connected to the straight-through correspondence and to the swizzle correspondence in accordance with FIGURE 7.
  • the latches load in a straightforward manner from information on the input bus upon the signal provided on the load lead. For the straight-through operation, a signal is provided on the REGULAR lead, and the outputs from the latches are clocked straight through the swizzle circuit with straight-through correspondence, as noted above.
  • the SWIZZLE lead is pulsed, and this serves to switch the outputs.
  • latch 801 in the straight-through mode, latch 801 is connected to lead 1 of the output bus.
  • another output from latch 1 is connected to lead 4 of the output bus.
  • All of the latches of swizzle circuit 32 are wired with this correspondence such that the swizzle output lead of each latch is connected as shown in FIGURE 7 to the output bus lead.
  • the circuit shown in FIGURE 8 can be expanded to cover the multiple swizzles required for swizzle circuit 42. In this situation, an extra controlled output lead would extend from each latch to a different output. In this mode a second swizzle control signal would extend to control multiple outputs from each latch, the number of multiples being a function of the number of VRAMs containing the same pixel information.
  • circuitry including the swizzle circuit and processor, could be integrated into a single chip.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Controls And Circuits For Display Device (AREA)

Claims (10)

  1. Circuit graphique vidéo comprenant :
    une première pluralité de bornes d'entrée de données ;
    une mémoire (200,201,207) pour stocker des données représentatives d'éléments d'image d'une image, chaque élément d'image étant représenté par une pluralité de bits et la mémoire ayant une seconde pluralité de bornes d'entrée de données ;
    un circuit de reordonnancement (32) pour relier la première pluralité de bornes d'entrée de données à la seconde pluralité de bornes d'entrée de données dans différents ordres suivant que le circuit graphique vidéo est commandé soit
    dans un premier mode dans lequel des données présentes à la première pluralité de bornes d'entrée de données sont stockées en tant que valeurs d'éléments d'image dans ladite mémoire, ou
    dans un second mode d'écriture par bloc dans lequel des bits uniques des données présentés à la première pluralité de bornes d'entrée de données déterminent si une valeur tenue dans un registre est appliquée auxdits éléments d'image respectifs dans la mémoire ; et
    un circuit d'expansion (52) relié entre la première pluralité de bornes d'entrée de données et le circuit de réordonnancement pour répliquer des bits présents aux premières bornes d'entrée de données et appliquer les bits répliqués en parallèle au circuit de réordonnancement.
  2. Circuit graphique vidéo selon la revendication 1, dans lequel le circuit de réordonnancement est un circuit d'aiguillage ayant une pluralité d'entrées et une pluralité analogue de sorties, ledit circuit d'aiguillage comprenant :
    une pluralité analogue de circuits à verrouillage, chacun commandant une entrée et une ou plusieurs sorties ; et
    un circuit pour commander quelle sortie est connectée à quelle entrée à tout instant.
  3. Circuit graphique vidéo selon la revendication 1, dans lequel le circuit de réordonnancement est un circuit multiplex.
  4. Circuit graphique vidéo selon la revendication 1, dans lequel le circuit de réordonnancement inclut une mémoire ayant une table à consulter.
  5. Circuit graphique vidéo selon l'une quelconque des revendications 1 à 4, incluant un circuit pour décaler des bits présents aux premières bornes d'entrée de données avant qu'ils soient appliqués au circuit d'expansion.
  6. Circuit graphique vidéo selon l'une quelconque des revendications précédentes, dans lequel la mémoire est organisée en plans et des bits d'une donnée d'image sont stockés sur des plans respectifs.
  7. Circuit graphique vidéo selon la revendication 6, dans lequel la mémoire comprend une ou plusieurs VRAM.
  8. Circuit graphique vidéo selon la revendication 7, comprenant en outre un circuit pour déterminer le nombre de VRAM contenant la même information d'élément d'image et pour commander ledit circuit d'expansion en fonction de ladite détermination.
  9. Circuit graphique vidéo selon la revendication 7, dans lequel ledit circuit d'expansion est agencé pour commander l'expansion lorsque ladite mémoire graphique est configurée avec tout nombre de VRAM commandant lesdits éléments d'image.
  10. Système de traitement graphique comprenant un circuit graphique vidéo selon l'une quelconque des revendications 1 à 9.
EP19900308245 1989-07-28 1990-07-27 Circuit logique et méthode de réarrangement pour une mémoire d'affichage de graphiques vidéos Expired - Lifetime EP0410777B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US38756789A 1989-07-28 1989-07-28
US387568 1989-07-28
US07/387,568 US5233690A (en) 1989-07-28 1989-07-28 Video graphics display memory swizzle logic and expansion circuit and method
US387567 1989-07-28

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EP0410777A2 EP0410777A2 (fr) 1991-01-30
EP0410777A3 EP0410777A3 (en) 1992-10-28
EP0410777B1 true EP0410777B1 (fr) 1996-11-06

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JP (1) JP3085693B2 (fr)
DE (1) DE69029065T2 (fr)

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US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations
US8769248B2 (en) 1995-08-16 2014-07-01 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

Also Published As

Publication number Publication date
EP0410777A3 (en) 1992-10-28
DE69029065T2 (de) 1997-03-06
DE69029065D1 (de) 1996-12-12
EP0410777A2 (fr) 1991-01-30
JP3085693B2 (ja) 2000-09-11
JPH03156576A (ja) 1991-07-04

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