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EP0376679A2 - Bildkodiervorrichtung und Bildkodierverfahren - Google Patents

Bildkodiervorrichtung und Bildkodierverfahren Download PDF

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Publication number
EP0376679A2
EP0376679A2 EP89313590A EP89313590A EP0376679A2 EP 0376679 A2 EP0376679 A2 EP 0376679A2 EP 89313590 A EP89313590 A EP 89313590A EP 89313590 A EP89313590 A EP 89313590A EP 0376679 A2 EP0376679 A2 EP 0376679A2
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EP
European Patent Office
Prior art keywords
image
encoding
pixel
forming
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89313590A
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English (en)
French (fr)
Other versions
EP0376679A3 (de
EP0376679B1 (de
Inventor
Akihiro Katayama
Mitsuru Maeda
Yasuji Hirabayashi
Tadashi Yoshida
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Canon Inc
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Canon Inc
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Publication date
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Publication of EP0376679A2 publication Critical patent/EP0376679A2/de
Publication of EP0376679A3 publication Critical patent/EP0376679A3/de
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Publication of EP0376679B1 publication Critical patent/EP0376679B1/de
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction
    • H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
    • H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
    • H04N1/417—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information using predictive or differential encoding
    • H04N1/4172—Progressive encoding, i.e. by decomposition into high and low resolution components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • H04N1/40068—Modification of image resolution, i.e. determining the values of picture elements at new relative positions

Definitions

  • the present invention relates to an image encoding apparatus and, more particularly, to a binary image hierarchical encoding apparatus in a still image communication apparatus.
  • a facsimile apparatus as a typical still image communication apparatus adopts a system for sequentially scanning, encoding and transmitting an image.
  • This system requires a long transmission time since all image data must be transmitted, and is difficult to be applied to image communication services such as an image data base service, videotex, and the like, which require quick judgment of an image.
  • image communication services such as an image data base service, videotex, and the like, which require quick judgment of an image.
  • a system different from that employed in the facsimile apparatus is proposed ("Sequential Reproduction/Encoding System of Facsimile Signal Suitable for Conversational Image Communication", Endo and Yamasaki, Shingakuron (B), J67-B.12, pp. 1462 - 1469 (1984)).
  • this system when one image is transmitted, rough image information is transmitted first, and additional information is transmitted later, thereby generating detailed image data.
  • the rough image information to be transmitted first is generated by omitting pixels at specific intervals from an original image, valid image information cannot often be transmitted at an initial stage depending on the type of image. For example, a straight line having a width of one pixel may be deleted.
  • the present invention has been made in consideration of the above situation, and has as its object to provide an image encoding apparatus which can efficiently encode image information without omitting the image information.
  • Fig. 1 shows an embodiment of an encoding unit of the present invention.
  • Original image data I1 is stored in a frame memory 1.
  • the original image data read out from the frame memory 1 is reduced by a reduction circuit 2, and is output as a signal 101.
  • the original image data read out from the frame memory 1 is input to a fine line detection circuit 3.
  • the fine line detection circuit 3 detects a fine line, and outputs selection signals S1 and S2 in accordance with the detection result.
  • the signals S1 and S2 are input to a selector 4.
  • the selector 4 outputs "1", "0", or the signal 101 as a signal 103.
  • the signal 103 is stored in a frame memory 5.
  • the signal stored in the frame memory 5 corresponds to 1/2 original image data.
  • the fine line detection circuit 3 is arranged in parallel with the reduction circuit 2, and reduced image data is formed based on the output from the fine line detection circuit 3. Thus, a fine line which would be lost if only the reduction circuit 2 is arranged can be preserved.
  • the 1/2 image data read out from the frame memory 5 is reduced to a 1/4 original image by a reduction circuit 6, a fine line detection circuit 7, and a selector 8, and is stored in a frame memory 9 as 1/4 image data.
  • Reference pixel determination means (or circuits) 10, 12, and 14 respectively detect sizes (the numbers of pixels) of image data stored in the frame memories 9, 5, and 1, and set the optimal numbers of pixels and optimal reference pixel positions in encoding.
  • An encoder 11 encodes the 1/4 image data stored in the frame memory 9 using the reference pixel set by the reference pixel determination means 10, and outputs the encoded data as a first-stage signal 107.
  • encoders 13 and 15 encode the 1/2 image data and original image data stored in the frame memories 5 and 1 using the reference pixels set by the reference pixel determination means 12 and 14, and output encoded data as second- and third-stage signals 108 and 109, respectively.
  • the first- to third-stage image data are encoded and transmitted in turn in the order starting from image data having a lower resolution, so that a receiver side can quickly identify the entire image. If the receiver side does not need the data, it can stop the following transmission. Thus, an efficient image communication service can be provided.
  • Fig. 2 is a block diagram of the reduction circuits 2 and 6.
  • Each reduction circuit comprises a low-pass filter 16, a comparator 17, and a sub-sampling circuit 18.
  • a parameter C for adjusting a degree of smoothness is input to the low-pass filter 16.
  • a threshold value T is input to the comparator 17. These values are determined based on required image quality and encoding efficiency.
  • a signal output from the low-pass filter 16 is binarized by the comparator 17 based on the threshold value T. The binarized signal is thinned by the sub-sampling circuit 18 to 1/2 in the vertical and horizontal directions.
  • Fig. 3 shows filter coefficients of the low-pass filter 16 having a 3 x 3 pixel size.
  • a weighting coefficient of the central pixel is represented by C, a weighting coefficient of 1 is assigned to four pixels closest to the central pixel, and a weighting coefficient of 1 is assigned to the next closest pixels.
  • the density W and the threshold value T have the following correspondences:
  • Fig. 4 is a block diagram of the low-pass filter 16.
  • An input signal is held in latches 20a, 20b, and 20c to be delayed by one pixel clock.
  • An input signal delayed by one line is held in each of line memories 19-a and 19-b.
  • signals whose pixel positions correspond to the latches 20a, 20b, and 20c can be obtained from latches 20d, 20e, and 20f or latches 20g, 20h, and 20i.
  • the output signals from the latches 20a, 20c, 20g, and 20i are added by an adder 21a to calculate a total sum.
  • the total sum output from the adder 21a is multiplied with a constant (x1) by a multiplier 22a.
  • the output signals from the latches 20b, 20d, 20f, and 20h are added by an adder 21b to calculate a total sum.
  • the total sum from the adder 21b is multiplied with a constant (x2) by a multiplier 22b.
  • the output signal from the latch 20e i.e, data of the central pixel
  • xC constant
  • the C value can be externally set.
  • the output signals from the multipliers 22a, 22b, and 22c are added by an adder 23 to calculate a total sum W.
  • the total sum W is then output.
  • the output signal from the adder 23 is compared with the threshold value T by the comparator 17 (Fig. 2). When the total sum W is larger than the threshold value T, a signal "1" is obtained; otherwise, a signal "0" is obtained.
  • the threshold value T can also be externally set.
  • Fig. 5 is a view for explaining an operation of the sub-sampling circuit 18.
  • Hatched pixel data (Fig. 5) are sampled at every other timings respectively in the main scan and sub scan directions, thereby forming a sub-sampling image of a 1/2 size (1/4 in terms of an area). This operation can be easily realized by adjusting latch timings of image data.
  • the fine line detection circuits 3 and 7 will be described below.
  • a fine line or the like of a one-pixel width may be lost.
  • Figs. 7A and 8A show examples of such images.
  • the low-pass filter output (Fig. 3) becomes 4, and this black line disappears unless the threshold value T of the comparator (Fig. 2) is set to be 4 or less.
  • a white line (black background) shown in Fig. 8A disappears unless the threshold value T is set to be (C+8) or more.
  • an edge of an image can be detected by a linear differential filter.
  • a linear differential filter For example, in the case of the image shown in Fig. 7A, an edge changing from black to white can be detected by a linear differential filter of 3 x 3 pixels shown in Fig. 7B. More specifically, only when an edge changing from black to white is present, a power of a filtering result is increased.
  • the filtering result in Fig. 7A is 3.
  • an edge changing from white to black can be detected by a linear differential filter shown in Fig. 8B. In this case, a power of a filtering result is also 3.
  • Fig. 6 is a block diagram of the fine line detection circuits 3 and 7.
  • Fig. 6 an arithmetic operation for fine line detection using the linear differential filter is simplified.
  • the circuit shown in Fig. 6 includes line memories 24a, 24b, and 24c for respectively holding input pixels of one line, latches 25a to 25k for temporarily storing reference pixels used in an arithmetic operation corresponding to linear differentiation, a latch 60 for adjusting a timing, AND gates 61a to 61l, inverters 62a to 62n, and OR gates 63a and 63b.
  • An input signal is held in the latches 25i, 25j, and 25k to be delayed by one pixel clock.
  • the line memories 24a, 24b, and 24c respectively hold input signals delayed by one line.
  • Signals whose pixel positions correspond to the latches 25i, 25j, and 25k can be obtained from the latches 25f, 25g, and 25h, and the latches 25c, 25d, and 25e.
  • pixel data (central pixel) held in the latch 25g corresponds to data held in the latch 20e shown in Fig. 4.
  • 3 x 3 pixels stored in the latches 25k, 25j, 25i, 25h, 25g, 25f, 25e, 25d, and 25c respectively correspond to 3 x 3 pixel latches 20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h, and 20i in Fig. 4.
  • the latch 25a latches a pixel two lines before the pixel of interest through the line memory 24c and the latch 60.
  • the latch 25b latches a pixel two pixels before the pixel of interest.
  • a linear differential value can be calculated based on the 3 x 3 pixels latched in the latches 25c to 25k in Fig. 6.
  • the following logical formula is taken into consideration. If data held in the latches 25a to 25k in Fig. 6 are represented by a to k , reversed data of the data a to k are represented by a to k , a logical sum is represented by "+”, and a logical product is represented by " ⁇ ”, the following logical formula can be considered in place of the linear differential filter shown in Fig. 7B.
  • the black line having a one-pixel width shown in Fig. 7A corresponds to c , f , and i .
  • V B (c ⁇ f ⁇ i) ⁇ ( e ⁇ h ⁇ k )
  • V B 1
  • an edge changing from black to white can be detected.
  • this detection is not preferable in reduction for reducing two pixels to one pixel.
  • V′ B (c ⁇ f ⁇ i) ⁇ ( e ⁇ h ⁇ k ) ⁇ b
  • V′ W 1.
  • V′ B and V′ W are used for detecting vertical black and white lines each having a one-pixel width.
  • the line memories and latches constituting the low-pass filter are different from those constituting the fine line detection circuits. Some of the line memories and latches of the fine line detection circuit can be commonly used as those for the low-pass filter.
  • the encoders 11, 13, and 15 perform an encoding operation in accordance with arithmetic codes.
  • a value of a pixel of interest is predicted from surrounding pixels.
  • a symbol of the predicted pixel is given by a major symbol, symbols of other pixels are given by minor symbols, and a probability of generation of minor symbols is represented by P.
  • encoding is performed.
  • C(S) and C(S′) + A(S′0) are compared.
  • Fig. 9 is a block diagram of a circuit for predicting a pixel of interest.
  • a frame memory 26 stores image data to be encoded.
  • a frame memory 27 stores image data obtained by 1/2 sub-sampling the image (image sent in the immediately preceding stage) stored in the frame memory 26.
  • the memories 26 and 27 respectively comprise two-­dimensional memories. If a clock of an x address is represented by ⁇ 1 and a clock of a y address is represented by ⁇ 2, the clocks ⁇ 1 and ⁇ 2 are supplied to the frame memory A, and clocks 1/2 ⁇ 1 and 1/2 ⁇ 2 each having a 1/2 frequency are supplied to the frame memory B. Thus, one pixel in the frame memory B corresponds to 2 x 2, i.e,. four pixels in the frame memory A.
  • Data from the frame memories 26 and 27 become one-line delayed data in line memories 28 and 29, and these data are then input to latches 30a to 30c and 31a and 31b.
  • Each latch latches data delayed by one pixel. If the outputs from these latches are caused to correspond to pixel positions shown in Fig. 10, a pixel of interest (*) corresponds to the output from the latch 30d; a pixel No. 1 in Fig. 10, the latch 30e; No. 2, the latch 30b; No. 3, 30a; and No. 4, the latch 30c.
  • a pixel No. 5 corresponds to the output from the latch 31b; No. 6, the latch 31a; No. 7, the latch 31d; No. 8, the latch 31c; and No. 9, the latch 31e.
  • the pixel No. 5 in Fig. 11 is one including a pixel of interest.
  • a 2-bit signal for identifying the position of the pixel of interest in the pixel No. 5 (four states of upper left, upper right, lower left, and lower right) is generated by a counter 32 based on the clocks ⁇ 1 and ⁇ 2.
  • AND gates 33a to 33k calculate logical products between signals 201 to 211 set by a controller (not shown) and outputs from the latches 30a to 30c, 30e, and 31a to 31e, and the counter, respectively, thereby outputting a prediction signal 300 of the pixel of interest. The operation of this portion will be described in detail below.
  • a pixel of interest is predicted from states of surrounding pixels, and a skew value is updated while calculating a "hit" probability of prediction. Therefore, in order to reflect the statistic nature of a symbol string to be encoded in a skew value, a considerable number of symbols for grasping the statistic nature are required in each state. For example, if the total number of symbols is 65,536, when the number of states is 211, an average number of symbols assigned to each state is 32, and it is difficult to grasp the statistic nature of the symbol string in each state.
  • a controller (not shown) controls the number of predicted states in accordance with the number of symbols to be encoded. More specifically, in hierarchical encoding, since an image is reduced in every stage, the number of symbols to be encoded is smallest in the first stage, and it is increased toward the higher stages like the second stage, the third stage,.... When the number of symbols is small, the signals 203, 209, and 211 of the signals 201 to 211 are set to be "1", and the remaining signals are set to be "0", so that 3 bits (8 states) can be used as the number of states. As the number of symbols is increased, the number of "1"s set in the signals 201 to 211 is increased, thus increasing the number of states.
  • Fig. 18 shows an example of values of the signals 201 to 211 in this embodiment. This is merely an example, and the way of setting the states and signals to be set are not limited to this.
  • Fig. 12 is a block diagram of a circuit for dynamically changing the skew value Q and a minor symbol lps.
  • a status signal G300 and a pixel of interest D301 are respectively input to a status counter 40 and a minor symbol counter 41.
  • internal counters corresponding in number to the states are prepared to allow a count operation in units of states, and are selected by a status signal G.
  • the status counter 40 counts the number of generation times of a certain state for each state. When the count value exceeds a setup value S302, the counter 40 outputs an updating signal 303.
  • An LUT 42 prestores Q G 305 as the next encoding parameter, a signal 306 for reversing mps (major symbols) so far, and data called a zero count (CT) 307 for generation of lc minor symbols.
  • CT zero count
  • Fig. 19 shows an example of the content of the LUT 42.
  • CT 0 is set, and new Q G and the next CT value are obtained based on the lc value.
  • N[x] is a closest integer value.
  • Equation (1) an exponential part when the generation probability of minor symbols generated when S states continue (CT+1) times is approximated by a power of 2 is given by Q G .
  • a latch 43 latches the current skew value Q G 305, the mps reversal signal 306, and CT 307, and latches the output from the LUT 42 in response to the updating signal 303 to be updated to a new state.
  • the LUT 42 receives the count signal lc of minor symbols, and the previous CT value 307, and outputs the skew value Q G , the mps reversal signal, and CT which are updated according to Fig. 19.
  • An mps value latch 44 latches a major symbol used in encoding so far, and this state is updated by the mps reversal signal.
  • An mps/ lps signal as an output of the latch 44 is supplied to the minor symbol counter.
  • Encoding is performed based on the determined skew value Q G and mps/ lps .
  • Fig. 13 is a block diagram of an arithmetic code encoder. If a skew value is assumed to be the skew value Q G 305 from the latch 43 shown in Fig. 12, the skew value Q G 305 and the mps/ lps signal 308 are input, so that an arithmetic operation given by equation (1) of pixel of interest data D is performed by an encoder, thus obtaining encoding data 401.
  • Fig. 14 is a block diagram of a decoder.
  • the same prediction circuit (Fig. 9) and dynamic adaptive circuit as in the encoding unit are prepared in the decoding side.
  • a decoder 46 performs a decoding arithmetic operation using a skew value Q D 321 of a decoder side, and a minor symbol LPS D 322 and receiving data 323 from an LUT, thus obtaining decoding data 402.
  • Fig. 15 shows an embodiment of a decoding unit.
  • the first-stage signal 107 is decoded by a decoder 47, and is stored in a frame memory 50. This signal is converted to high-resolution data by x4 interpolation processing of an interpolation device 53. The high-resolution data is stored in a video memory 56 after a selector 55 is switched by a controller 59.
  • the video memory 56 comprises a 2-port memory. Therefore, an image obtained at a receiver side is always displayed on a monitor 57.
  • the second-stage signal 108 is decoded by a decoder 48 with reference to the data stored in the frame memory 50, and is stored in a frame memory 51. This data is subjected to x2 interpolation processing by an interpolation device 54, and is stored in the video memory 56 upon switching of the selector 55.
  • the third-stage signal 109 is similarly decoded, it is displayed on the monitor 57.
  • a signal from a frame memory 52 as a decoded third-stage image signal is output to a printer 58 to obtain a hard copy.
  • the first embodiment employs a system for adjusting a degree of smoothness in accordance with a weighting coefficient of the central value of a 3 x 3 coefficient matrix of the low-pass filter.
  • lc/S is obtained from the number of minor symbols lc among S pixels to determine a new skew value Q G from Fig. 20.
  • Q G is determined using the updated Q G and lc/S.
  • a value Q G ′ in updating is calculated by, e.g., the following equation, and is stored in a table:
  • Fig. 17 shows an embodiment in this case, and a Q G signal 305 is input to an LUT 42 to determine Q G to be updated.
  • the available number of states is controlled in each stage.
  • the number of states can be controlled in accordance with an image size to be encoded. For example, when an image size of a third stage is 1024 x 1024 pixels, the number of states can be controlled to 27 states; when it is 3072 x 4096 pixels, it can be controlled to 211 states.
  • the stages can be further segmented, and the reference pixel position and the number of reference pixels can be changed in units of image sizes.
  • a reference pixel position suitable therefore is set to perform encoding.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Editing Of Facsimile Originals (AREA)
  • Image Processing (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
EP89313590A 1988-12-28 1989-12-27 Bildkodiervorrichtung und Bildkodierverfahren Expired - Lifetime EP0376679B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63332637A JPH02177766A (ja) 1988-12-28 1988-12-28 ２値画像の階層的符号化方式
JP332637/88 1988-12-28

Publications (3)

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EP0376679A2 true EP0376679A2 (de) 1990-07-04
EP0376679A3 EP0376679A3 (de) 1992-01-22
EP0376679B1 EP0376679B1 (de) 1996-05-01

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EP89313590A Expired - Lifetime EP0376679B1 (de) 1988-12-28 1989-12-27 Bildkodiervorrichtung und Bildkodierverfahren

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EP (1) EP0376679B1 (de)
JP (1) JPH02177766A (de)
DE (1) DE68926386T2 (de)

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JPH07322252A (ja) 1994-05-23 1995-12-08 Canon Inc 画像符号化装置
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DE19958553A1 (de) 1999-12-04 2001-06-07 Luratech Ges Fuer Luft Und Rau Verfahren zur Kompression von gescannten Farb- und/oder Graustufendokumenten
ATE509330T1 (de) * 1999-12-04 2011-05-15 Luratech Imaging Gmbh Verfahren zur kompression von gescannten farb- und/oder graustufendokumenten
US6968088B2 (en) * 2000-03-28 2005-11-22 Canon Kabushiki Kaisha Modification of detected quantization step size from the encoded bitstream based on a region of interest (ROI) bitmask
US6853930B2 (en) * 2001-02-27 2005-02-08 Hitachi, Ltd. System for aiding the preparation of operation and maintenance plans for a power generation installation
JP2003304404A (ja) * 2002-04-09 2003-10-24 Canon Inc 画像符号化装置
JP4612797B2 (ja) * 2004-03-11 2011-01-12 キヤノン株式会社 符号化装置、符号化方法
JP2005295505A (ja) * 2004-03-12 2005-10-20 Canon Inc 動画像符号化装置及び動画像復号装置及びそれらの制御方法、並びに、コンピュータプログラム及びコンピュータ可読記憶媒体
JP4702928B2 (ja) * 2004-03-12 2011-06-15 キヤノン株式会社 動画像符号化装置及び復号装置及びその制御方法、並びにコンピュータプログラム及びコンピュータ可読記憶媒体
JP3915795B2 (ja) 2004-03-29 2007-05-16 コニカミノルタビジネステクノロジーズ株式会社 画像処理装置および画像処理プログラム
JP4771541B2 (ja) * 2006-08-08 2011-09-14 キヤノン株式会社 画像符号化装置及び方法、並びに、コンピュータプログラム及びコンピュータ可読記憶媒体

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DE68926386D1 (de) 1996-06-05
US5371606A (en) 1994-12-06

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