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EP0364565B1 - Synchroner logischer schaltkreis mit übertragungssignalsteuerung - Google Patents

Synchroner logischer schaltkreis mit übertragungssignalsteuerung Download PDF

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Publication number
EP0364565B1
EP0364565B1 EP89904859A EP89904859A EP0364565B1 EP 0364565 B1 EP0364565 B1 EP 0364565B1 EP 89904859 A EP89904859 A EP 89904859A EP 89904859 A EP89904859 A EP 89904859A EP 0364565 B1 EP0364565 B1 EP 0364565B1
Authority
EP
European Patent Office
Prior art keywords
logic
signal
flipflop
counting
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89904859A
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English (en)
French (fr)
Other versions
EP0364565A1 (de
Inventor
Hendrik Adrianus Vink
Robertus Wilhelmus Cornelis Dekker
Aloysius Petrus Thijssen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP0364565A1 publication Critical patent/EP0364565A1/de
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Publication of EP0364565B1 publication Critical patent/EP0364565B1/de
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
    • H03K23/588—Combination of a synchronous and an asynchronous counter

Definitions

  • the invention relates to a synchronous logic circuit being formed of a series connection of a plurality of logic stages Each logic stage receives a clock signal.
  • each next one of the logic stages comprises a first logic element for receiving a data signal which is derived, from a carry signal being produced by a logic stage, preceding said next one in the series connection, to produce an intermediate data signal, and a second logic element for receiving the carry signal from the logic stage, preceding said next one in the series connection, and for receiving the intermediate data signal to logically combine the carry signal with the intermediate signal for producing a carry signal provided to a logic stage, succeeding the next one in the series connection.
  • Tolerating a ripple signal in a logic circuits with a plurality of stages in order to perform a further operation in a subsequent stage in dependence on an operation executed in a preceding stage substantially limits the operating speed of the logic circuit and hence also limits a clock pulse frequency when such a circuit is used in a synchronously operating digital signal processing system.
  • the gate circuit ultimately appears to be a drawback because it becomes very extensive for the last flipflops of the row; this is objectionable because each bit to be added to the counting capacity requires an increasingly larger integration surface area on a semiconductor substrate with respect to the counting flipflop, so that it increasingly tends to limit the counting speed of the counter, because a logic gate is slower as its number of inputs increases.
  • U.S. patent 3,631,350 discloses an electronic device with first and second cascades of clocked multiple-input J-K flipflops, wherein the flipflops in the second cascade receive a signal from the first cascade in parallel via a clocked multiple-input further J-K flipflop.
  • the further flipflop receives the output signals of flipflops of the first cascade in parallel.
  • a drawback of this embodiment again is the large number of signal leads and the absence of a modular architecture.
  • a circuit in accordance with the invention is characterized in that at least a particular one of the logic stages comprises a clock controlled storage element for transfer of the carry signal from the logic stage, preceding the particular one of the logic stages in the series connection, to the second logic element of the particular one of the logic stages.
  • a storage element By insertion of a storage element so that, for example, after the appearance of a clock pulse for the control of the logic stages a ripple signal is blocked after having partly traversed the ripple path, a steady state is always realized despite the tolerating of carry signals propagating from one stage to another as a ripple signal with delays so that the logic circuit is suitable for use in a system synchronized by means of clock pulses.
  • the clock frequency is substantially higher than in a network in which the carry signal propagates without obstruction as a ripple signal through all parts of the carry signal path.
  • a carry signal in the sense of the invention can propagate from components which process the least-significant bits to components which process the more significant bits but also vice versa.
  • a simple example in this respect is a comparator which compares multi-bit words and in which the comparison of two bits of the same significance can generate a carry signal which propagates optionally in the direction of the lower-order bits or in the direction of the higher-order bits (for example, in order to obtain a comparison result more quickly).
  • Fig. 1 shows a synchronous counter in accordance with the invention
  • Fig. 2 shows a flipflop circuit used in the counter shown in Fig. 1.
  • Fig. 1 shows a synchronous counter in accordance with the invention which can act as an address generator for a semiconductor memory.
  • the counter comprises a number of counting flipflops TF0, TF1, ... TF14 and a number of AND-gates EE1, EE2, EE3 to EE14 and a further number of AND-gates TE3, TE4 to TE14.
  • the counter shown in Fig. 1 comprises an input I which is connected to the input of the counting flipflop TF0 and also to an input of the AND-gates EE1 and EE2.
  • the output of the counting flipflop TF0 is connected to a further input the AND-gate EE1 as well as to a further input of the AND-gate EE2.
  • the output of the counting flipflop TF0 forms an address bit A0.
  • the output of the AND-gate EE1 is connected to the input of the second counting flipflop TF1.
  • the output of the counting flipflop TF1 forms the address bit A1 and is also connected to the third input of the AND-gate EE2.
  • the output of the AND-gate EE2 is connected to an input of the counting flipflop TF2 and to an enable line EP whereto all further AND-gates EE3, EE4 etc. to EE14 are connected by way of a first input.
  • the output of the counting flipflop TF2 forms the address bit A2 and a carry signal ET for the next counting flipflop TF3. This carry signal ET is applied, via the AND-gate EE3, to the input of the counting flipflop TF3.
  • the circuit has such a regular construction that the output of the counting flipflop TFi forms the address bit Ai. Furthermore, the output of the counting flipflop TFi is connected, via a carry AND-gate TEi and an enable AND-gate EEi+1, to the input of the counting flipflop TFi+1.
  • the variable i can assume the values 3, 4, ... to 14. It is to be noted that not all outputs of the carry AND-gates TEi are directly connected to the inputs of the carry gate TEi + 1.
  • the output signal of the carry AND-gate TE5 is applied, via a storage element in the form of a flipflop DF1, to the carry AND-gate TE6.
  • the output of the AND-gate TE8 is applied, via a similar storage element, i.e. the flipflop DF2, to the AND-gate TE9 and the output of the AND-gate TE11 is applied, via a similar storage element, i.e. the flipflop DF3, to the input of the AND-gate TE12.
  • the flipflop circuits used in Fig. 1, i.e. the counting flipflops TF0 to TF14, will be described in detail hereinafter with reference to Fig. 2.
  • the operation of the synchronous counter shown in Fig. 1 is as follows.
  • the flipflops used in Fig. 1 all receive a clock signal clk.
  • the counter flipflops TF0 to TF14 are so-called toggle flipflops, the pipeline flipflops DF1, DF2 and DF3 being so-called D-flipflops.
  • the flipflop TF0 therefore, is a one-bit counter.
  • the combination of the flipflops TF0, TF1, TF2 and the AND-gates EE1 and EE2 constitutes an eight-bit counter.
  • the input I is connected, either directly or via a single AND-gate EE1 or EE2, to the inputs of the flipflop TF0, TF1 and TF2, so that the counting operations in these flipflops take place substantially in parallel.
  • the output signal of the AND-gate EE2 should then be logic high, the output signals of the preceding counting flipflops TF3, ..., TFi-1 should also be logic high, like the output of the counting flipflop TF2.
  • a next clock signal should occur only after the output signal of the counting flipflop TF2 has traversed all AND-gates TE3 to TE14. This substantially limits the counting speed of the synchronous counter.
  • a carry signal which traverses the AND-gates TE3, TE4, TE5 as a ripple signal is now taken over by the D-flipflop DF1 in response to the next clock signal, and is only subsequently applied to the following AND-gates TE6, TE7 etc.
  • the carry signal is stored in the D-flipflop DF2 so that it is only subsequently applied to the subsequent AND-gates TE9 to TE11 etc.
  • a steady, desirable logic state is always ensured on the address output terminals A0 to A14, despite the high frequency of a clock signal.
  • the delay incurred by carry signals while traversing the AND-gates TE3 to TE14 is distributed over a number of clock periods. This enables a high clock frequency.
  • Various groups can be distinguished in the counter shown in Fig. 1. A first group actually operates in parallel and comprises the counting flipflops TF0, TF1 and TF2 which, having only one gate delay, hardly influence the counting speed.
  • a second part concerns a series connection of a number of counting flipflops TF3 to TF14 and a number of AND-gates TE3 to TE14 via which a carry signal must propagate.
  • a carry signal is admitted to a next counting flipflop TFi via a gate EEi by an enable signal on the enable line EP, which enable signal is applied in parallel to all access AND-gates EE3 to EE14.
  • the construction of the synchronous counter shown has the following consequences. The counter itself is very well suitable for use in a synchronous timing organization.
  • a very high counting frequency equal to the clock frequency can be achieved for as long as the delay incurred by the carry signals in the various parts TE3, 4, 5, and DF1, EE3, 4, 5, 6; TE6, 7, 8 and DF2, EE7, 8, 9; TE9, 10, 11 and DF3, EE10, 11, 12 is less than the clock pulse period.
  • the counting flipflops TFi Apart from the series connection of the counting flipflops TFi, hardly andy further hardware in the form of logic gates and further flipflops is required and the number of interconnections is limited. Consequently, the counter can be extended so as to form a counter for a larger number of bits.
  • the various parts of the counter to be distinguished as the parallel part and the serial part which are separated from one another by the pipeline flipflops DF1, DF2, DF3, always contain a correct counting code. It can be simple indicated that a counter has reached its full count and hence enters an overflow state.
  • the pipeline flipflops DF1, DF2, DF3 do not require reset facilities.
  • the counting procedure can be stopped as desired and can be subsequently resumed without any problems.
  • the counting direction can be reversed without problems, as will be described hereinafter, and the setting of an arbitrary counting position of the counter must be followed by a waiting period amounting to a number of clock periods equal to the number of pipeline flipflops, in this case DF1 to DF3.
  • Fig. 2 shows a flipflop TFi of Fig. 1.
  • This flipflop TFi comprises a first EXCLUSIVE-OR gate EO1, a second EXCLUSIVE-OR gate E02 and a D-flipflop DF.
  • a first input of the EXCLUSIVE-OR gate EO1 constitutes the input of the flipflop TFi.
  • the output of the EXCLUSIVE-OR gate EO1 is connected to the D-input of the flipflop DF.
  • the output of the flipflop DF is connected to a first input of the EXCLUSIVE-OR gate EO2 and also to the second input of the EXCLUSIVE-OR gate EO1.
  • the flipflop DF shown forms, together with the EXCLUSIVE-OR gate EO1, a flipflop which is connected as a toggle.
  • the output of the EXCLUSIVE-OR gate EO2 constitutes the output of the flipflop TFi.
  • the second input of the EXCLUSIVE-OR gate EO2 determines the counting direction of the synchronous counter shown in Fig. 1.
  • This second input of the EXCLUSIVE-OR gate EO2 of the flipflop TFi is connected to inputs of the EXCLUSIVE-OR gates EO2 of the other flipflops TFi of the counter shown in Fig. 1.
  • synchronous counting circuits for the purpose of illustration of the invention.
  • the invention can also be used in logic circuits in which operations other than counting operations are performed, for example, addition and multiplication operations (parallel adders, multipliers, etc.).
  • the effective speed of operation will be lower than the maximum speed that can be achieved by means of the clock pulse frequency.
  • the effective speed of operation will be substantially higher than a speed of operation to be achieved in, for example a parallel adder in which carry signals can propagate through all adder modules as a ripple signal.
  • An adder circuit in accordance with the invention could be organized as follows.
  • the parallel adder could perform an addition in three steps under the control of clock pulses, a first part of the adder adding two groups (for example, having a width of 8 bits) of least-significant bits and comprising transport means for the propagation of carry signals.
  • the duration of propagation of the carry signals should be shorter than the inverse of the clock pulse frequency.
  • a carry signal, if any, to be assigned to a more-significant bit is stored in a storage element in response to a next clock pulse; this element applies the carry signal to the transport means of a second part of the adder.
  • two groups of bits having a higher significance are also added in the second part (for example, bits 9 to 16 of words having a width of 24 bits).
  • a carry signal, if any, generated int he second part of the adder is applied to a third part of the adder in response to the subsequent clock pulse, which third part adds the groups of most-significant bits.

Landscapes

  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)

Claims (4)

  1. Synchrone Logikschaltung, die von einer Reihenschaltung aus einer Vielzahl von Logikstufen (TFi/TEi; i=3, 4, ..., 14) gebildet wird, wobei:
    - jede Logikstufe (TFi/TFe) ein Taktsignal empfängt;
    - in der Reihenschaltung jede folgende der Logikstufen (TFi/TFe) folgendes umfaßt:
    - ein erstes Logikelement (TFi) zum Empfang eines Datensignals, das aus einem von einer Logikstufe, die der genannten folgenden in der Reihenschaltung vorangeht, erzeugten Übertragssignal abgeleitet wird, zur Erzeugung eines Zwischendatensignals (Ai);
    - ein zweites Logikelement (TEi) zum Empfang des aus der Logikstufe, die der genannten folgenden in der Reihenschaltung vorangeht, kommenden Übertragssignals und zum Empfang des Zwischendatensignals, um das Übertragssignal mit dem Zwischensignal logisch zu kombinieren, zur Erzeugung eines Übertragssignals, das einer Logikstufe zugeführt wird, die der folgenden in der Reihenschaltung folgt, dadurch gekennzeichnet, daß mindestens eine bestimmte der Logikstufen (TF6/TF6) ein taktgesteuertes Speicherelement (DF1) umfaßt zur Übertragung des Übertragssignals von der Logikstufe, die der bestimmten der Logikstufen in der Reihenschaltung vorangeht, zu dem zweiten Logikelement der bestimmten der Logikstufen.
  2. Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß die ersten Logikelemente gleichförmig sind und daß die zweiten Logikelemente gleichförmig sind.
  3. Schaltung nach Anspruch 2, dadurch gekennzeichnet, daß
    - jedes jeweilige eine der ersten Logikelemente ein jeweiliges Toggle-Flipflop umfaßt;
    - jedes jeweilige eine der zweiten Logikelemente ein jeweiliges UND-Gatter umfaßt;
    - das taktgesteuerte Speicherelement ein D-Flipflop umfaßt.
  4. Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß jede folgende der Logikstufen ein Freigabe-Logikgatter (EEi; i=3, 4, ..., 14) zwischen der vorhergehenden Logikstufe und dem ersten Logikelement der genannten folgenden Logikstufe hat, wobei das Freigabe-Logikgatter in Reaktion auf ein den Freigabegattern von der Vielzahl von Logikstufen parallel zugeführtes Steuersignal (EP) für die Übertragung des Datensignals zum ersten Logikelement sorgt.
EP89904859A 1988-04-05 1989-04-05 Synchroner logischer schaltkreis mit übertragungssignalsteuerung Expired - Lifetime EP0364565B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NL8800860A NL8800860A (nl) 1988-04-05 1988-04-05 Logisch netwerk met overdrachtssignaalbesturing.
NL8800860 1988-04-05
PCT/NL1989/000018 WO1989010028A1 (en) 1988-04-05 1989-04-05 Synchronous logic network with transfer signal control

Publications (2)

Publication Number Publication Date
EP0364565A1 EP0364565A1 (de) 1990-04-25
EP0364565B1 true EP0364565B1 (de) 1995-08-16

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EP89904859A Expired - Lifetime EP0364565B1 (de) 1988-04-05 1989-04-05 Synchroner logischer schaltkreis mit übertragungssignalsteuerung

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EP (1) EP0364565B1 (de)
JP (1) JPH02503859A (de)
DE (1) DE68923843T2 (de)
NL (1) NL8800860A (de)
WO (1) WO1989010028A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2695773B1 (fr) * 1992-09-11 1994-10-21 Thomson Csf Circuit de comptage pour division de fréquence et synthétiseur équipé d'un tel circuit.
EP0860949A1 (de) * 1997-02-19 1998-08-26 Hewlett-Packard Company Synchroner binärer Zähler

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3631350A (en) * 1970-09-15 1971-12-28 Collins Radio Co Synchronous counting apparatus
US3753127A (en) * 1971-12-27 1973-08-14 Singer Co Pseudosynchronous counter
JPS6240824A (ja) * 1985-08-19 1987-02-21 Toshiba Corp 同期型バイナリカウンタ

Also Published As

Publication number Publication date
WO1989010028A1 (en) 1989-10-19
NL8800860A (nl) 1989-11-01
DE68923843D1 (de) 1995-09-21
DE68923843T2 (de) 1996-04-04
EP0364565A1 (de) 1990-04-25
JPH02503859A (ja) 1990-11-08

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