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EP0356556A1 - Multi-input four quadrant multiplier - Google Patents

Multi-input four quadrant multiplier Download PDF

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Publication number
EP0356556A1
EP0356556A1 EP88114225A EP88114225A EP0356556A1 EP 0356556 A1 EP0356556 A1 EP 0356556A1 EP 88114225 A EP88114225 A EP 88114225A EP 88114225 A EP88114225 A EP 88114225A EP 0356556 A1 EP0356556 A1 EP 0356556A1
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EP
European Patent Office
Prior art keywords
transistor
emitter
collector
input
resistor
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EP88114225A
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German (de)
French (fr)
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EP0356556B1 (en
Inventor
Richard Dipl.-Ing. Stepp
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Siemens AG
Siemens Corp
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Siemens AG
Siemens Corp
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Priority to DE88114225T priority Critical patent/DE3885280D1/en
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to AT88114225T priority patent/ATE96558T1/en
Priority to EP88114225A priority patent/EP0356556B1/en
Priority to ES88114225T priority patent/ES2045047T3/en
Priority to US07/393,607 priority patent/US5115409A/en
Priority to JP1222781A priority patent/JPH02113382A/en
Priority to DK426489A priority patent/DK426489A/en
Priority to PT91582A priority patent/PT91582B/en
Priority to FI894071A priority patent/FI894071A7/en
Publication of EP0356556A1 publication Critical patent/EP0356556A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

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  • the invention relates to a four-quadrant multiplier with more than two signal inputs for multiplying an input signal by a plurality of further input signals, at the output of which the individual multiplication results are additively linked, according to the preamble of patent claim 1.
  • Such multipliers are e.g. in the modulation of different signals on a common carrier or the detection of signals with different frequencies that are modulated on a carrier.
  • Figure 1 shows such a known circuit.
  • a first and a second transistor T1 and T2 and a third and a fourth transistor T3 and T4 each form a differential amplifier pair with directly connected emitters.
  • the collector terminal of the first transistor T1 is connected to the collector terminal of the third transistor T3 and connected via a first resistor R1 to a supply potential Uv and forms a signal output terminal + z.
  • the collector connection of the second transistor T2 is also the collector terminal of the fourth transistor T4 connected together, connected via a second resistor R2 to the supply potential Uv and forms another signal output terminal -z, which together with the signal output terminal + z can provide a symmetrical output signal.
  • the base connections of these transistors do not represent a linear signal input connected to the collector terminal of the fifth transistor T5 and connected via a first diode D1 to a current source which, in particular, connects a third resistor R3 connected to the supply potential Uv with another terminal.
  • the base connection of the second transistor T2 is connected to the base connection of the third transistor T3 and the collector connection of a sixth transistor T6 and connected via a second diode D2 to said third resistor R3 or said current source.
  • the emitter connections of the fifth transistor T5 and the sixth transistor T6 are either connected to one another via a resistor and each connected to the reference potential via a separate current source, or, as shown in FIG. 1, connected to one another via a fourth resistor Rx1 and a fifth resistor Rx2 , wherein the connection node of the resistors Rx1 and Rx2 is connected to the reference potential (ground) via a first constant current source I1.
  • the base terminal of the sixth transistor T6 thus forms the first input terminal + x and the base terminal of the fifth transistor T5 forms a second input terminal -x of the multiplier.
  • a symmetrical input signal can be fed in via the terminals + x and -x, the multiplier having linear transmission properties with respect to this signal input.
  • the emitter connections of the transistors T1 and T2 are connected to the collector connection of the seventh transistor T7.
  • the emitter connections of transistors T3 and T4 are connected to the collector connection of an eighth transistor T8 bound.
  • the emitter connections of the transistors T7 and T8 are connected together via a coupling resistor Ry.
  • the emitter terminal of the seventh transistor T7 is connected to the reference potential via a second constant current source I2 and the emitter terminal of the eighth transistor T8 is connected to the reference potential via a third constant current source I3.
  • the base terminal of the seventh transistor T7 forms the third input terminal + y and the base terminal of the eighth transistor T8 forms the fourth input terminal -y of the multiplier.
  • a symmetrical input signal can be fed in via the terminals + y and -y, the multiplier also having linear transmission properties with respect to this signal input due to the negative feedback caused by the coupling resistance Ry.
  • Circuits of this type are particularly suitable for multiplying at least one digital input signal by another input signal.
  • a corresponding number of such known multipliers could be interconnected.
  • this interconnection of several multipliers has certain disadvantages, which have a particularly negative effect when used as a detector or modulator.
  • Transistors or diodes manufactured in one operation and on a chip are to a great extent similar, but the slightly different large signal behavior, the scattering of the amplification factors etc. of the individual transistors, especially if many transistors are connected appropriately, among other things, for different DC voltages Offsets in individual amplifier stages and also the individual signal inputs of the overall multiplier circuit are weighted differently. Since the DC voltage offset is problematic in such circuits, the consideration is important tion of several different DC voltage offsets is particularly noticeable.
  • the object of the invention is to provide a multiplier for multiplying an input signal by a plurality of further input signals, the individual multiplication results to be provided in an additively linked manner at the output, in which these disadvantages do not occur or are reduced to a non-disturbing extent.
  • Figure 2 shows the subject matter of claim 1, which is particularly suitable for processing rectangular or digital signals.
  • Figure 3 shows the subject matter of claim 2.
  • Circuit elements which fulfill the same or a similar function are provided with the same or similar reference symbols in FIG. 1, FIG. 2 and FIG. 3.
  • the particular advantage of the circuits according to the invention resides in the fact that the transistors T1, T2, T3 and T4 connected in a corresponding control circuit in the form of a Gilbert cell are designed as multi-emitter transistors for this special application.
  • the circuit complexity and the chip area requirement of circuits according to the invention is thus hardly greater than that of single-stage multipliers.
  • the input signal that is fed in at the input terminals + x / -x is mixed in a known manner with the input signals that are fed in at the terminals + y1 / -y1, + y2 / -y2 etc., or multiplied in the linear control range . Since the collector currents of the transistors T1, T2, T3 and T4 each contain the sum of their emitter currents, the individual multiplication products are provided additively linked at the output terminals + z / -z.
  • the multiplication product of the input signal fed in at the input + x / -x with an input signal fed in at another signal input is added to the other multiplication products which are formed from the input signal by the input + x / -x and the input signals of the remaining signal inputs subtracted, is only due to the sign of the individual input signal.
  • the sign can be reversed by swapping the input terminals, for example + y1 with -y1.
  • the circuit shown in FIG. 3 and described in claim 2 is particularly suitable for applications in which the transmission behavior of the multiplier is to be linear with respect to the individual inputs.
  • This linear transmission behavior with regard to the inputs + y1 / -y1, + y2 / -y2, etc. is ensured in particular by the negative feedback which the coupling resistors Ry1, Ry2, ... bring about.
  • controllable current sources Is21, Is22, ... Is31, Is32, ... are designed as conventional constant current sources which are switched on or off depending on the signal level to be fed in in each case. If the collector of a transistor Tx is provided as the current input of these controllable current sources Is21, ..., the emitter of which is connected to another potential, in particular the reference potential and at the same time to the emitter of a further transistor Ty, the base connection of the transistor Tx being connected to the base connection and the collector connection of the transistor Ty is connected together and forms the control input of this current source and this control input is connected to the supply potential Uv via a resistor Rv, for example the control input of the current source constructed in this way can directly from the output of a logic gate, in particular an I2L gate G1, G2 , ... can be controlled.
  • an inverting input terminal -y1, -y2, ... can be controlled with the output signal of a logic gate G1, G2, ... and a non-inverting input terminal + y1, + y2, ... with the output signal of this logic gate G1, G2, ... which is inverse to this output signal.

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Abstract

Zum Multiplizieren mehrerer Signale mit einem gleichen weiteren Signal wird ein Vier-Quadranten-Multiplizierer auf der Grundlage der Gilbert-Zelle eingesetzt, wobei die Transistoren der beiden gekoppelten Differenzverstärkerpaare des einen, im Sinne der Gilbert-Zelle über eine Dioden-Transistor-Strecke angesteuerten Einganges des inneren Multiplizierers als Multiemitter-Transistoren ausgeführt sind und jeweils ein Emitterpaar des rechten und des linken Multipliziererzweiges über je eine steuerbare Stromquelle bzw. die Serienschaltung eines Transistors und einer Stromquelle gegenläufig ansteuerbar sind. Für die Verarbeitung von rechteckförmigen Signalen wird als steuerbare Stromquelle eine schaltbare Stromquelle vorgeschlagen, die insbesondere durch I²L-Gatter ansteuerbar ist.A four-quadrant multiplier based on the Gilbert cell is used to multiply several signals by the same additional signal, the transistors of the two coupled differential amplifier pairs of the one input, which in the sense of the Gilbert cell is controlled via a diode-transistor path of the inner multiplier are designed as multi-emitter transistors and an emitter pair of the right and left multiplier branches can be controlled in opposite directions via a controllable current source or the series connection of a transistor and a current source. For the processing of rectangular signals, a switchable current source is proposed as a controllable current source, which can be controlled in particular by I²L gates.

Description

Die Erfindung betrifft einen Vier-Quadranten-Multiplizierer mit mehr als zwei Signaleingängen zum Multiplizieren eines Eingangs­signals mit mehreren weiteren Eingangssignalen, an dessen Aus­gang die einzelnen Multiplikationsergebnisse additiv verknüpft sind, nach dem Oberbegriff des Patentanspruches 1.The invention relates to a four-quadrant multiplier with more than two signal inputs for multiplying an input signal by a plurality of further input signals, at the output of which the individual multiplication results are additively linked, according to the preamble of patent claim 1.

Solche Multiplizierer werden z.B. bei der Modulation verschie­dener Signale auf einen gemeinsamen Träger oder der Detektion von Signalen mit verschiedenen Frequenzen, die auf einem Träger aufmoduliert sind, benötigt.Such multipliers are e.g. in the modulation of different signals on a common carrier or the detection of signals with different frequencies that are modulated on a carrier.

Vier-Quadranten-Multiplizierer mit zwei linearen Signaleingän­gen sowie deren Funktionsweise sind unter anderem in dem "Data-­Acquisition Databook 1984, Vol. 1 Integrated Circuits" von Anolog Devices, Inc., auf den Seiten 6-9 bis 6-16 sowie in dem Buch "Halbleiterschaltungstechnik", 5. Auflage 1980 von U. Tietze, Ch. Schenk auf den Seiten 227 ff., insbesondere Abb. 11.41, beschrieben. Es handelt sich hierbei um Multiplizierer, die auf der Grundlage der sogenannten Gilbert-Zelle aufgebaut sind.Four-quadrant multipliers with two linear signal inputs and their mode of operation are described, inter alia, in "Data Acquisition Databook 1984, Vol. 1 Integrated Circuits" by Anolog Devices, Inc., on pages 6-9 to 6-16 and in the Book "semiconductor circuit technology", 5th edition 1980 by U. Tietze, Ch. Schenk on pages 227 ff., In particular Fig. 11.41. These are multipliers that are based on the so-called Gilbert cell.

Figur 1 zeigt eine solche bekannte Schaltung. Ein erster und ein zweiter Transistor T1 und T2 sowie ein dritter und ein vierter Transistor T3 und T4 bilden jeweils ein Differenzver­stärkerpaar mit unmittelbar verbundenen Emittern. Der Kollek­toranschluß des ersten Transistors T1 ist mit dem Kollektoran­schluß des dritten Transistors T3 zusammengeschaltet und über einen ersten Widerstand R1 mit einem Versorgungspotential Uv verbunden und bildet eine Signalausgangsklemme +z. In gleicher Weise ist der Kollektoranschluß des zweiten Transistors T2 mit dem Kollektoranschluß des vierten Transistors T4 zusammenge­schaltet, über einen zweiten Widerstand R2 mit dem Versorgungs­potential Uv verbunden und bildet eine andere Signalausgangs­klemme -z, die zusammen mit der Signalausgangsklemme +z ein symmetrisches Ausgangssignal bereitstellen kann. Da die Emit­teranschlüsse der Transistoren T1 und T2 sowie T3 und T4 ohne Gegenkopplungswiderstand miteinander verbunden sind, stellen die Basisanschlüsse dieser Transistoren keinen linearen Signal­eingang dar. Um einen linearen Signaleingang zu erhalten, ist der Basisanschluß des ersten Transistors T1 mit dem Basisan­schluß des vierten Transistors T4 sowie dem Kollektoranschluß des fünften Transistors T5 zusammengeschaltet und über eine er­ste Diode D1 an eine Stromquelle, die insbesondere einen mit einem anderen Anschluß an das Versorgungspotential Uv ange­schlossenen dritten Widerstand R3 geschaltet. Analog ist der Basisanschluß des zweiten Transistors T2 mit dem Basisanschluß des dritten Transistors T3 und dem Kollektoranschluß eines sechsten Transistors T6 zusammengeschaltet und über eine zweite Diode D2 an den besagten dritten Widerstand R3 bzw. die besagte Stromquelle geschaltet. Die Emitteranschlüsse des fünften Tran­sistors T5 und des sechsten Transistors T6 sind entweder über einen Widerstand miteinander verbunden und je über eine eigene Stromquelle an das Bezugspotential geschaltet, oder aber, wie in Figur 1 gezeigt, über einen vierten Widerstand Rx1 und einen fünften Widerstand Rx2 miteinander verbunden, wobei der Verbin­dungsknoten der Widerstände Rx1 und Rx2 über eine erste Kon­stantstromquelle I1 an das Bezugspotential (Masse) geschaltet ist. Der Basisanschluß des sechsten Transistors T6 bildet somit die erste Eingangsklemme +x und der Basisanschluß des fünften Transistors T5 bildet eine zweite Eingangsklemme -x des Multi­plizierers. Über die Klemmen +x und -x ist das Einspeisen eines symmetrischen Eingangssignales möglich, wobei der Multiplizie­rer bezüglich dieses Signaleinganges lineare Übertragungseigen­schaften besitzt. Die Emitteranschlüsse der Transistoren T1 und T2 sind mit dem Kollektoranschluß des siebten Transistors T7 verbunden. Die Emitteranschlüsse der Transistoren T3 und T4 sind mit dem Kollektoranschluß eines achten Transistors T8 ver­ bunden. Die Emitteranschlüsse der Transistoren T7 und T8 sind über einen Koppelwiderstand Ry zusammengeschaltet. Der Emitter­anschluß des siebten Transistors T7 ist über eine zweite Kon­stantstromquelle I2 an das Bezugspotential geschaltet und der Emitteranschluß des achten Transistors T8 ist über eine dritte Konstantstromquelle I3 an das Bezugspotential angeschlossen. Der Basisanschluß des siebten Transistors T7 bildet die dritte Eingangsklemme +y und der Basisanschluß des achten Transistors T8 bildet die vierte Eingangsklemme -y des Multiplizierers. Über die Klemmen +y und -y ist das Einspeisen eines symmetri­schen Eingangssignales möglich, wobei der Multiplizierer infol­ge der Gegenkopplung, die durch den Koppelwiderstand Ry bewirkt wird, auch bezüglich dieses Signaleinganges lineare Übertra­gungseigenschaften aufweist.Figure 1 shows such a known circuit. A first and a second transistor T1 and T2 and a third and a fourth transistor T3 and T4 each form a differential amplifier pair with directly connected emitters. The collector terminal of the first transistor T1 is connected to the collector terminal of the third transistor T3 and connected via a first resistor R1 to a supply potential Uv and forms a signal output terminal + z. In the same way, the collector connection of the second transistor T2 is also the collector terminal of the fourth transistor T4 connected together, connected via a second resistor R2 to the supply potential Uv and forms another signal output terminal -z, which together with the signal output terminal + z can provide a symmetrical output signal. Since the emitter connections of the transistors T1 and T2 as well as T3 and T4 are connected to each other without negative feedback resistance, the base connections of these transistors do not represent a linear signal input connected to the collector terminal of the fifth transistor T5 and connected via a first diode D1 to a current source which, in particular, connects a third resistor R3 connected to the supply potential Uv with another terminal. Analogously, the base connection of the second transistor T2 is connected to the base connection of the third transistor T3 and the collector connection of a sixth transistor T6 and connected via a second diode D2 to said third resistor R3 or said current source. The emitter connections of the fifth transistor T5 and the sixth transistor T6 are either connected to one another via a resistor and each connected to the reference potential via a separate current source, or, as shown in FIG. 1, connected to one another via a fourth resistor Rx1 and a fifth resistor Rx2 , wherein the connection node of the resistors Rx1 and Rx2 is connected to the reference potential (ground) via a first constant current source I1. The base terminal of the sixth transistor T6 thus forms the first input terminal + x and the base terminal of the fifth transistor T5 forms a second input terminal -x of the multiplier. A symmetrical input signal can be fed in via the terminals + x and -x, the multiplier having linear transmission properties with respect to this signal input. The emitter connections of the transistors T1 and T2 are connected to the collector connection of the seventh transistor T7. The emitter connections of transistors T3 and T4 are connected to the collector connection of an eighth transistor T8 bound. The emitter connections of the transistors T7 and T8 are connected together via a coupling resistor Ry. The emitter terminal of the seventh transistor T7 is connected to the reference potential via a second constant current source I2 and the emitter terminal of the eighth transistor T8 is connected to the reference potential via a third constant current source I3. The base terminal of the seventh transistor T7 forms the third input terminal + y and the base terminal of the eighth transistor T8 forms the fourth input terminal -y of the multiplier. A symmetrical input signal can be fed in via the terminals + y and -y, the multiplier also having linear transmission properties with respect to this signal input due to the negative feedback caused by the coupling resistance Ry.

Schaltungen dieser Art eignen sich besonders gut zum Multipli­zieren von mindestens einem Digitaleingangssignal mit einem weiteren Eingangssignal. Um entsprechende Multiplizierer mit mehr als zwei Signaleingängen zu erhalten, wobei ein Eingangs­signal mit mehreren weiteren Eingangssignalen multipliziert werden soll und die einzelnen Multiplikationsergebnisse addiert werden sollen, könnte man eine entsprechende Anzahl solcher be­kannter Multiplizierer zusammenschalten. Dieses Zusammenschal­ten mehrerer Multiplizierer bringt jedoch gewisse Nachteile mit sich, die sich insbesondere bei dem Einsatz als Detektor oder Modulator negativ bemerkbar machen.Circuits of this type are particularly suitable for multiplying at least one digital input signal by another input signal. In order to obtain corresponding multipliers with more than two signal inputs, one input signal to be multiplied by several further input signals and the individual multiplication results to be added, a corresponding number of such known multipliers could be interconnected. However, this interconnection of several multipliers has certain disadvantages, which have a particularly negative effect when used as a detector or modulator.

In einem Arbeitsgang und auf einem Chip hergestellte Transisto­ren bzw. Dioden sind sich in hohem Maße ähnlich, doch sorgt das geringfügig andere Großsignalverhalten, die Streuung der Ver­stärkungsfaktoren etc. der einzelnen Transistoren, speziell wenn viele Transistoren entsprechend zusammengeschaltet sind, unter anderem für unterschiedliche Gleichspannungs-Offsets in einzelnen Verstärkerstufen und außerdem werden die einzelnen Signaleingänge der Multiplizierer-Gesamtschaltung unterschied­lich gewichtet. Da der Gleichspannungs-Offset in solchen Schaltungen sowieso problematisch ist, macht sich die Überlage­ rung mehrerer verschiedener Gleichspannungs-Offsets besonders negativ bemerkbar.Transistors or diodes manufactured in one operation and on a chip are to a great extent similar, but the slightly different large signal behavior, the scattering of the amplification factors etc. of the individual transistors, especially if many transistors are connected appropriately, among other things, for different DC voltages Offsets in individual amplifier stages and also the individual signal inputs of the overall multiplier circuit are weighted differently. Since the DC voltage offset is problematic in such circuits, the consideration is important tion of several different DC voltage offsets is particularly noticeable.

Weitere Nachteile einer solchen Schaltung sind der große Chip­flächenbedarf und die bei hohen Frequenzen eventuell störenden Leiterbahnkapazitäten.Further disadvantages of such a circuit are the large chip area requirement and the interconnect capacitance, which may interfere at high frequencies.

Aufgabe der Erfindung ist das Bereitstellen eines Multiplizie­rers zum Multiplizieren eines Eingangssignales mit mehreren weiteren Eingangssignalen, wobei die einzelnen Multiplikations­ergebnisse additiv verknüpft am Ausgang bereitgestellt werden sollen, bei dem diese Nachteile nicht auftreten oder auf ein nicht störendes Maß reduziert sind.The object of the invention is to provide a multiplier for multiplying an input signal by a plurality of further input signals, the individual multiplication results to be provided in an additively linked manner at the output, in which these disadvantages do not occur or are reduced to a non-disturbing extent.

Diese Aufgabe wird durch eine Schaltungsanordnung nach dem Pa­tentanspruch 1 sowie durch eine Schaltungsanordnung nach dem Patentanspruch 2 gelöst.This object is achieved by a circuit arrangement according to claim 1 and by a circuit arrangement according to claim 2.

Günstige Ausgestaltungsformen sind Gegenstand von Unteransprü­chen.Favorable design forms are the subject of subclaims.

Figur 2 zeigt den Gegenstand des Patentanspruches 1, der sich insbesondere für die Verarbeitung von rechteckförmigen bzw. di­gitalen Signalen eignet.Figure 2 shows the subject matter of claim 1, which is particularly suitable for processing rectangular or digital signals.

Figur 3 zeigt den Gegenstand des Patentanspruches 2.Figure 3 shows the subject matter of claim 2.

Schaltungselemente, die die gleiche oder eine ähnliche Funktion erfüllen sind in Figur 1, Figur 2 und Figur 3 mit gleichen oder ähnlichen Bezugszeichen versehen.Circuit elements which fulfill the same or a similar function are provided with the same or similar reference symbols in FIG. 1, FIG. 2 and FIG. 3.

Die prinzipielle Funktionsweise der in Figur 2 und Figur 3 ge­zeigten und in den Patentansprüchen 1 und 2 beschriebenen Schaltungen ist analog der dem Fachmann geläufigen Funktions­weise der in Figur 1 gezeigten Schaltung.The basic mode of operation of the circuits shown in FIG. 2 and FIG. 3 and described in claims 1 and 2 is analogous to the mode of operation of the circuit shown in FIG.

Der besondere Vorteil der erfindungsgemäßen Schaltungen liegt darin begründet, daß die in einer entsprechenden Ansteuerschal­tung in Form einer Gilbert-Zelle geschalteten Transistoren T1, T2, T3 und T4 für diese spezielle Anwendung als Multiemitter­transistoren ausgeführt sind. Der Schaltungsaufwand sowie der Chipflächenbedarf erfindungsgemäßer Schaltungen ist somit kaum größer als der von einstufigen Multiplizierern.The particular advantage of the circuits according to the invention resides in the fact that the transistors T1, T2, T3 and T4 connected in a corresponding control circuit in the form of a Gilbert cell are designed as multi-emitter transistors for this special application. The circuit complexity and the chip area requirement of circuits according to the invention is thus hardly greater than that of single-stage multipliers.

Das Eingangssignal, das an den Eingangsklemmen +x/-x einge­speist wird, wird mit den Eingangssignalen, die an den Klemmen +y1/-y1, +y2/-y2 etc. eingespeist werden in bekannter Weise multiplikativ gemischt bzw. im linearen Ansteuerbereich multi­pliziert. Da die Kollektorströme der Transistoren T1, T2, T3 und T4 jeweils die Summe ihrer Emitterströme enthalten, werden die einzelnen Multiplikationsprodukte additiv verknüpft an den Ausgangsklemmen +z/-z bereitgestellt.The input signal that is fed in at the input terminals + x / -x is mixed in a known manner with the input signals that are fed in at the terminals + y1 / -y1, + y2 / -y2 etc., or multiplied in the linear control range . Since the collector currents of the transistors T1, T2, T3 and T4 each contain the sum of their emitter currents, the individual multiplication products are provided additively linked at the output terminals + z / -z.

Ob das Multiplikationsprodukt des am Eingang +x/-x eingespei­sten Eingangssignales mit einem an einem anderen Signaleingang eingespeisten Eingangssignal zu den übrigen Multiplikationspro­dukten, die aus dem Eingangssignal vom Eingang +x/-x und den Eingangssignalen der restlichen Signaleingänge gebildet werden, addiert wird oder davon subtrahiert, liegt nur am Vorzeichen des einzelnen Eingangssignales. Durch Vertauschen der Eingangs­klemmen, beispielsweise +y1 mit -y1, kann das Vorzeichen umge­dreht werden.Whether or not the multiplication product of the input signal fed in at the input + x / -x with an input signal fed in at another signal input is added to the other multiplication products which are formed from the input signal by the input + x / -x and the input signals of the remaining signal inputs subtracted, is only due to the sign of the individual input signal. The sign can be reversed by swapping the input terminals, for example + y1 with -y1.

Die in Figur 3 gezeigte und im Patentanspruch 2 beschriebene Schaltung eignet sich besonders für Anwendungsfälle, bei denen das Übertragungsverhalten des Multiplizierers bezüglich der einzelnen Eingänge linear sein soll. Dieses lineare Übertra­gungsverhalten bezüglich der Eingänge +y1/-y1, +y2/-y2, etc. wird insbesondere durch die Gegenkopplung, die die Koppelwider­stände Ry1, Ry2, ... bewirken, gewährleistet.The circuit shown in FIG. 3 and described in claim 2 is particularly suitable for applications in which the transmission behavior of the multiplier is to be linear with respect to the individual inputs. This linear transmission behavior with regard to the inputs + y1 / -y1, + y2 / -y2, etc. is ensured in particular by the negative feedback which the coupling resistors Ry1, Ry2, ... bring about.

Für erfindungsgemäße Schaltungsanordnungen ist es nicht rele­vant, ob die Emitter der Transistoren T5, T6, T7, T8, T71, T81, T72, T82, ... jeweils über einen Widerstand Ry1, ... mit dem Emitter des entsprechenden Transistors verbunden sind und je­weils über eine eigene Stromquelle an das Bezugspotential ge­schaltet sind oder ob diese Emitter über eine Serienschaltung zweier Widerstände Rx1, Rx2, ... miteinander verbunden sind und jeweils nur der Verbindungsknoten dieser Widerstände über eine Konstantstromquelle an das Bezugspotential geschaltet ist. Wie dem Buch "Halbleiter-Schaltungstechnik", 4. Auflage 1978 von U. Tietze, Ch. Schenk auf den Seiten 64 und 65 zu entnehmen ist, sind diese Ausgestaltungsformen äquivalent. Sie unterscheiden sich in ihrer Wirkung nur dadurch, daß bei zwei Stromquellen und einem Widerstand pro Emitterpaar dieser Widerstand im Ruhe­zustand stromlos ist, so daß eine Variation der Verstärkung hier keine Beeinträchtigung der Ruhepotentiale mit sich bringt. Die Wahl der entsprechenden Schaltungsausführung ist also von den jeweiligen Anforderungen abhängig, bei monolithisch inte­grierten Schaltungen aber weitgehend unkritisch.For circuit arrangements according to the invention it is not relevant whether the emitters of the transistors T5, T6, T7, T8, T71, T81, T72, T82, ... are each connected via a resistor Ry1, ... to the emitter of the corresponding transistor and are each connected to the reference potential via their own current source or whether these emitters are connected in series via two resistors Rx1, Rx2, .. are connected to one another and in each case only the connection node of these resistors is connected to the reference potential via a constant current source. As can be seen from the book "Semiconductor Circuit Technology", 4th edition 1978 by U. Tietze, Ch. Schenk on pages 64 and 65, these configurations are equivalent. They differ in their effect only in that with two current sources and one resistor per pair of emitters, this resistor is de-energized in the quiescent state, so that a variation in the amplification does not impair the quiescent potentials. The choice of the appropriate circuit design depends on the respective requirements, but is largely uncritical in the case of monolithically integrated circuits.

Wenn die in den Figuren mit +y/-y, +y1/-y1 etc. bezeichneten Signaleingänge zur Beaufschlagung mit rechteckförmigen Signalen vorgesehen sind, ist eine Multipliziererschaltung nach Figur 2 bzw. Patentanspruch 1 besonders günstig.If the signal inputs designated + y / -y, + y1 / -y1 etc. in the figures are provided for the application of rectangular signals, a multiplier circuit according to FIG. 2 or claim 1 is particularly favorable.

Hierbei kann es genügen, daß die steuerbaren Stromquellen Is21, Is22, ... Is31, Is32, ... als übliche Konstantstromquellen aus­gebildet sind, die in Abhängigkeit vom jeweils einzuspeisenden Signalpegel ein- oder ausgeschaltet sind. Wenn als Stromeingang dieser steuerbaren Stromquellen Is21, ... der Kollektor eines Transistors Tx vorgesehen ist, dessen Emitter an ein anderes Potential, insbesondere das Bezugspotential und gleichzeitig an den Emitter eines weiteren Transistors Ty geschaltet ist, wobei der Basisanschluß des Transistors Tx mit dem Basisanschluß und dem Kollektoranschluß des Transistors Ty zusammengeschaltet ist und den Steuereingang dieser Stromquelle bildet und dieser Steuereingang über einen Widerstand Rv an das Versorgungspoten­tial Uv geschaltet ist, kann beispielsweise der Steuereingang der derart aufgebauten Stromquelle unmittelbar vom Ausgang ei­nes Logikgatters, insbesondere eines I²L-Gatters G1, G2, ... angesteuert werden.It can suffice here that the controllable current sources Is21, Is22, ... Is31, Is32, ... are designed as conventional constant current sources which are switched on or off depending on the signal level to be fed in in each case. If the collector of a transistor Tx is provided as the current input of these controllable current sources Is21, ..., the emitter of which is connected to another potential, in particular the reference potential and at the same time to the emitter of a further transistor Ty, the base connection of the transistor Tx being connected to the base connection and the collector connection of the transistor Ty is connected together and forms the control input of this current source and this control input is connected to the supply potential Uv via a resistor Rv, for example the control input of the current source constructed in this way can directly from the output of a logic gate, in particular an I²L gate G1, G2 , ... can be controlled.

Um saubere Flanken des Rechtecksignals zu erhalten, kann dabei jeweils eine invertierende Eingangsklemme -y1, -y2, ... mit dem Ausgangssignal eines Logikgatters G1, G2, ... angesteuert wer­den und eine nichtinvertierende Eingangsklemme +y1, +y2, ... mit dem zu diesem Ausgangssignal inversen Ausgangssignal dieses Logikgatters G1, G2, ... angesteuert werden.In order to obtain clean edges of the square-wave signal, an inverting input terminal -y1, -y2, ... can be controlled with the output signal of a logic gate G1, G2, ... and a non-inverting input terminal + y1, + y2, ... with the output signal of this logic gate G1, G2, ... which is inverse to this output signal.

Claims (4)

1. Vier-Quadranten-Multiplizierer in Form einer monolithisch integrierten elektronischen Schaltung, bestehend aus einem er­sten Transistor (T1), dessen Kollektoranschluß mit dem Kollek­toranschluß eines dritten Transistors (T3) zusammengeschaltet und über einen ersten Widerstand (R1) mit einem Versorgungspo­tential (Uv) verbunden ist und eine Signalausgangsklemme (+z) bildet, des weiteren bestehend aus einem zweiten Transistor (T2), dessen Kollektoranschluß mit dem Kollektoranschluß eines vierten Transistors (T4) zusammengeschaltet und über einen zweiten Widerstand (R2) mit dem Versorgungspotential (Uv) ver­bunden ist und eine andere Signalausgangsklemme (-z) bildet, wobei der Basisanschluß des ersten Transistors (T1) mit dem Ba­sisanschluß des vierten Transistors (T4) sowie dem Kollektoran­schluß eines fünften Transistors (T5) und der Anode einer er­sten Diode (D1) zusammengeschaltet ist, wobei der Basisanschluß des zweiten Transistors (T2) mit dem Basisanschluß des dritten Transistors (T3) und dem Kollektoranschluß eines sechsten Tran­sistors (T6) sowie der Anode einer zweiten Diode (D2) zusammen­geschaltet ist, wobei die Kathode der ersten Diode (D1) gemein­sam mit der Kathode der zweiten Diode (D2) über einen dritten Widerstand (R3) an das Versorgungspotential (Uv) angeschlossen ist, wobei die Emitteranschlüsse des fünften Transistors (T5) und des sechsten Transistors (T6) über die Serienschaltung aus einem vierten Widerstand (Rx1) und einem fünften Widerstand (Rx2) miteinander verbunden sind, wobei der Verbindungsknoten dieser Widerstände (Rx1, Rx2) über eine erste Stromquelle (I1) an das Bezugspotential (Masse) geschaltet ist und wobei der Basisanschluß des sechsten Transistors (T6) die erste Eingangs­klemme (+x) und der Basisanschluß des fünften Transistors (T5) die zweite Eingangsklemme (-x) des Multiplizierers bilden,
dadurch gekennzeichnet,
daß als erster, als zweiter, als dritter und als vierter Tran­sistor (T1, T2, T3, T4) in ihrem Aufbau identische Multiemit­tertransistoren vorgesehen sind, daß jeder Emitter des ersten Transistors (T1) mit je einem Emitter des zweiten Transistors (T2) und dem Stromeingang einer jeweiligen steuerbaren Strom­quelle (Is21, Is22, ...) zusammengeschaltet ist, daß der jewei­lige Stromausgang dieser steuerbaren Stromquellen (Is21, Is22, ...) an das Bezugspotential (Masse) angeschlossen ist, daß die Steuereingänge dieser steuerbaren Stromquellen (Is21, Is22, ...) als nichtinvertierende Eingangsklemmen (+y1, +y2, ...) vorgesehen sind, daß jeder Emitter des dritten Transistors (T3) mit je einem Emitter des vierten Transistors (T4) und dem Stromeingang einer jeweiligen steuerbaren Stromquelle (Is31, Is32, ...) zusammengeschaltet ist, daß der jeweilige Stromaus­gang dieser steuerbaren Stromquellen (Is31, Is32, ...) an das Bezugspotential (Masse) angeschlossen ist, und daß die Steuer­eingänge dieser steuerbaren Stromquellen (Is31, Is32, ...) als invertierende Eingangsklemmen (-y1, -y2, ...) vorgesehen sind.1. Four-quadrant multiplier in the form of a monolithically integrated electronic circuit, consisting of a first transistor (T1), the collector connection of which is connected to the collector connection of a third transistor (T3) and, via a first resistor (R1), of a supply potential (Uv) is connected and forms a signal output terminal (+ z), further consisting of a second transistor (T2), the collector connection of which is connected to the collector connection of a fourth transistor (T4) and is connected to the supply potential (Uv) via a second resistor (R2) and forms another signal output terminal (-z), the base connection of the first transistor (T1) being connected together with the base connection of the fourth transistor (T4) and the collector connection of a fifth transistor (T5) and the anode of a first diode (D1), wherein the base connection of the second transistor (T2) with the base connection of the third trans istors (T3) and the collector terminal of a sixth transistor (T6) and the anode of a second diode (D2) is connected together, the cathode of the first diode (D1) together with the cathode of the second diode (D2) via a third resistor (R3 ) is connected to the supply potential (Uv), the emitter connections of the fifth transistor (T5) and the sixth transistor (T6) being connected to one another via the series circuit comprising a fourth resistor (Rx1) and a fifth resistor (Rx2), the connecting node of these resistors (Rx1, Rx2) is connected to the reference potential (ground) via a first current source (I1) and the base terminal of the sixth transistor (T6) is the first input terminal (+ x) and the base terminal of the fifth transistor (T5) is the second Form the input terminal (-x) of the multiplier,
characterized,
that the first, second, third and fourth transistor (T1, T2, T3, T4) identical multiemitter transistors are provided in their structure, that each emitter of the first transistor (T1) with one emitter of the second transistor (T2) and the current input of a respective controllable current source (Is21, Is22, ...) is interconnected, that the respective current output of these controllable current sources (Is21, Is22, ...) is connected to the reference potential (ground) that the control inputs these controllable current sources (Is21, Is22, ...) are provided as non-inverting input terminals (+ y1, + y2, ...) that each emitter of the third transistor (T3) with one emitter of the fourth transistor (T4) and the Current input of a respective controllable current source (Is31, Is32, ...) is interconnected, that the respective current output of these controllable current sources (Is31, Is32, ...) is connected to the reference potential (ground), and that the control inputs of these controllable current sources ( Is31, Is32, ...) are provided as inverting input terminals (-y1, -y2, ...). 2. Vier-Quadranten-Multiplizierer nach dem Oberbegriff des Pa­tentanspruches 1,
dadurch gekennzeichnet,
daß als erster, als zweiter, als dritter und als vierter Tran­sistor (T1, T2, T3, T4) in ihrem Aufbau identische Multiemitter­transistoren vorgesehen sind, daß jeder Emitter des ersten Tran­sistors (T1) mit je einem Emitter des zweiten Transistors (T2) und dem Kollektor eines siebten oder weiteren Transistors (T71, T72, ...) zusammengeschaltet ist, daß jeder Emitter des dritten Transistors (T3) mit je einem Emitter des vierten Transistors (T4) und dem Kollektor eines achten oder weiteren Transistors (T81, T82, ...) zusammengeschaltet ist, daß der Emitter eines jeden mit seinem Kollektor an einen Emitter des ersten Transi­stors (T1) angeschlossenen Transistors (T71, T72, ...) über je einen Koppelwiderstand (Ry1, Ry2, ...) mit je einem Emitter ei­nes mit seinem Kollektor an einen Emitter des dritten Transi­stors (T3) angeschlossenen Transistors (T81, T82, ...) verbun­den ist, daß jeweils beide Anschlüsse eines jeden Koppelwider­standes (Ry1, Ry2, ...) über eine separate Konstantstromquelle (I21, I22, ..., I31, I32, ...) an das Bezugspotential (Masse) geschaltet sind, daß der Basisanschluß des siebten Transistors (T71) sowie die Basisanschlüsse der entsprechend geschalteten weiteren Transistoren (T72, ...) als Eingangsklemmen für nicht­invertierende Signaleingänge vorgesehen sind und daß der Basis­anschluß des achten Transistors (T81) sowie die Basisanschlüsse der entsprechend geschalteten weiteren Transistoren (T82, ...) als Eingangsklemmen für invertierende Signaleingänge vorgesehen sind.2. four-quadrant multiplier according to the preamble of claim 1,
characterized,
that as the first, second, third and fourth transistor (T1, T2, T3, T4) identical multi-emitter transistors are provided in their structure that each emitter of the first transistor (T1) with one emitter of the second transistor (T2) and the collector of a seventh or further transistor (T71, T72, ...) is connected together so that each emitter of the third transistor (T3) each has an emitter of the fourth transistor (T4) and the collector of an eighth or further transistor (T81, T82 , ...) is interconnected so that the emitter of each transistor (T71, T72, ...) connected with its collector to an emitter of the first transistor (T1) has a coupling resistor (Ry1, Ry2, ...) one emitter of a transistor (T81, T82, ...) connected to its collector to an emitter of the third transistor (T3) is connected so that both connections of each coupling resistor (Ry1, Ry2, ...) are connected via a separate constant current source le (I21, I22, ..., I31, I32, ...) are connected to the reference potential (ground), that the base connection of the seventh transistor (T71) and the base connections of the correspondingly connected further transistors (T72, ...) are provided as input terminals for non-inverting signal inputs and that the base connection of the eighth transistor (T81) and the base connections of the correspondingly connected further transistors (T82, ...) are provided as input terminals for inverting signal inputs. 3. Monolithisch integrierter Vier-Quadranten-Multiplizierer nach Anspruch 1,
dadurch gekennzeichnet,
daß die mit den invertierenden und nichtinvertierenden Ein­gangsklemmen (-y1, -y2, ...; +y1, +y2, ...) verbundenen steuer­baren Stromquellen (Is21, Is22, ...; Is31, Is32, ...) als ein- und ausschaltbare Konstantstromquellen ausgebildet sind und die durch die entsprechenden Eingangsklemmen (+y1, -y1; +y2, -y2; ...) gebildeten Signaleingänge zur Beaufschlagung mit rechteck­förmigen Signalen vorgesehen sind.3. A monolithically integrated four-quadrant multiplier according to claim 1,
characterized,
that the controllable current sources (Is21, Is22, ...; Is31, Is32, ...) connected to the inverting and non-inverting input terminals (-y1, -y2, ...; + y1, + y2, ...) as Constant current sources that can be switched on and off are formed and the signal inputs formed by the corresponding input terminals (+ y1, -y1; + y2, -y2; ...) are provided for the application of rectangular signals. 4. Monolithisch integrierter Vier-Quadranten-Multiplizierer nach Anspruch 1 oder 3,
dadurch gekennzeichnet,
daß mindestens alle nichtinvertierenden Eingangsklemmen (+y1, +y2, ...) außer der ersten Eingangsklemme (+x) jeweils mit ei­nem ersten Ausgang eines jeweiligen I²L-Gatters (G1, G2, ...) verbunden sind, daß mindestens alle invertierenden Eingangs­klemmen (-y1, -y2, ...) außer der zweiten Eingangsklemme (-x) jeweils mit dem das inverse Signal zum am ersten Ausgang be­reitgestellten Signal führenden zweiten Ausgang jeweils eines dieser I²L-Gatter (G1, G2, ...) ist und daß jeweils der Eingang dieser I²L-Gatter (G1, G2, ...) zur Beaufschlagung mit einem auf Bezugspotential bezogenen Rechtecksignal vorgesehen ist.4. Monolithically integrated four-quadrant multiplier according to claim 1 or 3,
characterized,
that at least all non-inverting input terminals (+ y1, + y2, ...) except the first input terminal (+ x) are each connected to a first output of a respective I²L gate (G1, G2, ...), that at least all inverting ones In addition to the second input terminal (-x), input terminals (-y1, -y2, ...) each have one of these I²L gates (G1, G2, ...) with the second output carrying the inverse signal to the signal provided at the first output. and that in each case the input of these I²L gates (G1, G2, ...) is provided for the application of a square wave signal related to the reference potential.
EP88114225A 1988-08-31 1988-08-31 Multi-input four quadrant multiplier Expired - Lifetime EP0356556B1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
AT88114225T ATE96558T1 (en) 1988-08-31 1988-08-31 MULTI-INPUT FOUR QUADRANT MULTIPLIER.
EP88114225A EP0356556B1 (en) 1988-08-31 1988-08-31 Multi-input four quadrant multiplier
ES88114225T ES2045047T3 (en) 1988-08-31 1988-08-31 MULTIPLIER WITH FOUR QUADRANTS OF MULTIPLE INPUTS.
DE88114225T DE3885280D1 (en) 1988-08-31 1988-08-31 Multi-input four-quadrant multiplier.
US07/393,607 US5115409A (en) 1988-08-31 1989-08-14 Multiple-input four-quadrant multiplier
JP1222781A JPH02113382A (en) 1988-08-31 1989-08-28 4 quadrant multiplier
DK426489A DK426489A (en) 1988-08-31 1989-08-30 MULTIINDGANGS-four-quadrant MULTIPLIER
PT91582A PT91582B (en) 1988-08-31 1989-08-30 MULTIPLICATOR OF FOUR QUADRANTS WITH VARIOUS TICKETS
FI894071A FI894071A7 (en) 1988-08-31 1989-08-30 FYRKVADRANTMULTIPLICERARE MED FLERE INGAONGAR.

Applications Claiming Priority (1)

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EP88114225A EP0356556B1 (en) 1988-08-31 1988-08-31 Multi-input four quadrant multiplier

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EP0356556A1 true EP0356556A1 (en) 1990-03-07
EP0356556B1 EP0356556B1 (en) 1993-10-27

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EP (1) EP0356556B1 (en)
JP (1) JPH02113382A (en)
AT (1) ATE96558T1 (en)
DE (1) DE3885280D1 (en)
DK (1) DK426489A (en)
ES (1) ES2045047T3 (en)
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PT (1) PT91582B (en)

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JPH02113382A (en) 1990-04-25
ATE96558T1 (en) 1993-11-15
ES2045047T3 (en) 1994-01-16
FI894071A7 (en) 1990-03-01
DK426489D0 (en) 1989-08-30
US5115409A (en) 1992-05-19
PT91582A (en) 1990-03-08
FI894071A0 (en) 1989-08-30
EP0356556B1 (en) 1993-10-27
PT91582B (en) 1995-07-18
DE3885280D1 (en) 1993-12-02
DK426489A (en) 1990-03-01

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