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EP0355243A1 - Dispositif de compteur de temps à haute capacité - Google Patents

Dispositif de compteur de temps à haute capacité Download PDF

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Publication number
EP0355243A1
EP0355243A1 EP88810591A EP88810591A EP0355243A1 EP 0355243 A1 EP0355243 A1 EP 0355243A1 EP 88810591 A EP88810591 A EP 88810591A EP 88810591 A EP88810591 A EP 88810591A EP 0355243 A1 EP0355243 A1 EP 0355243A1
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EP
European Patent Office
Prior art keywords
timer
tag
address
control block
storage location
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88810591A
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German (de)
English (en)
Inventor
Roy Dr. Want
Robin Dr. Williamson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to EP88810591A priority Critical patent/EP0355243A1/fr
Publication of EP0355243A1 publication Critical patent/EP0355243A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
    • G04G15/006—Time-pieces comprising means to be operated at preselected times or after preselected time intervals for operating at a number of different times

Definitions

  • a timer is understood to be a device which can be set to furnish an interrupt or a timeout indication, plus an identification of the timer, at a specific time instant or after a selected time interval.
  • the timer arrangement is particularly useful for communication systems in which protocols require the timed supervision of a very large number of simultaneously occuring tasks such as data transmissions over a network.
  • Timers can be implemented in several ways. Two common approaches are the following:
  • a register or storage place can be provided for each timer to be activated.
  • the timeout value i.e. a numeric value representing a time
  • the identity of the timer i.e. the event to which it is related, may be stored in a separate list which also keeps the addresses or names of the respective registers or storage places. All active timers are read out on a regular basis, and their contents is decreased to reflect the elapsed time; simultaneously, a test is made whether the new contents has reached a given value, e.g. zero. If this is the case, the timer is expired and with the aid of the list, the using system can be notified of the timeout, giving the identity of the respective event.
  • a given value e.g. zero
  • Another possibilty for implementing timers is to have a list of events for which a timeout is to be supervised, which list is ordered in the same sequence in which the timeouts will occur. For the first item in the list, an actual timer is provided which is temporarily associated with this list item and provides a signal or interrupt when the timeout actually occurs. Thereafter, the next item in the list can be then associated with the timer. There can be provided also a plurality (e.g. 4) of actual timers which are then associated with the respective number of leading items in the list.
  • time supervison arrangements are also given in the following patents: - U.S.Patent 3,451,520: Time-Sharing Arrangement.
  • - Discloses a time-sharing arrangement for a multiprocessing system in which there is provided a time-sharing queue which consists of component tasks from jobs presented to the system for execution and placed on the queue in chronological order.
  • a demand interrupt list is included which includes a list of time slots.
  • a first pointer is provided to indicate the current time slot in the list.
  • a second pointer is provided to indicate a slot in the list which is a chosen multiple of slots removed from the current slot. Further pointers are provided to indicate the oldest slots for tasks to be executed.
  • This arrangement is suitable for ensuring the timely handling of several tasks in a time-sharing system.
  • It is a primary object of the invention provide an arrangement by which a large number of timers can be simultaneously implemented.
  • Another object of the invention is to enable, in a multiple-timer arrangement, simple setting of timers and cancelling of timers.
  • a further object is a multiple-timer arrangement which can be increased in capacity by simple adding another storage module.
  • Another object of the invention is a method of operating a high-capacity timer device which simplifies the handling of timers, and which also allows the handling of multiple timers expiring at the same time.
  • the invention allows the implementation of several hundreds or even thousands of timers by providing a single high-capacity timer chip and a relatively simple software timer service in the host using the timer arrangement.
  • the time scale can be selected prior to usage of the timer by simple insertion of a time scale factor.
  • cancelling of active timers can be easily effected.
  • Another advantage is that the total time of the timer can be increased if required easily by adding another module to the timer RAM storage.
  • timers For effective operation of a program there should be available a number of timers which can each be set individually to a target time (timeout) and which, when the timer expires, interrupts the respective program and identifies the timer which has just expired.
  • a random access storage in which each location represents a time instant. All locations are accessed in a cyclic sequence, the address being provided by a counter which is sequentially incremented.
  • an identifier is provided as well as the timeout value in terms of the number of time increments of the advancing clock of the cyclic counter; the timer is established by generating an address which is the sum of the current cyclic counter value and the provided timeout value, and by entering the identifier into the thus addressed RAM location.
  • an interrupt is generated indicating a timer expiration, and the stored identifier is returned to the host or application program.
  • the High Capacity Timer (termed HCT in the following) is a peripheral unit, i.e. a special hardware unit which can be used to provide a large number of timers to an application program running on an associated processor (host processor).
  • the highlights of the High Capacity Timer architecture are: (a) minimal processor interaction, (b) flexible number of timers provided, (c) programmable resolution.
  • An adder 20 connected to the New Timer register (13) and to the Current Address Counter (19) for adding the contents of both.
  • a multiplexer 21 for selecting one of three possible address sources to be applied to the Timer RAM (Mux).
  • a register 23 to hold the value by which the master time clock is to be divided before being applied to the CAC (Time Scale).
  • a divider 25 for dividing a master clock signal by the contents of the Time Scale register, for providing local clock pulses (or "ticks") to the CAC (Clock Divider).
  • a detecting unit 27 for receiving data read from a RAM location and furnishing respective interrupt and tag signals (Active Timer Detect).
  • a logic unit 29 for directing the operation of the various HCT components under control of the master clock and received "external" control signals (Control Logic).
  • the HCT is interconnected with the host processor by:
  • the data bus and its branches are shown as solid lines, weheras the control lines ar shown as dotted lines.
  • the high capacity timer operates by sequencing through the address space of the RAM, i.e. all storage locations of the Timer RAM are accessed sequentially. When a location with non-zero contents is acessed, a timeout has occured and the host processor is interrupted and an identification (Timer Tag) is returned to the host processor. When the addressed location holds a zero word, then no timer has expired. Hence, setting a timer is performed by setting the contents of some particular storage location to a specific value. This value is the Timer Tag which is contained in the respective register 17 when a new timer is requested. The most significant bit of each timer RAM word should always be set to a logical '1' in order to prevent an error when the Timer Tag was selected to have the value zero. Thus, the number of possible tag values is equal to 2 (N-1) where N is the number of bit positions in each Timer RAM word (storage location).
  • the host processor can request the setting of a new timer and the cancelling of an existing (running) timer by two commands: SET TIMER and CANCEL TIMER.
  • the user processor In order to update, i.e. to change the target timeout, of a timer, the user processor must explicitly call the HCT twice: first to cancel the previous value and then to set the new value.
  • the user processor In order to set a timer, the user processor first loads the tag (identifier) to be associated with the timer into the Timer Tag register 17 by furnishing this tag to the data bus 31 and activating the Set Timer Tag control line 35G.It then loads the timeout value (i.e. a number indicating after how many time units or increments the timer should expire) into the New Timer register 13 by furnishing this value to the data bus 31 and activating the Set New Time control line 35B, and then activates the Set Timer control line (35D). This causes the address of the currently accessed RAM location (i.e. the CAC contents) to be added to the value held in the New Timer register.
  • the timeout value i.e. a number indicating after how many time units or increments the timer should expire
  • Timer Tag register The contents of the Timer Tag register is then written into Timer RAM at the location addressed by the resulting sum.
  • the value furnished by the CAC can be seen as representing the current time.
  • Each Timer RAM address/location can be seen as representing a future instant of time which is ahead of the current time by as many time units/increments as the current CAC contents and the respective Timer RAM address are apart.
  • the HCT In order to give the host processor a reference to the timer which has just been set, the HCT also gates the address of the new timer onto the host processor data bus 31 via the driver circuit 33. This value will be required if the user wishes to utilize the Cancel Timer facility.
  • the normal cycling/sequencing of the CAC contents is of course suspended during the setting of a new timer.
  • the cycle during which a new timer is set is interleaved into the normal incrementing operation of the CAC. Because the contents of the CAC is not altered by the Set Timer operation, the cycling through the Timer RAM addresses resumes at the point at which it was suspended. Hence, no timers are lost during a Set Timer operation.
  • the host processor In order to cancel a timer, the host processor must load the reference value received from the HCT at the time of setting the timer, into the Old Timer register 15 by furnishing this value to the data bus 31 and activating the Set Old Timer control line 35A. Then the host processor activates the Cancel Timer command line (35E). The HCT then uses the value stored in the Old Timer register as address to access a location of the Timer RAM. The contents of this location is set to zero, thereby cancelling the timer.
  • the resolution and maximum duration of the HCT are interrelated and depend on the frequency of the clock signal which is used to increment the Current Address Counter (CAC) and which is furnished on output line 37 of the Clock Divider 25, and on the depth (number of storage locations) of the Timer RAM.
  • CAC Current Address Counter
  • the resolution is defined as the period of the CAC clock signal on line 37.
  • the duration of the CAC clock period is derived from a master clock which is divided by the contents of the Time Scale register 23.
  • the master clock is either furnished by a master clock generator 39 in the HCT, or it is provided on a separate clock line from the host processor) .
  • a respective value is furnished to the data bus 31 and then the Set Time Scale control line 35C is activated.
  • the host processor can define the length of each timer tick (the value of the time increment) prior to using the HCT.
  • the user may utilize this function to "slow down" or "speed up” time.
  • the maximum timeout is proportional to Nram - 1 and not Nram because the Timer RAM location with address zero is not used (as was briefly explained above).
  • Timer RAM comprising 64 k word locations is considered.
  • the number of independent timers which the HCT can support is defined by the number of storage locations in the Timer RAM. In this example up to 65,535 independent timers can be supported.
  • the maximum duration of the HCT is ca. 32 seconds.
  • the minimum time between timeouts is the period of the CAC clock signal, i.e. 0.5 ms in this case.
  • the maximum duration can be increased, along with an increase in the minimum time between timeouts, by increasing the value in the Time Scale register 23.
  • the maximum timeout duration rises to ca. 8 minutes.
  • the minimum time between timeouts is 8 ms.
  • a software Timer Service STS is provided as interface between the application program in the host processor and the HCT.
  • STS Timer Service
  • the respective configuration is schematically shown in Fig.2.
  • control signals shown on the control lines in Fig.1 are now exchanged between the HCT and the Software Timer Service STS. Furthermore, data are exchanged between the HCT and the STS via the data bus 31. It is assumed that the width of this data bus as well as the width of the host processor data bus is the same as the width of the storage locations of the HCT (i.e., the control or data words can be exchanged in parallel).
  • the application program in the host processor can issue the two basic commands (which were introduced above) to the STS in the following form:
  • the STS Upon completion of the SET_TIMER command, the STS returns to the application program a reference. This is to be used should the application program want to cancel the timer.
  • timer_ref The reference returned by the STS when the timer was started (This may be the address of the Timer RAM location in which the data of the respective timer are stored)
  • the Software Timer Service STS provides a Timer Control Block (T-CB) for each timer which is active in the HCT.
  • T-CB Timer Control Block
  • Activity A bit indicating whether the status of the respective timer is active or inactive
  • the application program issues the SET_TIMER command to the STS, including the three parameters timer_id (T-ID), ticks, and notifier.
  • the STS allocates a Timer Control Block T-CB and enters the timer-id and the notification into the two respective fields of the new T-CB.
  • the STS issues in turn a SET_TIMER command to the HCT. It sends to the HCT the ticks value as the new_timer value (NEW-T) and the address of the new T-CB, i.e. ADR(T-CB) as Timer Tag. These two values are entered into the respective registers 13 and 17 of the HCT and are used for establishing (setting) the requested timer (d). Once the timer has been set, the HCT returns (e) to the STS the address of the Timer RAM location which has just been used for establishing the timer, ADR(T-RAM).
  • This address is inserted (f) by the STS into the "HCT_reference" field of the T-CB, and the activity bit in the T-CB is set to "1".
  • the SET_TIMER operation terminates when the STS returns (g) a timer_ref (T-REF) to the application program.
  • the value of this timer_ref is the address of the Timer Control Block, ADR(T-CB), in the Software Timer Service.
  • the application program stores (h) this timer reference for subsequent utilization (if necessary).
  • the HCT When the HCT detects that a timer has expired by determining that an addressed Timer RAM location is not empty, it interrupts the STS (i). During the interrupt acknowledge procedure (j) which was described above already, the STS receives (k) from the HCT the timer_tag stored in the Timer RAM; this is the address ADR(T-CB) of the Timer Control Block associated with the expired timer. The STS then accesses the T-CB (l) and notifies the application program that a timer has expired and returns (m) to the application program the timer_id (T-ID) from the T-CB (and a notifier if such was stored). The T-CB in the STS is then deallocated (n).
  • the application program wants to cancel the timer, it issues (p) the CANCEL_TIMER command to the STS, furnishing the timer_ref (T-REF) which is the address of the T-CB.
  • the STS can read (q) HCT_reference (which is the Timer RAM address of the respective timer) from the T-CB and it issues (r) in turn a CANCEL_TIMER command to the HCT, furnishing this address ADR(T-RAM) as the argument.
  • the respective Timer RAM location is set to zero, thereby cancelling the timer (t).
  • the T-CB is also deallocated (s) in the STS.
  • the STS operation occuring when multiple timers have the same expiration time is schematically illustrated in Fig.5.
  • the STS then activates the IntAck control line (e ⁇ ) as if it were interrupted due to a timer expiration, and will receive thereupon from the HCT (e′′′) the timer_tag stored at the RAM address just used, which is actually the RAM address ADR(T-RAM) of the existing older timer which is due to expire at the same time as the new timer which is just to be set.
  • the STS now chains (f′) the two control blocks, using the "Next_CB" field in the T-CB of the older timer and setting the "chained" flag in both T-CBs.
  • the chain of Timer Control Blocks can be extended as far as necessary, i.e. any number of timers can be associated with the same expiration time.
  • Fig.6 illustrates the contents of three Timer Control Blocks T-CB which are chained.
  • the three control blocks T-CB1, T-CB2, and T-CB3 are stored at locations 026, 084, and 113, respectively.
  • the first box in Fig.6 shows the initial contents of T-CB1, i.e. when it represents a single (unchained) timer. It contains a timer_id "abc", a notifier, the T_RAM address 207 (pointing to the RAM location where its own address 026 is stored as timer_tag), and a "1" in the activity status field.
  • the other two fields contain zeros indicating "no chaining".
  • T-CB1 now contains a Next_CB address 084 pointing to T-CB2, and indicates a chained status by a "1" in the last field.
  • T-CB2 has as Next_CB the address 113 of T-CB3, whereas T-CB3 contains a zero as Next_CB indicating that it is the last in the chain.
  • T-CB2 If one timer is to be cancelled, e.g. the one represented by T-CB2, only the activity status bit is set to zero (as indicated above the box) but nothing else is changed so that the whole T-CB chain is maintained (as described above already).

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP88810591A 1988-08-26 1988-08-26 Dispositif de compteur de temps à haute capacité Withdrawn EP0355243A1 (fr)

Priority Applications (1)

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EP88810591A EP0355243A1 (fr) 1988-08-26 1988-08-26 Dispositif de compteur de temps à haute capacité

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2665313A1 (fr) * 1990-07-24 1992-01-31 Cit Alcatel Procede d'evaluation du debit de circuits virtuels empruntant une voie de transmission a multiplexage temporel asynchrone.
EP0478008A2 (fr) * 1990-01-19 1992-04-01 Pierre Boyer Méthode et système de contrôle de débits de communications temporelles asynchrones
EP0525786A2 (fr) * 1991-08-02 1993-02-03 Canon Kabushiki Kaisha Dispositif de commande d'affichage
EP0586768A1 (fr) * 1992-09-11 1994-03-16 International Business Machines Corporation Compteur de temps multi-utilisateurs efficace
EP0657791A2 (fr) * 1993-12-09 1995-06-14 Pitney Bowes Inc. Dispositif de comptage de temps programmable dynamiquement
EP0660207A2 (fr) * 1993-12-09 1995-06-28 Pitney Bowes Inc. Temporisateur-compteur à deux modes
EP0723235A2 (fr) * 1995-01-23 1996-07-24 Tandem Computers Incorporated Temporisateur commandé par programme et méthode d'utilisation
EP0823080A1 (fr) * 1995-04-27 1998-02-11 Emulex Corporation Gestionnaire de rythmeurs
WO2002034002A1 (fr) * 2000-10-17 2002-04-25 Telefonaktiebolaget Lm Ericsson (Publ) Procede d'amelioration de la qualite de transmission entre une station mobile et une station de base par reglage selectif des valeurs de temporisation de retransmission
US9304536B2 (en) 2013-08-22 2016-04-05 International Business Machines Corporation Calibrated timeout interval on a configuration value, shared timer value, and shared calibration factor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079366A (en) * 1976-05-20 1978-03-14 Gim Wong Electronic timer and thermoswitch device
US4193120A (en) * 1978-09-13 1980-03-11 Zenith Radio Corporation Addressable event display and control system
JPS61130893A (ja) * 1984-11-30 1986-06-18 Nec Corp タイマ回路
US4677541A (en) * 1984-09-24 1987-06-30 Rauland-Borg Corporation Programmable clock

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079366A (en) * 1976-05-20 1978-03-14 Gim Wong Electronic timer and thermoswitch device
US4193120A (en) * 1978-09-13 1980-03-11 Zenith Radio Corporation Addressable event display and control system
US4677541A (en) * 1984-09-24 1987-06-30 Rauland-Borg Corporation Programmable clock
JPS61130893A (ja) * 1984-11-30 1986-06-18 Nec Corp タイマ回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 10, no. 324 (P-512)[2380], 5th November 1986; & JP-A-61 130 893 (NEC CORP.) 18-06-1986 *

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0478008A2 (fr) * 1990-01-19 1992-04-01 Pierre Boyer Méthode et système de contrôle de débits de communications temporelles asynchrones
EP0478008A3 (en) * 1990-01-19 1992-10-21 Pierre Boyer Method and system for monitoring the data rates of asynchronous time division communications
US5299191A (en) * 1990-01-19 1994-03-29 Pierre Boyer Method and a system of control of asynchronous time communication outputs
EP0472901A1 (fr) * 1990-07-24 1992-03-04 Alcatel Cit Procédé d'évaluation du débit de circuits virtuels empruntant une voie de transmission à multiplexage temporel asynchrone
AU647150B2 (en) * 1990-07-24 1994-03-17 Alcatel N.V. Method of evaluating data rates of virtual circuits
FR2665313A1 (fr) * 1990-07-24 1992-01-31 Cit Alcatel Procede d'evaluation du debit de circuits virtuels empruntant une voie de transmission a multiplexage temporel asynchrone.
EP0525786A2 (fr) * 1991-08-02 1993-02-03 Canon Kabushiki Kaisha Dispositif de commande d'affichage
EP0525786A3 (en) * 1991-08-02 1993-05-19 Canon Kabushiki Kaisha Display control apparatus
US5686934A (en) * 1991-08-02 1997-11-11 Canon Kabushiki Kaisha Display control apparatus
US5491815A (en) * 1992-09-11 1996-02-13 International Business Machines Corporation Method and device for controlling timers associated with multiple users in a data processing system
EP0586768A1 (fr) * 1992-09-11 1994-03-16 International Business Machines Corporation Compteur de temps multi-utilisateurs efficace
EP0660207A2 (fr) * 1993-12-09 1995-06-28 Pitney Bowes Inc. Temporisateur-compteur à deux modes
EP0657791A2 (fr) * 1993-12-09 1995-06-14 Pitney Bowes Inc. Dispositif de comptage de temps programmable dynamiquement
EP0657791A3 (fr) * 1993-12-09 1998-03-04 Pitney Bowes Inc. Dispositif de comptage de temps programmable dynamiquement
EP0660207A3 (fr) * 1993-12-09 1998-03-04 Pitney Bowes Inc. Temporisateur-compteur à deux modes
EP0723235A2 (fr) * 1995-01-23 1996-07-24 Tandem Computers Incorporated Temporisateur commandé par programme et méthode d'utilisation
EP0723235A3 (fr) * 1995-01-23 2004-01-07 Tandem Computers Incorporated Temporisateur commandé par programme et méthode d'utilisation
EP0823080A1 (fr) * 1995-04-27 1998-02-11 Emulex Corporation Gestionnaire de rythmeurs
EP0823080A4 (fr) * 1995-04-27 2000-03-22 Emulex Corp Gestionnaire de rythmeurs
WO2002034002A1 (fr) * 2000-10-17 2002-04-25 Telefonaktiebolaget Lm Ericsson (Publ) Procede d'amelioration de la qualite de transmission entre une station mobile et une station de base par reglage selectif des valeurs de temporisation de retransmission
US9304536B2 (en) 2013-08-22 2016-04-05 International Business Machines Corporation Calibrated timeout interval on a configuration value, shared timer value, and shared calibration factor
US9513660B2 (en) 2013-08-22 2016-12-06 International Business Machines Corporation Calibrated timeout interval on a configuration value, shared timer value, and shared calibration factor
US9513661B2 (en) 2013-08-22 2016-12-06 International Business Machines Corporation Calibrated timeout interval on a configuration value, shared timer value, and shared calibration factor

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