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EP0349392A1 - Numerischer Zeitgeber mit konstanter Auflösung - Google Patents

Numerischer Zeitgeber mit konstanter Auflösung Download PDF

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Publication number
EP0349392A1
EP0349392A1 EP89401768A EP89401768A EP0349392A1 EP 0349392 A1 EP0349392 A1 EP 0349392A1 EP 89401768 A EP89401768 A EP 89401768A EP 89401768 A EP89401768 A EP 89401768A EP 0349392 A1 EP0349392 A1 EP 0349392A1
Authority
EP
European Patent Office
Prior art keywords
counter
display
display points
output
counters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89401768A
Other languages
English (en)
French (fr)
Other versions
EP0349392B1 (de
Inventor
André Chovin
Jacques Taillebois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Avionics SAS
Original Assignee
Thales Avionics SAS
Crouzet SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Avionics SAS, Crouzet SA filed Critical Thales Avionics SAS
Publication of EP0349392A1 publication Critical patent/EP0349392A1/de
Application granted granted Critical
Publication of EP0349392B1 publication Critical patent/EP0349392B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/02—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques
    • G04G9/027—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques provided with means for displaying at will a time indication or a date or a part thereof
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F1/00—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers
    • G04F1/005—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers using electronic timing, e.g. counting means

Definitions

  • the present invention relates to the field of digital timers whose most common application is relay control.
  • An object of the present invention is to provide such a timer with an extended time range.
  • Another object of the present invention is to provide such a timer, the components of which can be produced essentially in the form of an integrated circuit.
  • Another object of the present invention is to provide a timer having a particularly simple display of the remaining time.
  • the present invention provides a digital timer with constant resolution comprising a clock and a chain of binary down counters each of which corresponds to a time range multiple of that of the previous down counter.
  • the binary outputs of the downcounters are sent in parallel to display points of a first set of display points, validation means being provided so that only the output of the most significant non-zero downcounter activates the points d display, and a display point of a second set of display points is associated with each down counter so that only the display point corresponds to the most significant non-zero down counter is actuated.
  • the binary downcounters are respectively a down counter by 16, at 4 bits, receiving clock pulses at 16 hertz and three down counters by 60, at 6 bits, receiving the output of the previous down counter, to provide counts of sixteenths of seconds, seconds, minutes, and hours, the first set of display points comprising six display points and the second set of display points comprising four display points.
  • a display point controlled to be active when all the down counters are at zero.
  • each down counter is associated with a memory which stores the set value of this down counter; each down-counter, except that of the highest rank to which is assigned a non-zero set value which is loaded at its set value, is initially loaded at its maximum value; each down-counter includes an end of down-count indication output which is used to validate the loading in the down-counter of immediately lower rank of the associated set value, to validate the connection of the binary outputs of this down-down down counter to the first set display points, and cause the display point of the second set associated with the down counter to be activated.
  • This timer revolves around a down count block 10 comprising for example four down counters 11, 12, 13 and 14.
  • This block 10 is associated with a time base 20 coupled to a quartz 21. There are quartz at low cost having a piezoelectric resonant frequency at 32,768 hertz. If the time base divides this frequency by 2048, 16 hertz signals are obtained at the output, that is to say that the first countdown module 11 receives pulses at a frequency of one sixteenth of a second. From there, we can choose that the down-counter 11 is a divider by 16 and the other down-counters 12, 13 and 14 are the dividers by 60.
  • the down-counter 11 will count 16ths of a second, the down-counter 12 of the seconds, the down-counter 13 of the minutes and the down-counter 14 of the hours.
  • an adjustment block 30 actuated for example by a set of push buttons 31 making it possible to fix in a preselection block 32 selected timer durations in hours, minutes, seconds and sixteenths of a second.
  • the information collected in this preselection block 32 will be supplied to a non-volatile memory block 33, consisting for example of EEPROM, NOVRAM, RAM saved by batteries or supercapacitors, etc.
  • a connection block 34 is provided in a conventional manner making it possible to directly couple the memory block to a bus connected to an external processor.
  • blocks 30 to 34 will not be described in more detail because they are relatively conventional and there are similar devices in other devices, for example digital clocks. It should only be remembered here that the information corresponding to the chosen delay time has been stored in non-volatile memories contained in block 33.
  • This block 33 can, as shown, be divided into word memories 33-1 33-2 33-3 and 33-4, respectively 4 bits for block 33-1 and 6 bits for blocks 33-2 at 33-4.
  • the total countdown output Z of the countdown block 10 is supplied to a function block 40 receiving an input from an input circuit 41, a power supply (also intended for the other blocks of the system during operation or initial adjustment) 42 , and an output circuit 43 providing a control signal intended for example to actuate an electro-mechanical or static relay.
  • the function block makes it possible to send start (PRESET) or reset (RESET) signals to the countdown block according to programs memorized in advance, as is conventional in the field of timers, for example to obtain that the timer only starts after a specific time or after the arrival of a particular input, that the output starts with a high or a low level, etc.
  • start (PRESET) or reset (RESET) signals to the countdown block according to programs memorized in advance, as is conventional in the field of timers, for example to obtain that the timer only starts after a specific time or after the arrival of a particular input, that the output starts with a high or a low level, etc.
  • the various blocks and in particular the countdown block 10 are connected to a display block 50 in which the display points consist of light-emitting diodes.
  • This display unit makes it possible to activate, in a manner which will be explained in more detail below, a first set of light-emitting diodes 51 which light up as a function of the state of the binary outputs of a particular down-counter. countdown block. Six diodes are shown here designated by “1", “2”, “4", “8”, "16”, “32”, for the case where the downcounters comprise six binary outputs.
  • a second set of light-emitting diodes 52 is provided so that one of its diodes is lit to indicate the down-counter whose value is displayed by block 51.
  • these diodes are marked “H”, “M”, “S” and “1/16” to show that they refer to each of the hours, minutes, seconds and 1 / 16th of a second counters respectively.
  • a diode 53 is provided to light up when all the downcounters are at zero (and possibly to flash during the adjustment phase).
  • a diode 54 reflects the start of the power supply and a diode 55 reflects the fact that the output is at high or low level.
  • the same diodes in the diode assembly 51 are used to indicate the time remaining during the operation of the timer.
  • the first display will translate the value 35 (LEDs "32", “2” and “1” lit) while that the diode 'H “of group 52 will be lit.
  • This duration in hours decreases while the down-counter 14 counts down.
  • the diode' H" of group 52 will go out while the "M “of this same group will light up and the value 30 will be displayed (LEDs 16, 8, 4 and 2) then this counting will be decremented until the countdown of the minute countdown timer 13 ends.
  • the 1/16 indicator of group 52 will light up and the display of its countdown will appear extremely quickly.
  • FIG. 2 very schematically shows in the form of blocks the coupling between the downcounters 11 to 14 and the diodes of the groups of diodes 51 and 52.
  • each downcounter is shown with only three binary outputs and therefore only three diodes in the diode group 51, these diodes being marked “1", “2” and “4".
  • the binary outputs Q2, Q1 and Q0 of each of the down counters 11 to 14 are connected via respective validation circuits 61 to 64 to the diodes "1", “2", "4" and logic circuits are provided to validate each of circuits 61 to 64 and activate the corresponding diode of group 52 only when the corresponding down-counter is the most significant down-counter whose output is non-zero. This is symbolized by the link between the zero crossing indication outputs (Z) of each of the downcounters and the blocks 61 to 64.
  • FIG. 3 shows in more detail an embodiment of the present invention and more precisely connections between the downcount block 10 and the memory 33 and display 50 blocks of FIG. 1. We take the case of the numerical examples of figure 1.
  • Each of the downcounters 11, 12, 13, 14 comprises: - six programming inputs D0 to D5 (four for the down-counter 11), - six binary down-counting outputs Q0 to Q5 (four for down-counter 11), - a Z output which is at low level (0) when a down-counter is programmed or is in the process of down-counting and which goes to high level (1) when the downcounter has completed its downcounting, if the CF input is itself at the high level, - a reset MR input, - a PE input allowing the programming of the down-counter to the value fixed by the inputs D0 to D5, - a CF input for programming the down-counter to its maximum value, and - a clock input CL.
  • the input CL of each of the downcounters is connected to the binary output of highest rank of the previous downcounter except for the downcounter 11 which receives the clock signal at 16 hertz.
  • the PE input of the highest rank down counter, the down counter 14, receives the PRESET signal from the function block (see FIG. 1).
  • the PE inputs of the other downcounters are connected to the output 7 of the downcounter of immediately higher rank by means of a circuit 70 for shaping pulses consisting of two inverters connected to each other by means of a differentiator.
  • All MR inputs of the downcounters are connected to the RESET input from the function block (see Figure 1) to allow resetting to zero.
  • the CF input of the highest-ranked down-counter is not connected and the CF inputs of the other down-counters are connected to the Z output of the next-highest down-counter.
  • the outputs Q0 to Q5 of the down counters 12, 13 and 14 and the outputs Q0 to Q3 of the down counter 11 are connected to the first set of light-emitting diodes 51, respectively "1" to "32", via validation circuits 61 to 64.
  • These circuits validation consist of controlled inverters as shown in Figure 3.
  • the control input of each of the validation blocks is connected to the output Z via an inverter 71 for the highest rank down counter and an ET 72 gate for the other down counters.
  • Each gate 72 receives on a first inverting input the output Z of the corresponding down-counter and on a second non-inverting input the output Z of the down-counter of immediately superior rank.
  • the output of the inverter 71 and those of each of the AND gates 72 are connected via inverters 73 to the respective light-emitting diodes, "H", “M”, “S”, “1 / 16 ", from the second group of diodes 52.
  • the LED for displaying the end of the downcounting of the whole of the downcounter block is connected to the output Z of the downcounter. lower row 11 by means of an inverter 74. This output Z of the down-counter 11 also corresponds to the output 80 of the down-count block.
  • memories 33-4 to 33-1 contain the values in hours, minutes, seconds and 16ths of a second chosen for the timer.
  • the down-counter start signal is supplied (the PRESET signal)
  • the down-counter 14 is loaded with the value of memory 33-4, the down-counters 11, 12 and 13 having a level 0 on their CF inputs, each of which is connected at the output Z of the previous down-counter so that these down-counters are loaded to their maximum value (60 for down-counters 12 and 13, and 16 for down-counter 11).
  • the downcounting of the downcounter 14 then occurs at the rate imposed by the preceding chain of downcounters, that is to say that this down-counter decrements its binary outputs by one unit every hour.
  • the group 52 light-emitting diode "H" is on and the group 51 light-emitting diodes reflect the time remaining in hours.
  • the passage to 1 of its output Z inhibits the input CF of the next down-counter and validates the input PE of this down-counter so that it is loaded at the value programmed in the corresponding memory.
  • the corresponding light-emitting diode of group 52 lights up and the diodes of group 51 progressively indicate the remaining time. The process is then repeated for the following down counters until a signal is supplied on the output 80 when the down counter 11 has completed its counting.
  • an advantage of the general organization of the structure according to the invention is that it requires a minimum number of memory points in order to keep programming information of a timer retentively.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)
EP89401768A 1988-06-27 1989-06-22 Numerischer Zeitgeber mit konstanter Auflösung Expired - Lifetime EP0349392B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8808718A FR2633406B1 (fr) 1988-06-27 1988-06-27 Minuterie numerique a resolution constante
FR8808718 1988-06-27

Publications (2)

Publication Number Publication Date
EP0349392A1 true EP0349392A1 (de) 1990-01-03
EP0349392B1 EP0349392B1 (de) 1993-02-03

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP89401768A Expired - Lifetime EP0349392B1 (de) 1988-06-27 1989-06-22 Numerischer Zeitgeber mit konstanter Auflösung

Country Status (4)

Country Link
US (1) US4928270A (de)
EP (1) EP0349392B1 (de)
DE (1) DE68904703D1 (de)
FR (1) FR2633406B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7562105B2 (en) * 2003-11-26 2009-07-14 Intel Corporation Methods and apparatus for generating a delay using a counter
CH698848B1 (de) * 2006-04-27 2009-11-13 Andreas Hieronymi Vorrichtung und Verfahren zur mobilen elektronischen Datenerfassung, -darstellung und -auswertung.
US20130128705A1 (en) * 2011-11-18 2013-05-23 John David Jones Devices for quantifying the passage of time
US8842499B2 (en) * 2011-11-18 2014-09-23 DS Zodiac, Inc. Devices for quantifying the passage of time

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3284715A (en) * 1963-12-23 1966-11-08 Rca Corp Electronic clock
US3750384A (en) * 1971-08-13 1973-08-07 A Miller Electric chronometer with binary readout
FR2312813A1 (fr) * 1975-05-30 1976-12-24 Casio Computer Co Ltd Montre a arret electronique
GB1505960A (en) * 1975-09-22 1978-04-05 Seiko Instr & Electronics Digital electronic timepieces
EP0009870A1 (de) * 1978-09-29 1980-04-16 Gulf And Western Industries, Inc. Zähler/Zeitgeber mit Schritt-Anzeige
FR2438863A1 (fr) * 1978-10-11 1980-05-09 Suisse Horlogerie Affichage sequentiel pour chronographe numerique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3943288A (en) * 1973-10-23 1976-03-09 Edgar D. Young Telephone incorporating binary coded decimal time display
US4564845A (en) * 1984-06-28 1986-01-14 Lambie Rosemary A Device to aid in the manual recordation of data

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3284715A (en) * 1963-12-23 1966-11-08 Rca Corp Electronic clock
US3750384A (en) * 1971-08-13 1973-08-07 A Miller Electric chronometer with binary readout
FR2312813A1 (fr) * 1975-05-30 1976-12-24 Casio Computer Co Ltd Montre a arret electronique
GB1505960A (en) * 1975-09-22 1978-04-05 Seiko Instr & Electronics Digital electronic timepieces
EP0009870A1 (de) * 1978-09-29 1980-04-16 Gulf And Western Industries, Inc. Zähler/Zeitgeber mit Schritt-Anzeige
FR2438863A1 (fr) * 1978-10-11 1980-05-09 Suisse Horlogerie Affichage sequentiel pour chronographe numerique

Also Published As

Publication number Publication date
DE68904703D1 (de) 1993-03-18
EP0349392B1 (de) 1993-02-03
FR2633406B1 (fr) 1990-11-02
FR2633406A1 (fr) 1989-12-29
US4928270A (en) 1990-05-22

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