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EP0165108B1 - Ultra-rapid time-numerical converter - Google Patents

Ultra-rapid time-numerical converter Download PDF

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Publication number
EP0165108B1
EP0165108B1 EP85400870A EP85400870A EP0165108B1 EP 0165108 B1 EP0165108 B1 EP 0165108B1 EP 85400870 A EP85400870 A EP 85400870A EP 85400870 A EP85400870 A EP 85400870A EP 0165108 B1 EP0165108 B1 EP 0165108B1
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EP
European Patent Office
Prior art keywords
signal
gates
chain
gate
time
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
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EP85400870A
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German (de)
French (fr)
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EP0165108A1 (en
Inventor
Jean-François Genat
François Rossel
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Centre National de la Recherche Scientifique CNRS
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Centre National de la Recherche Scientifique CNRS
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Priority to AT85400870T priority Critical patent/ATE41713T1/en
Publication of EP0165108A1 publication Critical patent/EP0165108A1/en
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the present invention relates to an ultra-fast time-to-digital converter, that is to say a device intended to supply a digital value representing the time elapsed between the reception of a start signal and the reception of a signal. stop.
  • the field of application of the invention is notably, but not exclusively, that of very short time measurement in nuclear electronics: high energy physics, nuclear physics, or nuclear medicine.
  • the converter according to the invention is particularly suitable for measuring the collection time intervals at the ends of particle detectors.
  • time-to-digital converters are essentially of two types.
  • the second are based on the use of reference clocks; they are also of complex structure and their precision is linked to that of the clock.
  • a converter of this type is described in document US-A-4,439,046.
  • the counter intended to count the clock signals between the start and stop signals is completed by a vernier circuit and using a delay line which receives the clock signals and which has several successive outputs connected to the clock inputs of flip-flops whose trigger and reset inputs receive the stop and start signals.
  • a time-digital converter comprising two delay lines receiving respectively the start signal and the stop signal. Each delay line has a plurality of outputs distributed regularly along the line. Circuits formed by flip-flops each have a first input connected to a particular output of the first delay line and a second input connected to the corresponding output of the second delay line. The propagation along the second delay line is faster than along the first, so that the position of the rocker in which the order of reception of the start and stop signals is reversed is representative of the duration to measure.
  • a ROM circuit receives the output signals from the flip-flops and processes the information sought in digital form.
  • the object of the present invention is to provide a time-to-digital converter having a simple structure enabling it to be produced in the form of an integrated circuit.
  • the present invention also aims to provide an ultra-fast time-digital converter, that is to say having a very short response time.
  • the present invention is based on the use, as a time reference, of the propagation times of logic signals in an integrated circuit.
  • the new integrated circuit technologies in the present case the manufacture of networks of prediffused doors, ensure, within the same sample, dispersions of the order of a few percent on sets of logical doors. several thousand units.
  • the measurement is carried out by inhibiting, following reception of the stop signal, the propagation of the start signal in a chain of doors.
  • This inhibition can be achieved in several ways.
  • the locking circuit comprises a second chain of doors which is formed on the same integrated circuit substrate and at one end of which the stop signal is received, the two chains forming paths parallel with connections between the doors of the first chain and the doors of the second chain so that the state of the doors of at least one of the two chains is locked when the starting signal propagating along the first chain and the stop signal propagating along the second chain met.
  • the configuration of the doors of the first chain, as well as possibly that of the doors of the second chain is representative of the time to be measured.
  • the converter is provided with coding means having inputs connected to the doors of minus one of the chains to provide a numerical measurement value depending on the state of these doors.
  • the directions of propagation of the start signal and the stop signal along the two parallel chains can be opposite to each other or identical. In the latter case, the propagation time through the doors of the first chain is greater than the propagation time through the doors of the second chain so that the stop signal can "catch up" with the starting signal.
  • the locking circuit comprises a set of paths each formed between a common input receiving the stop signal and a respective gate of the propagation chain of the start signal.
  • the stop signal is applied almost simultaneously to the different doors so that the state of the chain is frozen upon receipt of the stop signal.
  • Means for reading the state of the gates of the propagation chain of the starting signal are provided to provide a digital value representative of the time to be measured.
  • the converter according to the invention makes it possible to give the result of the measurement of very short times in an ultra-fast manner.
  • An additional advantage is that the converter can be implemented as an integrated circuit.
  • the converter of FIG. 1 comprises two chains of doors 10 and 15 similar, formed parallel to one another but with opposite directions of propagation.
  • the door chains are formed from a network of pre-diffused doors on the same integrated circuit substrate.
  • Each door 11 of the chain 10 has a first input connected to a non-inverting output of the previous door 11 and a second input connected to the inverting output of an associated door 16 of the chain 15.
  • the latter has a first input connected to the non-inverting output of the previous door 16 and a second input connected to the inverting output of the associated door 11.
  • Each door 11 is thus associated with a door 16, and vice versa.
  • the term "gate" is used here to designate a logic circuit through which an incoming signal may or may not be propagated depending on the state of a control signal which can also be received by this circuit.
  • a departure signal d is applied to the input end 12 of the door chain 10 in the form, for example, of a transition from low logic level to high logic level at an instant t1.
  • a stop signal is applied to the input end 17 of the door chain 15 also in the form of a transition from low logic level to high logic level at an instant t2.
  • the inputs 12 and 17 are located at opposite ends of the chains 10 and 15, the signals sd and sa propagating in opposite directions. Each time the signal sd crosses a door 11, the corresponding door 16 is blocked. Likewise, each time the signal sa passes through a door 16, the corresponding door 11 is blocked.
  • the coding circuit can be arranged to directly deliver a binary digital word giving on N bits a value proportional to At.
  • the least significant bit of the word supplied by the converter is worth 2 tp d .
  • the dispersion crtpd of the propagation times per integrated circuit gate must satisfy:
  • the maximum number N of significant bits that the converter can supply is such that: T being the value of the full scale of the converter.
  • the value of the least significant bit is here equal to 2 t Pd .
  • FIG. 2 illustrates another embodiment of a converter according to the invention with which the least significant bit has a value which can be less than the propagation time per gate.
  • the start signal sd is applied to the input end 22 of a first chain 20 of doors 21 similar to the chain 10 of the converter of FIG. 1.
  • the stop signal sa is applied to the end of input 27 of a second chain 25 of transmission doors 26.
  • Each door 26 is arranged to systematically transmit the signal which is present on its signal input, the latter being connected to its control input.
  • Each input of a door 26 is connected to an input of a door 23 whose inverting output is connected to an input of an associated door 21.
  • the other entry of this door 21 is connected to the non-inverting output of the previous door 21 while the other input of door 23 is connected to the inverting output of the associated door 21.
  • a door 26 is associated with each pair of doors 21-23.
  • the starting signal sd is applied to the input 22 at time t1 and propagates along the chain 20. It will be noted that the crossing of each door 21 by the signal sd is accompanied by the blocking of the associated door 23 .
  • the stop signal sa is applied to the input 27 at time t2 and propagates along the chain 25. The propagation along this chain is faster than that along the chain 20 so that the signal sa can catch up with the starting signal. As soon as the signal meets a door 23 which is not blocked, it passes through it so as to be able to block the corresponding door 21, thus blocking the propagation of the starting signal.
  • the signal sa continues to be propagated along the chain 25, successively blocking the doors of the chain 20 not crossed by the start signal.
  • the coding circuit 29 can be arranged to supply the number m in the form of a binary digital word.
  • the propagation time through the doors of a chain depends on several factors: number of doors connected at the output of each door of the chain, length of connections between doors, supply voltage of the circuit, ... In this case , one can play on one or more of these factors to have different propagation times t1 pd and t2p d such as: t1 pd > t2p d .
  • the gates 21, 23, 26 are formed from a network of prediffused gates on the same substrate and the difference in propagation time is obtained by varying the number of gates connected to each gate of a chain and on connection lengths.
  • the least significant bit of the word supplied by the converter is equal to t1 pd ⁇ t2 pd ; it can therefore take a value lower than tlp d and t2p d .
  • condition (1) With the dispersions ⁇ t1 pd and crt2pd on the propagation times, we find condition (1) with:
  • the pre-broadcast networks currently available have propagation times per gate less than a nanosecond and dispersions of less than a few tens of picoseondes.
  • the converter of FIG. 2 allows under these conditions a coding on 5 bits with a low weight equal to 500 ps and a full scale of 16 ns.
  • this is a common advantage to all of the embodiments of the invention, the result is available very quickly.
  • FIG. 2 also shows means for adjusting the converter.
  • each chain 20, 25 is connected a series of transmission doors, respectively 20a, 25a.
  • the starting signal is applied to an input terminal 22a which is connected to the input of a switching circuit 24, the outputs of which are connected to respective inputs of the doors 21a of the suite 20a.
  • the stop signal is applied to an input terminal 27a which is connected to the input of a switching circuit 28, the outputs of which are connected to respective inputs of the doors 26a of the sequence 25a.
  • Each switching circuit has a control input for selecting one of the outputs.
  • the zero adjustment is carried out by positioning the routing circuits so that the response of the converter is equal to zero when the signals sd and sa are applied simultaneously to the terminals 22a and 27a.
  • a decoding circuit 20b is arranged at the end of the chain 20 opposite to that of the input, this decoding circuit 20b having inputs connected to the non-inverting outputs of several doors 21.
  • the converter operating on N bits, the chain 20 comprises at least 2N gates 21.
  • the number of gates 21 is chosen a little greater than 2N, for example equal to 2N + k and the decoding circuit 20b receives the outputs of the 2k + 1 last doors in the chain.
  • the propagation time per gate, here tlp d is a function of the supply voltage of the integrated circuit.
  • the decoding circuit 20b is used to provide a control quantity for adjusting the supply voltage, so that the full scale is just reached when two reference signals sd and sa are applied with a time interval. equal to full scale, the coding circuit 29 being connected to the first 2N doors of the chain 21.
  • FIG. 3 illustrates another embodiment of a converter according to the invention in which the propagation of the starting signal in a chain of doors is stopped by the parallel blocking of the doors of the chain in response to the reception of the signal d 'stop.
  • the start signal sd is received at the input end 32 of a chain 30 of doors 31 while the stop signal sa is applied to a terminal 37 in parallel on the first door inputs 33 each associated with a respective door 31.
  • the connections of doors 31 and 33 are identical ticks to those of the gates 21 and 23 of the converter of FIG. 2, the gates 31 and 33 being formed on the same integrated circuit substrate from a network of prediffused gates.
  • each door 31 by the signal sd is accompanied by the blocking of the associated door 33.
  • the stop signal passes through the doors 33 not yet blocked to block the associated doors 31 and thus stop the propagation of the signal sd.
  • the state of the doors of the chain 30 is a linear function of the time interval At separating the instants t1 and t2 of reception of the signals sd and sa. This state is read directly from the non-inverting outputs of the gates 31 and converted into the form of a digital word by means of a coding circuit 39.
  • the least significant bit ⁇ t of the word supplied by the converter is equal to tp d , that is to say the propagation time per gate of the chain 30.
  • tp d the propagation time per gate of the chain 30.
  • condition (1) is weaker by a factor 2 112 than condition (1), because there is only one propagation in a single chain. However, an additional dispersion is introduced because the locking of the doors 31 of the chain 30 cannot be exactly simultaneous.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Gripping On Spindles (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)

Abstract

A chain of gates is formed on one and the same substrate of integrated circuit to enable the propagation along the chain of a starting signal received at one end of the chain, and a locking circuit formed for example by another chain of gates has outputs connected to the gates of the chain in order to be able to block the state thereof following the reception of a stop signal, so that the number of gates gone through by the starting signal is a linear function of the time elapsed between the reception of the starting signal and the reception of the stop signal.

Description

La présente invention concerne un convertisseur temps-numérique ultra-rapide, c'est-à-dire un dispositif destiné à fournir une valeur numérique représentant le temps écoulé entre la réception d'un signal de départ et la réception d'un signal d'arrêt.The present invention relates to an ultra-fast time-to-digital converter, that is to say a device intended to supply a digital value representing the time elapsed between the reception of a start signal and the reception of a signal. stop.

Le domaine d'application de l'invention est notamment, mais non exclusivement, celui de la mesure de temps très brefs en électronique nucléaire: physique des hautes énergies, physique nucléaire, ou médecine nùcléaire. A titre d'exemple, le convertisseur selon l'invention convient particulièrement à la mesure des intervalles de temps de collection aux extrémités de détecteurs de particules.The field of application of the invention is notably, but not exclusively, that of very short time measurement in nuclear electronics: high energy physics, nuclear physics, or nuclear medicine. By way of example, the converter according to the invention is particularly suitable for measuring the collection time intervals at the ends of particle detectors.

Les convertisseurs temps-numérique connus sont essentiellement de deux types.Known time-to-digital converters are essentially of two types.

Les premiers utilisent un condensateur qui est chargé à courant constant pendant la durée à mesurer, le niveau de charge étant ensuite numérisé, ces convertisseurs sont généralement précis, mais d'une structure complexe.The first use a capacitor which is charged at constant current for the duration to be measured, the charge level being then digitized, these converters are generally precise, but of a complex structure.

Les seconds sont basés sur l'utilisation d'horloges de référence; ils sont également de structure complexe et leur précision est liée à celle de l'horloge. Un convertisseur de ce type est décrit dans le document US-A-4 439 046. Dans ce convertisseur, le compteur destiné à compter les signaux d'horloge entre les signaux de départ et d'arrêt est complété par un circuit formant vernier et utilisant une ligne à retard qui reçoit les signaux d'horloge et qui a plusieurs sorties successives reliées aux entrées d'horloge de bascules dont les entrées de déclenchement et de réen- clenchement reçoivent les signaux d'arrêt et de départ.The second are based on the use of reference clocks; they are also of complex structure and their precision is linked to that of the clock. A converter of this type is described in document US-A-4,439,046. In this converter, the counter intended to count the clock signals between the start and stop signals is completed by a vernier circuit and using a delay line which receives the clock signals and which has several successive outputs connected to the clock inputs of flip-flops whose trigger and reset inputs receive the stop and start signals.

Il est par ailleurs connu du brevet US-A-4 433 919 un convertisseur temps-numérique comprenant deux lignes à retard recevant respectivement le signal de départ et le signal d'arrêt. Chaque ligne à retard a une pluralité de sorties réparties régulièrement le long de la ligne. Des circuits formés par des bascules ont chacun une première entrée reliée à une sortie particulière de la première ligne à retard et une deuxième entrée reliée à la sortie correspondante de la deuxième ligne à retard. La propagation le long de la deuxième ligne à retard est plus rapide que le long de la première, de sorte que la position de la bascule dans laquelle l'ordre de réception des signaux de départ et d'arrêt est inversé est représentative de la durée à mesurer. Un circuit ROM reçoit les signaux de sortie des bascules et élabore l'information recherchée sous forme numérique.It is also known from US-A-4,433,919 a time-digital converter comprising two delay lines receiving respectively the start signal and the stop signal. Each delay line has a plurality of outputs distributed regularly along the line. Circuits formed by flip-flops each have a first input connected to a particular output of the first delay line and a second input connected to the corresponding output of the second delay line. The propagation along the second delay line is faster than along the first, so that the position of the rocker in which the order of reception of the start and stop signals is reversed is representative of the duration to measure. A ROM circuit receives the output signals from the flip-flops and processes the information sought in digital form.

La présente invention a pour but de fournir un convertisseur temps-numérique ayant une structure simple permettant sa réalisation sous forme de circuit intégré. La présente invention a aussi pour but de fournir un convertisseur temps-numérique ultra-rapide, c'est-à-dire ayant un temps de réponse très bref.The object of the present invention is to provide a time-to-digital converter having a simple structure enabling it to be produced in the form of an integrated circuit. The present invention also aims to provide an ultra-fast time-digital converter, that is to say having a very short response time.

Ce but est atteint au moyen d'un convertisseur du type comprenant une ligne à retard destinée à être parcourue par le signal de départ et dans lequel, conformément à l'invention:

  • - la ligne à retard est formée par une pluralité de portes connectées en cascade pour former une chaîne dont une extrémité est destinée à recevoir le signal de départ pour permettre la propagation du signal de départ le long de la chaîne, les portes étant toutes constituées par des mêmes circuits intégrés formés sur un seul et même substrat semi-conducteur de manière à présenter sensiblement le même temps de propagation, chaque porte ayant une entrée de signal, une sortie de signal et une entrée de commande, ladite sortie de signal ayant un premier état lorsque le signal de départ s'est propagé à travers la porte correspondante ou un deuxième état différent du premier lorsque le signal de départ ne s'est pas propagé à travers la porte correspondante, et
  • - un circuit de verrouillage est prévu ayant une entrée destinée à recevoir le signal d'arrêt et une pluralité de sorties chacune reliée à une entrée de commande d'une porte correspondante de ladite chaîne, le circuit de verrouillage agissant en réponse à la réception d'un signal d'arrêt pour verrouiller les portes à travers lesquelles le signal de départ ne s'est pas encore propagé, de sorte que le nombre de portes traversées par le signal de départ et ayant par conséquent leur sortie de signal dans le deuxième état, est une fonction linéaire du temps écoulé entre la réception du signal de départ et la réception du signal d'arrêt.
This object is achieved by means of a converter of the type comprising a delay line intended to be traversed by the starting signal and in which, according to the invention:
  • the delay line is formed by a plurality of gates connected in cascade to form a chain, one end of which is intended to receive the starting signal to allow the propagation of the starting signal along the chain, the gates all being constituted by of the same integrated circuits formed on a single semiconductor substrate so as to have substantially the same propagation time, each gate having a signal input, a signal output and a control input, said signal output having a first state when the start signal has propagated through the corresponding door or a second state different from the first when the start signal has not propagated through the corresponding door, and
  • - a locking circuit is provided having an input intended to receive the stop signal and a plurality of outputs each connected to a control input of a corresponding door of said chain, the locking circuit acting in response to the reception of 'a stop signal to lock the doors through which the start signal has not yet propagated, so that the number of doors crossed by the start signal and therefore having their signal output in the second state , is a linear function of the time between reception of the start signal and reception of the stop signal.

La présente invention est basée sur l'utilisation, en tant que référence temporelle, des temps de propagation de signaux logiques dans un circuit intégré. En effet, les nouvelles technologies de circuits intégrés, dans le cas présent la fabrication de réseaux de portes prédiffusées, assurent, à l'intérieur d'un même échantillon, des dispersions de l'ordre de quelques pour cent sur des ensembles de portes logiques de plusieurs milliers d'unités.The present invention is based on the use, as a time reference, of the propagation times of logic signals in an integrated circuit. Indeed, the new integrated circuit technologies, in the present case the manufacture of networks of prediffused doors, ensure, within the same sample, dispersions of the order of a few percent on sets of logical doors. several thousand units.

La mesure est réalisée par l'inhibition, à la suite de la réception du signal d'arrêt, de la propagation du signal de départ dans une chaîne de portes.The measurement is carried out by inhibiting, following reception of the stop signal, the propagation of the start signal in a chain of doors.

Cette inhibition peut être réalisée de plusieurs façons.This inhibition can be achieved in several ways.

Selon un mode de réalisation préféré de l'invention le circuit de verrouillage comprend une deuxième chaîne de portes qui est formée sur un même substrat de circuit intégré et à une extrémité de laquelle est reçu le signal d'arrêt, les deux chaînes formant des trajets parallèles avec liaisons entre les portes de la première chaîne et les portes de la deuxième chaîne de sorte que l'état des portes d'au moins l'une des deux chaînes est verrouillé lorsque le signal de départ se propageant le long de la première chaîne et le signal d'arrêt se propageant le long de la deuxième chaîne se sont rencontrés. La configuration des portes de la première chaîne, de même, éventuellement, que celle des portes de la deuxième chaîne est représentative du temps à mesurer. Aussi, le convertisseur est-il muni de moyens de codage ayant des entrées reliées aux portes d'au moins l'une des chaînes pour fournir une valeur numérique de mesure fonction de l'état de ces portes.According to a preferred embodiment of the invention, the locking circuit comprises a second chain of doors which is formed on the same integrated circuit substrate and at one end of which the stop signal is received, the two chains forming paths parallel with connections between the doors of the first chain and the doors of the second chain so that the state of the doors of at least one of the two chains is locked when the starting signal propagating along the first chain and the stop signal propagating along the second chain met. The configuration of the doors of the first chain, as well as possibly that of the doors of the second chain is representative of the time to be measured. Also, the converter is provided with coding means having inputs connected to the doors of minus one of the chains to provide a numerical measurement value depending on the state of these doors.

Les sens de propagation du signal de départ et du signal d'arrêt le long des deux chaînes parallèles peuvent être inverses l'un de l'autre ou identiques. Dans ce dernier cas, le temps de propagation à travers les portes de la première chaîne est supérieur au temps de propagation à travers les portes de la deuxième chaîne afin que le signal d'arrêt puisse «rattraper» le signal de départ.The directions of propagation of the start signal and the stop signal along the two parallel chains can be opposite to each other or identical. In the latter case, the propagation time through the doors of the first chain is greater than the propagation time through the doors of the second chain so that the stop signal can "catch up" with the starting signal.

Selon un autre mode de réalisation de l'invention, le circuit de verrouillage comprend un ensemble de trajets formés chacun entre une entrée commune recevant le signal d'arrêt et une porte respective de la chaîne de propagation du signal de départ. Dans ce cas, le signal d'arrêt est appliqué de façon quasi-simultanée aux différentes portes de sorte que l'état de la chaîne est figé dès réception du signal d'arrêt. Des moyens de lecture de l'état des portes de la chaîne de propagation du signal de départ sont prévus pour fournir une valeur numérique représentative du temps à mesurer.According to another embodiment of the invention, the locking circuit comprises a set of paths each formed between a common input receiving the stop signal and a respective gate of the propagation chain of the start signal. In this case, the stop signal is applied almost simultaneously to the different doors so that the state of the chain is frozen upon receipt of the stop signal. Means for reading the state of the gates of the propagation chain of the starting signal are provided to provide a digital value representative of the time to be measured.

Dans tous les cas, le convertisseur conforme à l'invention permet de donner de façon ultra-rapide le résultat de la mesure de temps très brefs. Un avantage supplémentaire tient à ce que le convertisseur est réalisable sous forme de circuit intégré.In all cases, the converter according to the invention makes it possible to give the result of the measurement of very short times in an ultra-fast manner. An additional advantage is that the converter can be implemented as an integrated circuit.

D'autres particularités et avantages du convertisseur temps-numérique selon l'invention ressortiront à la lecture de la description faite ci-après, à titre indicatif mais non limitatif, en référence aux dessins annexés sur lesquels:

  • - la figure 1 est un schéma d'un convertisseur temps-numérique selon un premier mode de réalisation de l'invention,
  • - la figure 2 est un schéma d'un convertisseur temps-numérique selon un mode préféré de réalisation de l'invention, et
  • - la figure 3 est un schéma d'un convertisseur temps-numérique selon encore un autre mode de réalisation de l'invention.
Other particularities and advantages of the time-digital converter according to the invention will emerge on reading the description given below, by way of indication but not limitation, with reference to the appended drawings in which:
  • FIG. 1 is a diagram of a time-digital converter according to a first embodiment of the invention,
  • FIG. 2 is a diagram of a time-digital converter according to a preferred embodiment of the invention, and
  • - Figure 3 is a diagram of a time-to-digital converter according to yet another embodiment of the invention.

Le convertisseur de la figure 1 comporte deux chaînes de portes 10 et 15 similaires, formées parallèlement l'une à l'autre mais avec des directions de propagation opposées. Les chaînes de portes sont formées à partir d'un réseau de portes prédiffusées sur un même substrat de circuit intégré.The converter of FIG. 1 comprises two chains of doors 10 and 15 similar, formed parallel to one another but with opposite directions of propagation. The door chains are formed from a network of pre-diffused doors on the same integrated circuit substrate.

Chaque porte 11 de la chaîne 10 a une première entrée reliée à une sortie non-inverseuse de la porte 11 précédente et une seconde entrée reliée à la sortie inverseuse d'une porte 16 associée de la chaîne 15. Celle-ci a une première entrée reliée à la sortie non-inverseuse de la porte 16 précédente et une seconde entrée reliée-à la sortie inverseuse de la porte 11 associée. A chaque porte 11 est ainsi associée une porte 16, et réciproquement. On notera que le terme «porte» est utilisé ici pour désigner un circuit logique à travers lequel un signal entrant peut ou non être propagé selon l'état d'un signal de commande qui peut être reçu également par ce circuit.Each door 11 of the chain 10 has a first input connected to a non-inverting output of the previous door 11 and a second input connected to the inverting output of an associated door 16 of the chain 15. The latter has a first input connected to the non-inverting output of the previous door 16 and a second input connected to the inverting output of the associated door 11. Each door 11 is thus associated with a door 16, and vice versa. It will be noted that the term "gate" is used here to designate a logic circuit through which an incoming signal may or may not be propagated depending on the state of a control signal which can also be received by this circuit.

Un signal de départsd est appliqué à l'extrémité d'entrée 12 de la chaîne de portes 10 sous forme par exemple d'une transition de niveau logique bas à niveau logique haut à un instant t1. Un signal d'arrêt est appliqué à l'extrémité d'entrée 17 de la chaîne de portes 15 également sous forme d'une transition de niveau logique bas à niveau logique haut à un instant t2. Les entrées 12 et 17 sont situées à des extrémités opposées des chaînes 10 et 15, les signaux sd et sa se propageant en sens opposés. A chaque fois que le signal sd franchit une porte 11, la porte 16 correspondante est bloquée. De la même façon, à chaque fois que le signal sa franchit une porte 16, la porte 11 correspondante est bloquée. La rencontre des signaux sd et sa s'effectue en un point tel que le nombre de portes traversées par l'un deux est une fonction linéaire du temps recherché At = t2-t1. L'état des portes après la rencontre est figé. Il peut être lu immédiatement sur les sorties des portes de l'une des chaînes, par exemple sur les sorties non-inverseuses des portes 16, celles-ci étant reliées à un circuit de codage 19. Si l'on désigne par M le nombre total de portes dans chaque chaîne, par m le nombre de portes 11 franchies par le signal de départ, et par tpd le temps de propagation à travers une porte, l'on a At = tpd (2 m-M). Le circuit de codage peut être agencé pour délivrer directement un mot numérique binaire donnant sur N bits une valeur proportionnelle à At.A departure signal d is applied to the input end 12 of the door chain 10 in the form, for example, of a transition from low logic level to high logic level at an instant t1. A stop signal is applied to the input end 17 of the door chain 15 also in the form of a transition from low logic level to high logic level at an instant t2. The inputs 12 and 17 are located at opposite ends of the chains 10 and 15, the signals sd and sa propagating in opposite directions. Each time the signal sd crosses a door 11, the corresponding door 16 is blocked. Likewise, each time the signal sa passes through a door 16, the corresponding door 11 is blocked. The meeting of the signals sd and sa takes place at a point such that the number of gates crossed by one of them is a linear function of the sought time At = t2-t1. The condition of the doors after the meeting is frozen. It can be read immediately on the outputs of the doors of one of the chains, for example on the non-inverting outputs of doors 16, these being connected to a coding circuit 19. If we denote by M the number total of doors in each chain, by m the number of doors 11 crossed by the starting signal, and by tpd the time of propagation through a door, we have At = tpd (2 mM). The coding circuit can be arranged to directly deliver a binary digital word giving on N bits a value proportional to At.

Le bit de poids faible du mot fourni par le convertisseur vaut 2 tpd. Pour un convertisseur N bits dont le poids faible vaut δt et avec une précision absolue égale au demi-poids faible, la dispersion crtpd des temps de propagation par porte de circuit intégré doit satisfaire:

Figure imgb0001
The least significant bit of the word supplied by the converter is worth 2 tp d . For an N-bit converter whose least significant value is δt and with an absolute precision equal to the least significant half weight, the dispersion crtpd of the propagation times per integrated circuit gate must satisfy:
Figure imgb0001

L'on peut aussi montrer que pour une dispersion donnée, le nombre N de bits significatifs maximum que le convertisseur peut fournir, est tel que:

Figure imgb0002
T étant la valeur de la pleine échelle du convertisseur. La valeur du bit de poids faible est ici égale à 2 tPd. Une diminution de cette valeur en vue d'améliorer la précision ou la finesse de la mesure requiert une diminution du temps de propagation par porte.It can also be shown that for a given dispersion, the maximum number N of significant bits that the converter can supply, is such that:
Figure imgb0002
 T being the value of the full scale of the converter. The value of the least significant bit is here equal to 2 t Pd . A reduction in this value in order to improve the precision or the fineness of the measurement requires a reduction in the propagation time per gate.

La figure 2 illustre un autre mode de réalisation d'un convertisseur selon l'invention avec lequel le bit de poids faible a une valeur qui peut être inférieure au temps de propagation par porte.FIG. 2 illustrates another embodiment of a converter according to the invention with which the least significant bit has a value which can be less than the propagation time per gate.

Le signal de départ sd est appliqué à l'extrémité d'entrée 22 d'une première chaîne 20 de portes 21 analogue à la chaîne 10 du convertisseur de la figure 1. Le signal d'arrêt sa est appliqué à l'extrémité d'entrée 27 d'une deuxième chaîne 25 de portes 26 de transmission.The start signal sd is applied to the input end 22 of a first chain 20 of doors 21 similar to the chain 10 of the converter of FIG. 1. The stop signal sa is applied to the end of input 27 of a second chain 25 of transmission doors 26.

Chaque porte 26 est agencée pour transmettre systématiquement le signal qui se présente sur son entrée de signal, celle-ci étant reliée à son entrée de commande. Chaque entrée d'une porte 26 est reliée à une entrée d'une porte 23 dont la sortie inverseuse est connectée à une entrée d'une porte 21 associée. L'autre entrée de cette porte 21 est reliée à la sortie non-inverseuse de la porte 21 précédente tandis que l'autre entrée de la porte 23 est connectée à la sortie inverseuse de la porte 21 associée. Ainsi, une porte 26 est associée à chaque couple de portes 21-23.Each door 26 is arranged to systematically transmit the signal which is present on its signal input, the latter being connected to its control input. Each input of a door 26 is connected to an input of a door 23 whose inverting output is connected to an input of an associated door 21. The other entry of this door 21 is connected to the non-inverting output of the previous door 21 while the other input of door 23 is connected to the inverting output of the associated door 21. Thus, a door 26 is associated with each pair of doors 21-23.

Le signal de départ sd est appliqué à l'entrée 22 à l'instant t1 et se propage le long de la chaîne 20. On notera que le franchissement de chaque porte 21 par le signal sd s'accompagne du blocage de la porte 23 associée. Le signal d'arrêt sa est appliqué à l'entrée 27 à l'instant t2 et se propage le long de la chaîne 25. La propagation le long de cette chaîne est plus rapide que celle le long de la chaîne 20 de sorte que le signal sa puisse rattraper le signal de départ. Dès que le signal sa rencontre une porte 23 non bloquée, il passe à travers celle-ci pour pouvoir bloquer la porte 21 correspondante, bloquant ainsi la propagation du signal de départ. Le signal sa continue d'être propagé le long de la chaîne 25, bloquant successivement les portes de la chaîne 20 non franchies par le signal de départ. L'état des portes de la chaîne 20 est une fonction linéaire de At = t2-t1. Il peut être lu immédiatement sur les sorties non-inverseuses des portes 21, celles-ci étant reliées à un circuit de codage 29. Si l'on désigne par m le nombre de portes 21 franchies par le signal de départ, par tlpd le temps de propagation par porte de la chaîne 20 et par t2pd le temps de propagation par porte de la chaîne 25, l'on a At = m (tlpd-t2pd). Le circuit de codage 29 peut être agencé pour fournir le nombre m sous forme d'un mot numérique binaire.The starting signal sd is applied to the input 22 at time t1 and propagates along the chain 20. It will be noted that the crossing of each door 21 by the signal sd is accompanied by the blocking of the associated door 23 . The stop signal sa is applied to the input 27 at time t2 and propagates along the chain 25. The propagation along this chain is faster than that along the chain 20 so that the signal sa can catch up with the starting signal. As soon as the signal meets a door 23 which is not blocked, it passes through it so as to be able to block the corresponding door 21, thus blocking the propagation of the starting signal. The signal sa continues to be propagated along the chain 25, successively blocking the doors of the chain 20 not crossed by the start signal. The state of the doors of the chain 20 is a linear function of At = t2-t1. It can be read immediately on the non-inverting outputs of gates 21, these being connected to a coding circuit 29. If we denote by m the number of gates 21 crossed by the starting signal, by tlpd the time propagation by gate of the chain 20 and by t2p d the propagation time by gate of the chain 25, we have At = m (tlp d -t2p d ). The coding circuit 29 can be arranged to supply the number m in the form of a binary digital word.

Le temps de propagation à travers les portes d'une chaîne dépend de plusieurs facteurs: nombre de portes connectées en sortie de chaque porte de la chaîne, longueur des connexions entre portes, tension d'alimentation du circuit, ... En l'espèce, l'on peut jouer sur l'un ou plusieurs de ces facteurs pour avoir des temps de propagation t1pd et t2pd différents tels que: t1pd > t2pd. L'on pourrait disposer la chaîne de portes 21 avec les portes 23 associées sur un substrat de circuit intégré et la chaîne de portes 26 sur un autre substrat. Toutefois, de préférence, les portes 21, 23, 26 sont formées à partir d'un réseau de portes prédiffusées sur un même substrat et la différence de temps de propagation est obtenue en jouant sur le nombre de portes connectées à chaque porte d'une chaîne et sur les longueurs de connexion.The propagation time through the doors of a chain depends on several factors: number of doors connected at the output of each door of the chain, length of connections between doors, supply voltage of the circuit, ... In this case , one can play on one or more of these factors to have different propagation times t1 pd and t2p d such as: t1 pd > t2p d . One could arrange the door chain 21 with the associated doors 23 on an integrated circuit substrate and the door chain 26 on another substrate. However, preferably, the gates 21, 23, 26 are formed from a network of prediffused gates on the same substrate and the difference in propagation time is obtained by varying the number of gates connected to each gate of a chain and on connection lengths.

Le bit de poids faible du mot fourni par le convertisseur vaut t1pd―t2pd; il peut donc prendre une valeur inférieure à tlpd et t2pd. En ce qui concerne les dispersions σt1pd et crt2pd sur les temps de propagation, l'on retrouve la condition (1) avec:

Figure imgb0003
The least significant bit of the word supplied by the converter is equal to t1 pd ―t2 pd ; it can therefore take a value lower than tlp d and t2p d . Regarding the dispersions σt1 pd and crt2pd on the propagation times, we find condition (1) with:
Figure imgb0003

L'on retrouve également la relation (2) donnant le nombre de bits N.We also find the relation (2) giving the number of bits N.

Les réseaux prédiffusés disponibles actuellement présentent des temps de propagation par porte inférieurs à la nanoseconde et des dispersions inférieures à quelques dizaines de picose- condes. A titre indicatif, le convertisseur de la figure 2 permet dans ces conditions un codage sur 5 bits avec un poids faible égal à 500 ps et une pleine échelle de 16 ns. De plus, et c'est un avantage commun à tous les modes de réalisation de l'invention, le résultat est disponible très rapidement.The pre-broadcast networks currently available have propagation times per gate less than a nanosecond and dispersions of less than a few tens of picoseondes. As an indication, the converter of FIG. 2 allows under these conditions a coding on 5 bits with a low weight equal to 500 ps and a full scale of 16 ns. In addition, and this is a common advantage to all of the embodiments of the invention, the result is available very quickly.

Sur la figure 2 sont également représentés des moyens de réglage du convertisseur.FIG. 2 also shows means for adjusting the converter.

Pour le réglage du zéro, on connecte en amont de chaque chaîne 20, 25 une suite de portes de transmission, respectivement 20a, 25a. Le signal de départ est appliqué sur une borne d'entrée 22a qui est reliée à l'entrée d'un circuit d'aiguillage 24 dont les sorties sont reliées à des entrées respectives des portes 21a de la suite 20a. De même le signal d'arrêt est appliqué sur une borne d'entrée 27a qui est reliée à l'entrée d'un circuit d'aiguillage 28 dont les sorties sont reliées à des entrées respectives des portes 26a de la suite 25a. Chaque circuit d'aiguillage a une entrée de commande permettant de sélectionner une des sorties. Le réglage de zéro est effectué en positionnant les circuits d'aiguillage de manière que la réponse du convertisseur soit égale à zéro lorsque les signaux sd et sa sont appliqués simultanément aux bornes 22a et 27a.For zero adjustment, upstream of each chain 20, 25 is connected a series of transmission doors, respectively 20a, 25a. The starting signal is applied to an input terminal 22a which is connected to the input of a switching circuit 24, the outputs of which are connected to respective inputs of the doors 21a of the suite 20a. Likewise, the stop signal is applied to an input terminal 27a which is connected to the input of a switching circuit 28, the outputs of which are connected to respective inputs of the doors 26a of the sequence 25a. Each switching circuit has a control input for selecting one of the outputs. The zero adjustment is carried out by positioning the routing circuits so that the response of the converter is equal to zero when the signals sd and sa are applied simultaneously to the terminals 22a and 27a.

Pour le réglage de la pleine échelle, un circuit de décodage 20b est disposé à l'extrémité de la chaîne 20 opposée à celle d'entrée, ce circuit de décodage 20b ayant des entrées connectées aux sorties non-inverseuses de plusieurs portes 21. Le convertisseur fonctionnant sur N bits, la chaîne 20 comprend au moins 2N portes 21. En fait, le nombre de portes 21 est choisi un peu supérieur à 2N, par exemple égal à 2N + k et le circuit de décodage 20b reçoit les sorties des 2k + 1 dernières portes de la chaîne. Comme déjà indiqué, le temps de propagation par porte, ici tlpd est fonction de la tension d'alimentation du circuit intégré. Aussi, le circuit de décodage 20b est-il utilisé pour fournir une grandeur de commande de réglage de la tension d'alimentation, de manière que la pleine échelle soit juste atteinte lorsque deux signaux de référence sd et sa sont appliqués avec un intervalle de temps égal à la pleine échelle, le circuit de codage 29 étant relié aux 2N premières portes de la chaîne 21.For the adjustment of the full scale, a decoding circuit 20b is arranged at the end of the chain 20 opposite to that of the input, this decoding circuit 20b having inputs connected to the non-inverting outputs of several doors 21. The converter operating on N bits, the chain 20 comprises at least 2N gates 21. In fact, the number of gates 21 is chosen a little greater than 2N, for example equal to 2N + k and the decoding circuit 20b receives the outputs of the 2k + 1 last doors in the chain. As already indicated, the propagation time per gate, here tlp d is a function of the supply voltage of the integrated circuit. Also, the decoding circuit 20b is used to provide a control quantity for adjusting the supply voltage, so that the full scale is just reached when two reference signals sd and sa are applied with a time interval. equal to full scale, the coding circuit 29 being connected to the first 2N doors of the chain 21.

On notera que plusieurs réglages alternés du zéro et de la pleine échelle peuvent être nécessaires.Note that several alternating zero and full scale adjustments may be necessary.

Dans ce qui précède, on a envisagé le cas où la propagation du signal de départ dans une chaîne de portes est stoppée en étant rejointe par la propagation du signal d'arrêt dans une autre chaîne de portes.In the foregoing, we have considered the case where the propagation of the start signal in a chain of doors is stopped by being joined by the propagation of the stop signal in another chain of doors.

La figure 3 illustre un autre mode de réalisation d'un convertisseur selon l'invention dans lequel la propagation du signal de départ dans une chaîne de portes est stoppée par le blocage en parallèle des portes de la chaîne en réponse à la réception du signal d'arrêt.FIG. 3 illustrates another embodiment of a converter according to the invention in which the propagation of the starting signal in a chain of doors is stopped by the parallel blocking of the doors of the chain in response to the reception of the signal d 'stop.

Le signal de départ sd est reçu à l'extrémité d'entrée 32 d'une chaîne 30 de portes 31 tandis que le signal d'arrêt sa est appliqué sur une borne 37 en parallèle sur les premières entrées de portes 33 associées chacune à une porte 31 respective. Les connexions des portes 31 et 33 sont identiques à celles des portes 21 et 23 du convertisseur de la figure 2, les portes 31 et 33 étant formées sur un même substrat de circuit intégré à partir d'un réseau de portes prédiffusées.The start signal sd is received at the input end 32 of a chain 30 of doors 31 while the stop signal sa is applied to a terminal 37 in parallel on the first door inputs 33 each associated with a respective door 31. The connections of doors 31 and 33 are identical ticks to those of the gates 21 and 23 of the converter of FIG. 2, the gates 31 and 33 being formed on the same integrated circuit substrate from a network of prediffused gates.

Le franchissement de chaque porte 31 par le signal sd s'accompagne du blocage de la porte 33 associée. Le signal d'arrêt passe à travers les portes 33 non encore bloquées pour bloquer les portes 31 associées et arrêter ainsi la propagation du signal sd. L'état des portes de la chaîne 30 est une fonction linéaire de l'intervalle de temps At séparant les instants t1 et t2 de réception des signaux sd et sa. Cet état est lu directement sur les sorties non-inverseuses des portes 31 et converti sous forme d'un mot numérique au moyen d'un circuit de codage 39.The crossing of each door 31 by the signal sd is accompanied by the blocking of the associated door 33. The stop signal passes through the doors 33 not yet blocked to block the associated doors 31 and thus stop the propagation of the signal sd. The state of the doors of the chain 30 is a linear function of the time interval At separating the instants t1 and t2 of reception of the signals sd and sa. This state is read directly from the non-inverting outputs of the gates 31 and converted into the form of a digital word by means of a coding circuit 39.

Le bit de poids faible δt du mot fourni par le convertisseur vaut tpd, c'est-à-dire le temps de propagation par porte de la chaîne 30. Pour un convertisseur N bits de précision égale au demi-poids faible, la dispersion crtpd du temps de propagation tpd doit ici satisfaire la condition:

Figure imgb0004
The least significant bit δt of the word supplied by the converter is equal to tp d , that is to say the propagation time per gate of the chain 30. For an N-bit converter of precision equal to half the least significant, the dispersion crtpd of the propagation time tp d must satisfy the condition here:
Figure imgb0004

On notera que cette condition est moins forte d'un facteur 2112 que la condition (1), du fait qu'il y a une seule propagation dans une seule chaîne. Toutefois, une dispersion supplémentaire est introduite du fait que le verrouillage des portes 31 de la chaîne 30 ne peut être exactement simultané.It will be noted that this condition is weaker by a factor 2 112 than condition (1), because there is only one propagation in a single chain. However, an additional dispersion is introduced because the locking of the doors 31 of the chain 30 cannot be exactly simultaneous.

Claims (9)

1. Ultra-high speed time-to-digital converter, designed to supply a digital information representing the duration of the time interval between the time when a starting signal is received and the time when a stop signal is received and comprising a delay line designed to be gone through by the starting signal, characterized in that:
-the delay line is formed by a plurality of cascade-connected gates (11; 21; 31) forming a chain of which one end is designed to receive the starting signal in order to allow propagation of the starting signal along the chain, the gates being all constituted by the same integrated circuits formed on one and the same semi-conductor substrate, so as to present substantially the same propagation time, each gate having a signal input, a signal output and a control input, said signal output having a first condition when the starting signal is propagated through the corresponding gate or a second condition different from the first when the starting signal is not propagated through the corresponding gate, and
- a locking circuit (15; 23; 25; 33) is provided having an input designed to receive the stop signal and a plurality of outputs, each one being connected to a control input of a corresponding gate of said chain, said locking circuit acting in response to the reception of a stop signal, for locking the gates through which the starting signal is not yet propagated, so that the number of gates traversed through by the starting signal and consequently having their output signal in the second condition, is a linear function of the time which has elapsed between the time when the starting signal has been received and the time when the stop signal has been received.
2. Ultrahigh speed time-to-digital converter designed to supply a digital information representing the duration of the time interval between the time when a starting signal is received and the time when a stop signal is received, and comprising a delay line designed to be gone through by the starting signal, characterized in that:
- a plurality of first gates (11; 21) are cascade-connected in order to form a first chain of which one end is designed to receive the starting signal so as to allow propagation of the starting signal along the first chain, all the first gates being constituted by the same integrated circuits formed on one and the same semi-conductor substrate so as to present a substantially similar first propagation time, each first gate having a signal input and a signal output, said latter having a first condition when the starting signal is propagated through the first corresponding gate or a second condition different from the first when the starting signal is not propagated through the first corresponding gate,
- a plurality of second gates (16; 26) are cascade-connected in order to form a second chain of which one end is designed to receive the stop signal so as to allow the propagation of the stop signal along the second chain, all the second gates being constituted by the same integrated circuits formed on one and the same semi-conduc- . tor circuit, in such a way as to present a substantially similar propagation time, each gate having a signal input and a signal output, said signal output having a first condition when the stop signal is propagated through the second corresponding gate, or a second condition different from the first, when the stop signal is not propagated through the second corresponding gate,
- a plurality of locking circuits are each connected between a first respective gate and a second corresponding respective gate so as to cause the locking of the condition of the signal outputs of all the gates in one at least of the first and second chains when the starting signal and the stop signal which are propagated along the parallel paths constituted by the first and the second chains, reach at the same time a first and a second corresponding gates, and
- coding means (19, 29) are connected to the signal outputs of which the condition may be locked in order to supply a digital information which is function of the locked condition of said signal outputs.
3. Converter according to claim 2, characterized in that the first and second gates are formed on one and the same semi-conductor substrate.
4. Converter according to any one of claims 2 and 3, characterized in that the directions of propagation of the starting signal and stop signal along parallel paths formed by the first and second chains (10, 15) are opposite.
5. Converter according to claim 4, characterized in that each one of the first and second gates (11, 16) has a control input; and each locking circuit comprises a first connection connecting one output of the first corresponding gate (11) to the control input of the second corresponding gate (16) and a second connection connecting one output of the second corresponding gate (16) to the control input of the first corresponding gate (11) so as to control the locking of one gate of one chain by the passage of the signal output of the corresponding gate of the other chain from the first to the second condition.
6. Converter according to any one of claims 2 and 3, characterized in that the directions of propagation of the starting signal and of the stop signal along parallel paths formed by the first and second chains (20, 25) are identical, the first propagation time being longer than the second propagation time.
7. Converter according to claim 6, characterized in that each first gate (21) has a control input; and each locking circuit comprises a third gate (23) having a signal input connected to the signal output of the second corresponding gate (26), a control input connected to the signal output of the first corresponding gate (21) and a signal output connected to the control input of the first corresponding gate (21), so as to control the locking of a first gate (21) in response to the passage of the signal output of the second corresponding gate (26) from the first to the second condition only when the signal output of the first gate is still in the first condition.
8. Ultra-high speed time-to-digital converter designed to supply a digital information representing the duration of the time interval separating the time when a starting signal is received from the time when a stop signal is received and comprising a delay line designed to be gone through by the starting signal, characterized in that:
-the delay line is formed by a plurality of gates (31) which are cascade-connected to form a chain of which one end is designed to receive a starting signal in order to allow the propagation of the starting signal along the chain, the gates being all constituted by the same integrated circuits formed on one and the same semi-conductor substrate so as to have substantially the same propagation time, each gate having a signal input, a signal output and a control input, said signal output having a first condition when the starting signal is propagated through the corresponding gate or a second condition different from the first when the starting signal is not propagated through the corresponding gate,
- a plurality of locking circuits (33) are provided, each one having a signal input designed to receive a stop signal and a signal output connected to the control input of a respective corresponding gate, the locking circuits acting in response to the reception of a stop signal by locking the condition of the signal outputs of the gates, and
-coding means (39) are connected to the signal outputs of the gates (31) in order to supply a digital information which is function of the locked condition of said signal outputs.
9. Converter according to claim 8, characterized in that each locking circuit comprises a circuit of gates (33) having an input signal designed to receive the stop signal, a control input connected to a signal output of the corresponding gate (31) and a signal output connected to the control input of the corresponding gate (31), so as to control the locking of the corresponding gate in response to the reception of the stop signal only if the signal output of the corresponding gate is still in the first condition.
EP85400870A 1984-05-11 1985-05-06 Ultra-rapid time-numerical converter Expired EP0165108B1 (en)

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FR8407344A FR2564216B1 (en) 1984-05-11 1984-05-11 HIGH-SPEED TIME-TO-DIGITAL CONVERTER

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Also Published As

Publication number Publication date
JPS60253994A (en) 1985-12-14
DE3569049D1 (en) 1989-04-27
FR2564216B1 (en) 1986-10-24
FR2564216A1 (en) 1985-11-15
ATE41713T1 (en) 1989-04-15
EP0165108A1 (en) 1985-12-18
US4719608A (en) 1988-01-12

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