EP0161966B1 - Method of and device for transcoding colours allowing the interconnection of two devices and a different colour definition - Google Patents

Abstract

PCT No. PCT/FR85/00088 Sec. 371 Date Dec. 10, 1985 Sec. 102(e) Date Dec. 10, 1985 PCT Filed Apr. 16, 1985 PCT Pub. No. WO85/04977 PCT Pub. Date Nov. 7, 1985.A process and apparatus for connecting the color coding of one equipment to another equipment. The position of the color of character Cc of the first equipment in the interval Ci-Ci+1 of two successive colors of the second equipment and the position of the background color Cf in the interval Cj-Cj+1 are determined. As a function of these positions, the character color is taken either as Ci, or as Ci+1. The background color is taken either as Cj or Cj+1.

Description

The subject of the present invention is a method for transcoding colors and a corresponding transcoder.

• - d'une part, un équipement d'entrée comprenant une mémoire de page dont le contenu est apte à définir une image du type mosaïque formée de caractères définis chacun par une forme, une couleur de caractère, une couleur de fond et divers autres attributs, les couleurs de caractères et de fond étant prises dans un groupe qui en comprend N; avec
• - d'autre part, un équipement de sortie comprenant un moyen d'affichage d'image du type mosaïque à l'aide de caractères ayant eux aussi une forme, une couleur de caractère et une couleur de fond, les couleurs de caractère et de fond étant prises dans un groupe qui en comprend M, le nombre M étant inférieur à N.

The invention makes it possible to connect:

• - on the one hand, an input device comprising a page memory whose content is capable of defining an image of the mosaic type formed of characters each defined by a shape, a character color, a background color and various other attributes , the character and background colors being taken from a group comprising N; with
• - on the other hand, an output device comprising a means of image display of the mosaic type using characters also having a shape, a character color and a background color, the character colors and background being taken from a group which includes M, the number M being less than N.

The field of application of the invention is vast. It covers in particular videography which is, as we know, a telecommunication method making it possible to present alphanumeric or graphic messages to a user on a display screen. In its broadcast variant, this process is often designated by "teletext" and in its interactive variant by "videotex". The invention can also be applied to the field of computers or microcomputers, as well as to that of printers, and various display devices such as flat screens.

The problem which the invention proposes to solve is a problem of incompatibility between equipment working with a different number of colors. This is the case, for example, when you want to display an eight-color videography image on a two-color flat screen, or when you want to couple a high-definition microcomputer using 64 colors to an 8-color printer , etc ...

Figures 1 and 2 illustrate the place occupied by the transcoder of the invention in known installations with two incompatible devices. In FIG. 1, the transcoder TR is killed between an EQE input equipment and an EQS output equipment. Figure 2 shows how this same transcoder fits into a videography chain which includes a central processing unit UCT, a page memory MP, a UV display unit and a television receiver RT. The transcoder is then inserted between the page memory MP and the UV display unit and it allows the control of an EQS output device.

The invention applies in the case where the images to be processed are images of the mosaic type. We know that such images are made up of characters, each character being included in a matrix. The mosaic image consists of a grid (row, column) of such matrices, these being arranged contiguously both horizontally and vertically. The characters are either alphanumeric or graphic. Figure 3 shows an alphanumeric character (in this case the letter A). Such a character is defined by a form F, by the color of the character, ie Cc, (this color being shown diagrammatically by inclined stripes) and by the background color, ie Cf (diagrammed by dotted lines). Certain other attributes of the character can be added to the two preceding ones (such as for example the blinking, the height, the width etc ...). As for the graphic characters, examples will be described later, with reference to FIGS. 9a and 9b.

For certain output devices that only have two colors (this is the case with certain printers or flat screens), the background color is necessarily that of the medium used (paper in the first case and screen in the second) and the Character color must be that of the ribbon ink (for the printer) or that of the excited material (for the screen). If the screen is liquid crystal, the background of the screen is usually bright and the character is dark. With a CRT screen, the background is usually dark and the character bright.

These examples suggest that, thereafter, there will frequently be an inversion operation (translated by a binary signal denoted I) which will make it possible to pass from a display mode to the complementary mode, (such as for example of a character shiny on a black background or black on a light background).

The principle of the invention is first of all to establish a correspondence table between the N colors of the input equipment and the M colors of the output equipment. If we denote by K0, K1, ..., KN-2, KN-1 the N colors of the input equipment, we can arrange these colors in a certain order. As, in practice, the color information is coded by binary words, this amounts to arranging such words. Figure 4, on its left side, shows the N colors in question as horizontal lines.

For example, for a group of N = 8 colors, we can adopt the following classification, which is based on a growth in luminance:

But we can rely on other criteria to rank N colors. In addition, it is convenient to work with groups of colors which contain a number of colors equal to an exact power of 2 N = 2n (in the example considered above, we have N = 23). The number of binary elements, or bits, of the words translating the colors is then equal to n (3 in the previous example). But the invention is not limited to this one case, of course.

It will be observed that the digital code chosen is not necessarily the color code used for the display on a screen of the color television type, such as the screen RT of FIG. 2.

The correspondence table to be established must make it possible to associate with each of the N colors K0, K1, ..., KN-1, one of the M colors C0, C1, ..., CM-2, CM-1 of the output equipment. It is therefore necessary to establish, in the same way, a second color scale with these M colors. Since M is, hypothetically, less than N, the two scales do not coincide. This second scale is represented in the middle part of FIG. 4.

Assuming that the number M is also an exact power of 2, ie 2 ^m , each color C can be associated with a word of m bits. The number m is less than n.

In general, the extreme colors CO and CM-1 are black and white, so it makes sense to match KO to CO and KN-1 to CM-1. The transcoding between a color K and a color C therefore only really arises for the intermediate colors.

According to the invention, the transcoding operation will consist of processing on the binary words associated with each of the colors of the two families. As these words do not have the same number of bits (the N colors are associated with words of n bits and the M colors with words of m bits), these are first completed by n-m least significant bits. For Co, which includes m bits equal to zero, it goes without saying that the word will be completed with n-m other bits equal to 0 to obtain a word identical to that which characterizes K0. To the input Ko color, we will therefore immediately match the output Co color. For CM-1, which includes m times bit 1, the word will be completed with n-m least significant bits equal to 1, which will give an n-bit word identical to that of KN-1. For the intermediate colors one will supplement the words of m bits by bits equal to 0 or 1, according to the colors in question, while endeavoring to make coincide the intermediate colors common to both systems.

A character to be displayed is defined by a character color Cc, taken from among the N colors K0, ..., KN-1 and a background color Cf, taken from the same colors. The color Cc can moreover be identical to the color Cf, in which case it is a question of displaying a uniform space. The problem amounts to attributing to Cc and Cf two colors taken from the m colors C0, ..., CM-1.

In general, Cc does not coincide with one of these colors, but falls between two colors, which we will denote respectively Ci and Ci +1, the index i being a number between 0 and M-2.

Likewise Cf does not necessarily coincide with one of the colors of the output equipment, but falls between two colors Cj and Cj + 1. the index j also being a number between 0 and M-2.

Of course, in some cases, i and j can be equal.

The invention makes it possible to choose between the colors Ci and Ci + for the character color Cc and between Cj and Cj + for the background color.

The correspondence between a color and a binary word being thus well defined, the notations Cc, Cf, Ci, Cj etc ... will designate thereafter as well colors as the numerical words translating them.

• - pour chaque caractère défini par les mots Cc et Cf, on détermine la plage Ci-Cj + dans laquelle se situe le mot Cc, et la plage Cj-Cj + dans laquelle se trouve le mot Cf,
• - on fait correspondre à la couleur Cc soit la couleur Ci, soit la couleur Ci + 1 et a la couleur Cf soit la couleur Cj, soit la couleur Cj+1, le choix dans cette double alternative, étant fixé selon les critères suivants: on compare d'abord les mots Cf et Cc:
  • A) si le mot Cc n'est pas égal au mot Cf, alors la forme du caractère n'est pas modifiée et l'on compare le mot Ci au mot Cj pour déterminer si Ci est égal à Cj ou si Ci n'est pas égal à Cj,
    Aa) si Ci n'est pas égal à Cj: Aa1) on détermine quelle est la plus petite des deux différences Cf-Cj et Cj+1-Cf; si Cf-Cj est la plus petite différence, alors on choisit pour Cf la couleur Cj; dans le cas contraire, on choisit pour Cf la couleur Cj + 1, Aa2) on détermine quelle est la plus petite des différences Cc-Ci et Ci + 1-Cc; si Cc-Ci est la plus petite différence alors on choisit pour Cc la couleur Ci; dans le cas contraire, on choisit pour Cc la couleur Ci + 1,
    Ab) si le mot Ci est égal au mot Cj: on détermine si Cf est inférieur à Cc; dans l'affirmative, on choisit pour Cf la couleur Ci et pour Cc la couleur Ci + 1; dans la négative, on choisit pour Cf la couleur Ci + 1 et pour Cc la couleur Ci;
  • B) si le mot Cf est égal au mot, Cc, la forme du caractère est identique au fond et la couleur de cet espace est prise égale à l'une des couleurs Ci et Ci + 1.

The transcoding method of the invention is then characterized by the fact that it comprises the following operations:

• - for each character defined by the words Cc and Cf, the range Ci-Cj + in which the word Cc is located, and the range Cj-Cj + in which the word Cf is located,
• - we make the color Cc correspond to the color Ci, or the color Ci + 1 and to the color Cf either the color Cj, or the color Cj + 1, the choice in this double alternative, being fixed according to the following criteria: we first compare the words Cf and Cc:
  • A) if the word Cc is not equal to the word Cf, then the shape of the character is not modified and the word Ci is compared to the word Cj to determine whether Ci is equal to Cj or if Ci is not not equal to Cj,
    Aa) if Ci is not equal to Cj: Aa1) we determine which is the smaller of the two differences Cf-Cj and Cj + 1-Cf; if Cf-Cj is the smallest difference, then we choose for Cf the color Cj; otherwise, the color Cj + 1, Aa2 is chosen for Cf), which is the smallest of the differences Cc-Ci and Ci + 1-Cc; if Cc-Ci is the smallest difference then the color Ci is chosen for Cc; otherwise, the color Ci + 1 is chosen for Cc,
    Ab) if the word Ci is equal to the word Cj: we determine if Cf is less than Cc; if so, the color Ci is chosen for Cf and the color Ci + 1 for Cc; in the negative, the color Ci + 1 is chosen for Cf and the color Ci for Cc;
  • B) if the word Cf is equal to the word, Cc, the shape of the character is identical to the background and the color of this space is taken equal to one of the colors Ci and Ci + 1.

On the right-hand side of FIG. 4 are represented, in the most general way, the intervals which intervene in the process of choice which has just been defined. This representation makes it possible to understand that one seeks, among the M colors of the second group, that which "comes closest" to the initial color.

As each color is associated with a binary word, the choice can be determined by placing implementation of a decision algorithm which relates to the words in question. Graphically, the operations previously described are translated as shown in FIG. 5 where the double rectangles represent results and the hexagons of the tests.

If the first comparison test between Cf and Cc leads to a negative result (Cf is different from Cc), this means that the shape of the character is determined by the word F taken from the page memory. If the result is positive (Cf = Cc), this means that there is not strictly speaking a character distinguished by its color from the background. In other words, the shape fills the entire space of the mosaic matrix. The choice of color is then arbitrary. It can be fixed on Ci + (this is what is indicated in figure 5, rectangle in bottom on the left). But we can also decide to choose the "lower" color Ci.

The present invention also relates to a transcoder which implements the method which has just been defined.

• - les figures 1 et 2 déjà décrites, montrent la place occupée par le transcodeur de l'invention,
• - la figure 3, déjà décrite, montre un caractère alphabétique,
• - la figure 4, déjà décrite, illustre la mise en correspondance de deux échelles de couleurs,
• - la figure 5, déjà décrite, est un organigramme expliquant le processus de choix des couleurs de sortie,
• - les figures 6a et 6b, montrent le schéma synoptique du transcodeur de l'invention,
• - les figures 7a et 7f montrent un exemple de réalisation d'un transcodeur dans le cas d'un équipement d'entrée à 2ⁿ couleurs et d'un équipement de sortie à 2_m couleurs,
• - la figure 8 est un chronogramme expliquant le fonctionnement du transcodeur précédent,
• - les figures 9a et 9b montrent la structure des caractères graphiques,
• - la figure 10 est un algorithme montrant comment s'insère un test d'inversion dans la variante des figures 7a à 7f,
• - la figure 11 illustre la structure des moyens correspondant au cas précédent,
• - la figure 12 montre un esemble de caractères avec une zone non inversable et une zone inversable,
• - la figure 13 est un organigramme illustrant le processus de décision dans le cas de l'application au vidéotex à 16 bits,
• - les figures 14a à 14f illustrent un mode de réalisation du transcodeur correspondant au cas précédent,
• - la figure 15 est un chronogramme expliquant le fonctionnement du transcodeur.

The principle of the invention having been explained, various embodiments will now be described to specify some practical methods of implementation. This description refers to attached drawings in which:

• FIGS. 1 and 2, already described, show the space occupied by the transcoder of the invention,
• FIG. 3, already described, shows an alphabetical character,
• FIG. 4, already described, illustrates the matching of two color scales,
• FIG. 5, already described, is a flow chart explaining the process for choosing the output colors,
• FIGS. 6a and 6b show the block diagram of the transcoder of the invention,
• FIGS. 7a and 7f show an exemplary embodiment of a transcoder in the case of input equipment with 2 ⁿ colors and output equipment with 2 _m colors,
• FIG. 8 is a timing diagram explaining the operation of the preceding transcoder,
• FIGS. 9a and 9b show the structure of the graphic characters,
• FIG. 10 is an algorithm showing how an inversion test is inserted in the variant of FIGS. 7a to 7f,
• FIG. 11 illustrates the structure of the means corresponding to the previous case,
• FIG. 12 shows a set of characters with a non-invertible zone and a reversible zone,
• FIG. 13 is a flow diagram illustrating the decision process in the case of application to 16-bit videotex,
• FIGS. 14a to 14f illustrate an embodiment of the transcoder corresponding to the previous case,
• - Figure 15 is a timing diagram explaining the operation of the transcoder.

In all that follows, the various organs, circuits and other components shown will be referenced using a number of which one hundred will be that of the assembly to which it belongs in the general representation of FIGS. 6a and 6b. For example, a circuit referenced 1002 will belong to block 1000; a circuit 903 will belong to block 900, etc. If a means described does not strictly fall within one of the blocks of FIGS. 6a and 6b (as will be the case for example of a connection between two blocks or an additional component), this means will have a numerical reference less than 100.

• - un ensemble de registres d'entrée 100 reliés par un bus à la mémoire de page de l'équipement d'entrée; ces registres sont aptes à mémoriser des données numériques correspondant aux divers caractères à afficher; cet ensemble comprend notamment un registre 101 mémorisant un bit d'inversion I, un registre 102 mémorisant le mot de n bits correspondant à la couleur de caractère Cc, un registre 103 mémorisant le mot de n bits correspondant à la couleur de fond Cf, un registre 104 mémorisant divers attributs A et un registre 105 mémorisant le mot définissant la forme du caractère;
• - un premier comparateur 200 possédant deux entrées reliées respectivement aux deux registres d'entrée 102, 103 d'où elles reçoivent les mots Cc et Cf, et trois sorties 3, 1 et 4 dont l'état binaire indique si Cc est respectivement inférieur, égal ou supérieur à Cf,
• - une mémoire morte 1000 contenant les M mots Co, C1, ..., CM-1 de m bits correspondant aux M couleurs de l'équipement de sortie, ces mots étant complétés à n bits comme indiqué plus haut et rangés dans un ordre déterminé, chaque mot étant adressable dans la mémoire par un indice (i ou j) définissant le rang du mot; on verra plus loin que cette mémoire comprend 4 mémoires mortes 1001, 1002, 1003, 1004;
• - un premier sous-ensemble 300 permettant de déterminer dans quelle plage Ci-Ci + est situé le mot Cc; ce premier sous-ensemble possède une première entrée reliée au registre d'entrée 102 d'où elle reçoit le mot Cc et une seconde entrée reliée à la mémoire morte 1000, et deux sorties délivrant les mots Ci et Ci + délimitant la plage dans laquelle se trouve Cc;
• - un second sous-ensemble 400 permettant de déterminer dans quelle plage Cj-Cj + 1 est situé le mot Cf, ce second sous-ensemble possède une première entrée reliée au registre d'entrée 103 d'où elle reçoit le mot Cf et une seconde entrée reliée à la mémoire morte 1000 et deux sorties délivrant les mots Cj, Cj + 1 délimitant la plage dans laquelle se trouve Cf;
  • un second comparateur 500 ayant deux entrées recevant les mots Ci et Cj délivrés respectivement par les sous-ensembles 300 et 400 et possédant une sortie 2 dont l'état binaire indique si Ci et Cj sont ou ne sont pas égaux,
  • un premier organe de comparaison 600 apte à calculer les différences Cc-Ci et Ci+1-Cc et à déterminer laquelle de ces deux
  • différences est la plus faible; ce premier organe possède une première et une deuxième entrées reliées respectivement aux deux sorties du premier sous-ensemble 300 d'où elles reçoivent les mots Ci et Ci + 1, et une troisième entrée reliée au registre d'entrée 102 d'où elle reçoit le mot Cc, ce premier organe 600 possédant une sortie 5 dont l'état binaire indique si Cc-Ci est ou n'est pas inférieur à Ci+1-Cc,
  • un second organe de comparaison 700 apte à calculer les différences Cf-Cj et Cj+1-Cf et à déterminer laquelle de ces deux différences est la plus faible; ce second organe possède une première et une seconde entrées reliées respectivement aux deux sorties du second sous-ensemble 400 d'où elles reçoivent les mots Cj et Cj + 1 et une troisième entrée reliée au registre d'entrée 103 d'où elle reçoit le mot Cf, ce second organe possédant une sortie 6 dont l'état binaire indique si Cf-Cj est ou n'est pas inférieur à Cj+1-Cf;
  • un troisième comparateur 1400 à trois entrées, dont l'une est reliée au registre 105 contenant le mot de forme F et dont les autres reçoivent les mots caractérisant l'espace alphanumérique et l'espace graphique; ce comparateur possède deux sorties 12 et 13 véhiculant des signaux binaires traduisant le résultat de la comparaison entre forme et espaces (utiles dans les réalisations décrites plus loin); un circuit logique de décision 800 comprenant huit entrées reliées respectivement aux sorties 3, 1, et 4 du premier comparateur 200, à la sortie 5 du premier organe de comparaison 600, à la sortie 6 du second organe de comparaison 700 et aux sorties 12 et 13 du troisième comparateur 1400; ce circuit logique 800 a pour fonction la mise en oeuvre de l'opération de choix définie plus haut; il possède trois sorties 7, 8 et 9,
  • un ensemble multiplexexeur 900, possédant des entrées de données recevant les mots de forme et d'espace; cet ensemble multiplexeur 900 possède également des entrées de commande reliées aux sorties 7, 8 et 9 du circuit logique de décision et au registre 101 pour le bit d'inversion; ce multiplexeur possède une sortie de données, qui délivre l'un des mots d'entrée,
• - un ensemble de registres de sortie 1100 relié à l'équipement de sortie,
• - un circuit séquenceur et compteur d'adresses 1200 possédant des entrées respectivement d'initialisation, de demande de transcodage, de lecture de caractère et d'horloge d'incrémentation et des sorties, respectivement de lecture de mémoire de page, de chargement de l'ensemble des registres d'entrée 10, de chargement de l'ensemble des registres de sortie 11, de validation de caractère, et d'adresses pour la mémoire de page.

As shown in FIGS. 6a and 6b, the transcoder generally comprises:

• a set of input registers 100 connected by a bus to the page memory of the input equipment; these registers are capable of storing digital data corresponding to the various characters to be displayed; this set includes in particular a register 101 memorizing an inversion bit I, a register 102 memorizing the word of n bits corresponding to the character color Cc, a register 103 memorizing the word of n bits corresponding to the background color Cf, a register 104 storing various attributes A and a register 105 storing the word defining the shape of the character;
• a first comparator 200 having two inputs respectively connected to the two input registers 102, 103 from which they receive the words Cc and Cf, and three outputs 3, 1 and 4 whose binary state indicates whether Cc is respectively lower, equal to or greater than Cf,
• - a read only memory 1000 containing the M words Co, C1, ..., CM-1 of m bits corresponding to the M colors of the output equipment, these words being completed with n bits as indicated above and arranged in order determined, each word being addressable in the memory by an index (i or j) defining the rank of the word; we will see later that this memory includes 4 read only memories 1001, 1002, 1003, 1004;
• a first subset 300 making it possible to determine in which range Ci-Ci + is located the word Cc; this first subset has a first input connected to the input register 102 from which it receives the word Cc and a second input connected to the read-only memory 1000, and two outputs delivering the words Ci and Ci + delimiting the range in which is Cc;
• a second subset 400 making it possible to determine in which range Cj-Cj + 1 is located the word Cf, this second subset has a first input connected to the input register 103 from which it receives the word Cf and a second input connected to the read-only memory 1000 and two outputs delivering the words Cj, Cj + 1 delimiting the range in which Cf is located;
  • a second comparator 500 having two inputs receiving the words Ci and Cj delivered respectively by the subsets 300 and 400 and having an output 2 whose binary state indicates whether Ci and Cj are or are not equal,
  • a first comparator 600 able to calculate the differences Cc-Ci and Ci + 1-Cc and to determine which of these two
  • differences is the smallest; this first member has first and second inputs connected respectively to the two outputs of the first subset 300 from which they receive the words Ci and Ci + 1, and a third input connected to the input register 102 from which it receives the word Cc, this first member 600 having an output 5 whose binary state indicates whether Cc-Ci is or is not less than Ci + 1-Cc,
  • a second comparator 700 able to calculate the differences Cf-Cj and Cj + 1-Cf and to determine which of these two differences is the smallest; this second member has first and second inputs connected respectively to the two outputs of the second sub-assembly 400 from which they receive the words Cj and Cj + 1 and a third input connected to the input register 103 from which it receives the word Cf, this second member having an output 6 whose binary state indicates whether Cf-Cj is or is not less than Cj + 1-Cf;
  • a third comparator 1400 with three inputs, one of which is connected to the register 105 containing the word of form F and the others of which receive the words characterizing the alphanumeric space and the graphic space; this comparator has two outputs 12 and 13 carrying binary signals translating the result of the comparison between shape and spaces (useful in the embodiments described below); a decision logic circuit 800 comprising eight inputs connected respectively to outputs 3, 1, and 4 of the first comparator 200, to output 5 of the first comparator 600, to output 6 of the second comparator 700 and to outputs 12 and 13 of the third comparator 1400; this logic circuit 800 has the function of implementing the choice operation defined above; it has three outputs 7, 8 and 9,
  • a multiplexer assembly 900, having data inputs receiving the words of shape and space; this multiplexer assembly 900 also has control inputs connected to outputs 7, 8 and 9 of the decision logic circuit and to register 101 for the inversion bit; this multiplexer has a data output, which delivers one of the input words,
• a set of output registers 1100 connected to the output equipment,
• a sequencer and address counter circuit 1200 having respectively initialization, transcoding request, character reading and increment clock inputs and outputs, respectively of page memory reading, of loading of the set of input registers 10, loading of all output registers 11, character validation, and addresses for the page memory.

FIGS. 7a to 7f illustrate in more detail the structure of the transcoder of the invention, in the case where the input equipment comprises N = 2n colors. It can be, for example, 24-bit parallel 8-color videotex, the output equipment comprising less than 8 colors, and for example 2. This example will be repeated in more detail with reference to the following figures, since it corresponds to specific solutions.

FIG. 7a shows a subset 300 comprising M comparators 301, etc ... 30M with two inputs, one receiving the word Cc coming from the input register 102, the other one of the M words C0,. .., CM-1 representing the output colors. These comparators work on n bits and they have an output which indicates whether the word received on one of the inputs is or is not less than the word received on the other. The sub-assembly 300 also comprises a multiplexer 310 with M inputs connected to the preceding comparators and with m outputs; these m outputs, by their binary state, give the rank i of the color Ci for which Ci is less than Cc and for which Ci + is greater than Cc. In other words, i is the rank of the last comparator 301, ..., 30M indicating that the color Ci is less than Cc. The subset 300 also includes an adder 311 with n bits, adding 1 to the number i that it receives and therefore delivering the number i + 1. The subset 300 gives the information relating to the interval i / i + 1 in which the character color Cc is situated.

Two read only memories 1001 and 1002 containing the words C0, ..., CM + 1 1 are addressed respectively by i and i + 1. They therefore deliver the words Ci and Ci + 1 limiting the interval in which Cc is found.

In FIG. 7b there is a subset 400 completely similar to 300, with M comparators 401, .., 40M, a multiplexer 410 of type M- + m, an adder 411 and two read only memories 1003, 1004 which deliver the words Cj and Cj + which limit the interval in which the background color Cf contained in the input register 103 is situated.

The set of four read-only memories 1001 to 1004 constitutes the read-only memory 1000, which can also deliver the words C0,., CM-1 necessary for the blocks 300 and 400.

Returning to FIG. 7a, there is also a first comparator 600 which includes a NON gate 606 receiving the word Ci coming from the memory 1001 and delivering the complementary word Ci, an adder 601 adding + 1 to This and delivering This +1, an adder 602 with n bits receiving This +1 and Cc and delivering the sum of these two words. The sub-assembly 600 also includes a NON gate 607 receiving Cc and delivering Cc, an adder 605 adding 1 to this number, an adder 603 receiving Cc + 1 and Ci + 1 coming from memory 1002, and delivering CC +1 + Ci +1; finally, block 600 includes an n-bit comparator 604, which compares This + + Cc and CC + + Ci + 1. This comparator has an output 5 which is active (that is to say which delivers a logic 1) if This + + Cc is less than CC +1 + Ci + 1, in other words if Cc-Ci is less than Ci + 1-Cc.

In other words, the comparison of the deviations Cc-Ci and Ci + 1-Cc is done through the calculation of the 2's complements of Ci and Cc (inversion and addition of 1).

Similarly, the subassembly 700 shown in FIG. 7b comprises an inverter 706, an adder 701, an adder 703, an inverter 707, an adder 705, an adder 702, a comparator 704, whose output 6 is active if Cf-Cj is less than Cj + 1-Cf.

FIG. 7c shows, on its left side, a comparator 201 having two inputs, connected respectively to the input registers 102 and 103 and receiving Cc and Cf, and three outputs, respectively 3, 1 and 4, indicating whether Cc is lower, equal to or greater than Cf. FIG. 7c also shows, on its right side, a comparator 501 having two inputs connected to the multiplexers 310 and 410, from which they receive the numbers i and j, and an output 2 indicating whether these two numbers are equal.

It will be observed that the comparator 501 operates with m bits since the numbers i and j are themselves with m bits. But one could work on the words Ci and Cj, provided that the comparator 501 is connected downstream of the memories 1001 and 1004 and no longer upstream.

FIG. 7d represents two blocks 801 and 802 belonging to the decision logic circuit 800. The first 801 comprises three inverters 897, 898, 899, two AND gates 895 and 896, an OR gate 894 whose output 8 is the general output of 801. The second circuit comprises, in the same way, three inverters 890, 891, 892, two AND gates 888 and 889, and an OR gate 887 whose output 7 is the general output of circuit 802.

The inputs of these different gates are connected to outputs 1, 2, 3, 4, 5 and 6 of the various circuits mentioned above (1, 2, 3,4 are the outputs of comparators 201 and 501 in FIG. 7c, 5 is the output of the sub-assembly 600 of FIG. 7a and 6 the output of the sub-assembly 700 of FIG. 7. These logic circuits implement the decision algorithm described above (FIG. 5).

FIG. 7e shows the structure of the multiplexer 900. This consists of three multiplexers 2 → 1, the first 901, controlled by the signal coming from the output 1 of the comparator 201 and receiving the shape and space data, the second 902, controlled by the signal from output 7 of logic circuit 802, and receiving the words Ci and Ci + 1, and the third, 903, controlled by the signal from output 8 of circuit 801 and receiving the words Cj and Cj + 1.

It is clear that one thus selects, depending on the value of the signal 1, either the shape or the space; according to signal 7, either Ci or Ci + 1; and according to signal 8, either Cj or Cj + 1.

The word relating to the form, that is RO, is loaded into an output register 1108. The word R1, relating to colors, is loaded into a double register 1109, 1110 for Cc and Cf. These output registers are actuated by a connection 11 coming from the sequencer 1201. The output of these registers is connected to the output equipment which thus receives information of form RO and information of color R1.

Finally, Figure 7f shows a detail of the sequencing circuit. This circuit includes a sequencer 1201 and a counter 1202, with connections which have already been indicated in connection with FIG. 6b. We simply note an additional counter reset connection (RESET) by the sequencer.

• Phase 00: A la mise sous tension, le séquenceur est initialisé par le fil initialisation; il effectue une remise à zéro (RAZ) du compteur d'adresse, met à 1 le fil lecture de la mémoire d'image RD, à 0 le fil "caractère valide" (état inactif); il ne délivre aucun signal jusqu'à ce qu'il reçoive le signal de demande de transcodage (première ligne).
• Phase 01: C'est la demande de transcodage (transition 0→1).
• Phase 02: C'est la phase de préparation de RO et R1 qui sont les contenus des registres de sortie; le transcodeur envoie le signal RD vers la mémoire d'image (RD = 0) et le signal de chargement des registres d'entrée 101 à 105 par la connexion 10; ce signal permet donc le chargement des informations d'inversion dans 101, de couleur de caractère Cc dans 102, de couleur de fond Cf dans 103, d'attributs A dans 104 et de forme F dans 105; la taille de l'ensemble des registres 101 à 105 est de 24 bits dont 1 bit pour l'inversion, 3 pour la couleur de caractère et 3 pour la couleur de fond et généralement 8 bits pour la forme F. Le transcodeur compare ensuite Cf et Cc dans le comparateur 3 bits 201 et le résultat est donné par l'état des 3 fils 1, 3, 4. Si Cf=Cc (fil 1 actif), le multiplexeur 8 bits 901 valide le code espace, donc RO est chargé par l'espace. Sinon il valide la forme F. L'ensemble des attributs de forme, autres que l'inversion (hauteur, largeur, incrustation, masquage, soulignement, clignotement...) sont chargés sans modification dans R1. Le bit d'inversion est le résultat d'une logique combinatoire simple 802 traduisant l'algorithme. L'inversion est validée (fil 2) s'il y a inversion vidéotex (1 actif) et Cf>Cc ou s'il n'y a pas d'inversion vidéotex et Cf< Cc. Les informations de RO et R1 étant prêtes, le séquenceur envoie un signal de chargement des registres de sortie 108 et 109 par la connexion 11.
• Phase 03: Fin d'acquisition de RO et R1. Cette phase est déclenchée par la transition 0→ 1 du signal "caractère valide".
• Phase 04 : Attente du signal "caractère lu" envoyé par l'équipement de sortie en acquittement de "caractère valide". Il est à noter qu'avant d'envoyer le signal "caractère lu", l'horloge d'incrémentation du compteur d'adresse aura au prealable été fournie au compteur 1202.
• Phase 05 : Lecture du caractère à la transition 1 → 0 du signal "caractère valide".

The timing diagram of FIG. 8 illustrates the operation of the transcoder whose components have been represented in FIGS. 7a to 7f. This operation is broken down into various phases indicated on the lower line:

• Phase 00: On power up, the sequencer is initialized by the initialization wire; it performs a reset to zero (RESET) of the address counter, sets the image memory reading wire to 1 RD , at 0 the thread "valid character" (inactive state); it does not deliver any signal until it receives the transcoding request signal (first line).
• Phase 01: This is the transcoding request (transition 0 → 1).
• Phase 02: It is the preparation phase of RO and R1 which are the contents of the output registers; the transcoder sends the signal RD to the image memory ( RD = 0) and the signal for loading the input registers 101 to 105 via connection 10; this signal therefore makes it possible to load the inversion information in 101, of character color Cc in 102, of background color Cf in 103, of attributes A in 104 and of form F in 105; the size of the set of registers 101 to 105 is 24 bits including 1 bit for the inversion, 3 for the character color and 3 for the background color and generally 8 bits for the form F. The transcoder then compares Cf and Cc in the 3-bit comparator 201 and the result is given by the state of the 3 wires 1, 3, 4. If Cf = Cc (wire 1 active), the 8-bit multiplexer 901 validates the space code, therefore RO is loaded by the space. Otherwise it validates the form F. All the form attributes, other than the inversion (height, width, inlay, masking, underlining, blinking, etc.) are loaded without modification in R1. The inversion bit is the result of simple combinatorial logic 802 translating the algorithm. The inversion is validated (thread 2) if there is videotex inversion (1 active) and Cf> Cc or if there is no videotex inversion and Cf <Cc. The information from RO and R1 being ready, the sequencer sends a signal for loading the output registers 108 and 109 via the connection 11.
• Phase 03: End of acquisition of RO and R1. This phase is triggered by the 0 → 1 transition of the "valid character" signal.
• Phase 04: Waiting for the "read character" signal sent by the output equipment in acknowledgment of "valid character". It should be noted that before sending the "read character" signal, the incrementing clock of the address counter will first have been supplied to counter 1202.
• Phase 05: Reading of the character at transition 1 → 0 of the "valid character" signal.

After incrementing the address counter by one unit either by the output equipment (in the case of certain flat screens) or by the sequencer (in the case of printers), the various phases are resumed for processing the next character.

In the case of videotex, in addition to the alphanumeric character sets, semi-graphic games are used, the principle of which is illustrated in FIG. 9a. The matrix containing the character is broken down into 6 blocks b _o to b _{5 which} can each be switched on or off. This gives 64 different shapes. Each of these shapes can be matched with the complementary shape, as illustrated in Figure 9b. The two shapes shown are said to be "paired". We pass from one to the other by inverting the command of the state of the paving stones.

As for the alphanumeric character set, it is also linked to an inversion bit.

• A) si Cf=Cc alors la forme transmise (RO) est l'espace;
• B) sinon Cf≠ Cc, alors un seul cas se présente puisqu'il n'y a qu'une seule plage dans l'ensemble des couleurs d'arrivée:
  • Ba) - si l'inversion n'est pas valide:
    • - si Cf > Cc RO est constitué par la forme F
    • - si Cf < Cc RO est constitué par la forme inversée F
  • Bb) - si l'inversion est valide:
    • - si Cf>Cc RO est constitué par la forme inversée F
    • - si Cf < Cc RO est constitué par la forme F.

In general, if the inversion bit is present, the shape of the character will be noted F. The transcoder must therefore be designed to be able to take this information relating to the inversion into account. As illustrated in FIG. 6a, it is the role of the input register 101 to memorize the inversion bit I. FIG. 10 is precisely intended to illustrate this aspect in a simple case where the output equipment n uses only two output colors. In this case, there is therefore only one color range at the output. It is defined by black, corresponding to Ci and by white corresponding to Ci + 1. In this case, we therefore have Ci = Cj and the flowchart in Figure 5 is simplified considerably as shown in Figure 10. The The represented organization chart reads as follows:

• A) if Cf = Cc then the transmitted form (RO) is space;
• B) otherwise Cf ≠ Cc, then there is only one case since there is only one range in the set of arrival colors:
  • Ba) - if the inversion is not valid:
    • - if Cf> Cc RO is constituted by the form F
    • - if Cf <Cc RO is constituted by the inverted form F
  • Bb) - if the inversion is valid:
    • - if Cf> Cc RO is constituted by the inverted form F
    • - if Cf <Cc RO is constituted by the form F.

This algorithm applies differently depending on whether the output equipment interprets the inversion bit or not.

• A) si Cf=Cc alors la forme transmise est l'espace,
• B) sinon Cf≠ Cc:
  • Ba) pour I non valide:
    • si Cf > Cc RO=F, bit d'inversion non valide
  • si Cf < Cc R0=F, bit d'inversion valide Bb) pour valide:
    • si Cf>Cc RO=F, bit d'inversion valide
    • si Cf<Cc R0=F, bit d'inversion non valide.

If the output equipment has the inversion, then it becomes:

• A) if Cf = Cc then the transmitted form is space,
• B) otherwise Cf ≠ Cc:
  • Ba) for I not valid:
    • if Cf> Cc RO = F, invalid inversion bit
  • if Cf <Cc R0 = F, valid inversion bit Bb) for valid:
    • if Cf> Cc RO = F, valid inversion bit
    • if Cf <Cc R0 = F, invalid inversion bit.

In the case where the output equipment only works with 2 colors, the structure of the transcoder takes a simplified form compared to the general variant of FIGS. 7a to 7f. The corresponding diagram is represented in FIG. 11 where the numerical references designate the same elements as for FIGS. 7a to 7f. In this figure, the notations a and y of the register 105 mean "alphanumeric" and "graphic"; the hlClmis notation for register 104 designates attribute codes meaning respectively "height, width, flashing, masking, overlay, underlining". These attributes will completely occupy the output register 1109 (content R1). In this particular case, there is more strictly speaking no color word to select.

The above variant corresponds to the case where reversal is possible in the output equipment. Naturally, the invention can be applied in the case where this equipment does not accept inversion. The decision algorithm should then be slightly modified to simulate this inversion by acting on the shape of the displayed character. The output register 1109 loading R1 will no longer contain information 1, and the loading register RO will contain either F or F. This supposes that the multiplexer 901 receives not only the form F but also the inverted form F, and not only the space but also the solid pavement. The multiplexer 901 therefore changes from a type 2 → 1 to a type 4 → 1.

A second variant of the transcoder of the invention will now be described, which relates to the 16-bit parallel and serial videotex, with 8 colors for the input equipment, the output equipment being a printer or a flat screen in two colors. , not having the inversion bit. This is the most complex case.

• a) Tout d'abord, la couleur de fond est un attribut "série" pour les caractères alphanumériques (c'est donc un attribut défini par zone) et un attribut "parallèle" pour les caractères semigraphiques. Ceci nécessite l'ajout d'une cellule de verrouillage de la couleur de fond.
• b) Ensuite, il est fait usage de caractères spéciaux, appelés délimiteurs, qui introduisent des zones pour les attributs série. Ils sont à visualiser comme des espaces ou des pavés pleins, suivant le contexte. De même que pour les caractères alphanumériques, il faut connaître le type de zone dans lequel se situe le délimiteur: zone inversable ou non. Si le caractère qui suit le délimiteur est un semi-graphique, celui-ci sera dans une zone inversable, sinon il sera visualisé comme un espace. L'exemple représenté sur la figure 12 permet d'illustrer ce point. L'image représentée comprend une zone non inversable où apparaissent des caractères alphabétiques formant l'expression "L'ARBRE" et une zone inversable dans laquelle apparaissent des caractères semi-graphiques. Dans la zone non inversable, le délimiteur (carré blanc) est visualisé comme un espace, quelles que soient les couleurs Cc et Cf. Dans la zone inversable, le délimiteur est visualisé comme un pavé plein (si le fond avait été jaune, il aurait été visualisé comme un espace).
• c) Enfin, à l'effacement d'écran, celui-ci est rempli d'espaces semi-graphiques, afin d'éviter, lors du remplissage de l'écran, des effets série parasites. Il ne faut pas, au niveau de l'algorithme, les considérer comme des caractères semi-graphiques, car ils ne sont là qu'en raison de contraintes liées au vidéotex et non en tant qu'éléments de graphisme.

Restricting videotex to 16-bit terminals places additional constraints on the transcoder.

• a) First, the background color is a "series" attribute for alphanumeric characters (it is therefore an attribute defined by area) and a "parallel" attribute for semigraphic characters. This requires the addition of a background color lock cell.
• b) Next, special characters, called delimiters, are used which introduce zones for the serial attributes. They are to be viewed as solid spaces or paving stones, depending on the context. As for the alphanumeric characters, it is necessary to know the type of zone in which the delimiter is situated: reversible zone or not. If the character following the delimiter is a semi-graphic, it will be in an invertible zone, otherwise it will be displayed as a space. The example shown in Figure 12 illustrates this point. The image shown includes a non-invertible zone where alphabetical characters appear forming the expression "THE TREE" and an invertible zone in which semi-graphic characters appear. In the non-invertible zone, the delimiter (white square) is displayed as a space, whatever the colors Cc and Cf. In the invertable zone, the delimiter is displayed as a solid block (if the background had been yellow, it would have been viewed as a space).
• c) Finally, when the screen is erased, it is filled with semi-graphic spaces, in order to avoid parasitic serial effects when filling the screen. At the level of the algorithm, they should not be considered as semi-graphic characters, because they are only there because of constraints linked to videotex and not as graphic elements.

The completed algorithm then presents itself as indicated in FIG. 13 where we see, in addition to the operations already described in connection with FIG. 5, tests on the presence of a delimiter, on the semi-graphic nature of the character which follows this delimiter, on the presence of a filling graphic character, on the validity of a graphic environment.

• A)si le caractère est un délimiteur, alors:
  • Aa) si le caractère suivant est un semi-graphique défini par C'c et C'f alors:
    • a) si Cc = alors si Cc=C'f graphique > C'c graphique, R0=espace, sinon R0=pavé plein,
    • β) si Cc≠ C'f alors -si C'f<Cc, RO=espace sinon R0=pavé plein,
  • Ab) si le caractère n'est pas un semi-graphique alors RO = espace;
• B) si le caractère n'est pas un délimiteur:
  • Ba) si c'est un semi-graphique:
    • a) s'il s'agit du caractère semi-graphique de remplissage alors RO=espace
    • β) s'il ne s'agit pas du caractère semi-graphique de remplissage alors le signal "environnement graphique" est validé. Alors si Cf=Cc, RO=espace, si Cf# Cc, alors RO =forme si Cf > Cc et R0 = F si Cf < Cc.
  • Bb) si ce n'est pas un semi-graphique (alors c'est un alphanumérique)
    • 1) s'il s'agit de l'espace:
      • 1a) si le signal "environnement graphique" est non validé, alors R0=espace,
      • 1β) si le signal "environnement graphique" est validé et s'il y a inversion: alors RO=espace si Cf≤Cc et RO=pavé plein dans le cas contraire s'il n'y a pas inversion alors R0= espace si Cf≥Cc et R0=pavé plein dans le cas contraire.
    • 2) s'il ne s'agit pas de l'espace, autrement dit s'il s'agit d'un caractère alphanumérique hors espace: alors le signal "environnement graphique" est non validé, et R0=F.

This flowchart then reads as follows:

• A) if the character is a delimiter, then:
  • Aa) if the following character is a semi-graphic defined by C'c and C'f then:
    • a) if Cc = then if Cc = C'f graphic>C'c graphic, R0 = space, otherwise R0 = solid block,
    • β) if Cc ≠ C'f then -if C'f <Cc, RO = space otherwise R0 = solid block,
  • Ab) if the character is not a semi-graphic then RO = space;
• B) if the character is not a delimiter:
  • Ba) if it is a semi-graphic:
    • a) if it is the semi-graphic filling character then RO = space
    • β) if it is not a semi-graphic filling character then the "graphic environment" signal is validated. Then if Cf = Cc, RO = space, if Cf # Cc, then RO = form if Cf> Cc and R0 = F if Cf <Cc.
  • Bb) if it is not a semi-graphic (then it is an alphanumeric)
    • 1) if it is space:
      • 1a) if the "graphic environment" signal is not validated, then R0 = space,
      • 1β) if the "graphic environment" signal is validated and if there is an inversion: then RO = space if Cf≤Cc and RO = full block otherwise if there is no inversion then R0 = space if Cf≥Cc and R0 = solid block otherwise.
    • 2) if it is not about space, in other words if it is about an alphanumeric character except space: then the signal "graphic environment" is not validated, and R0 = F.

FIGS. 14a to 14f illustrate the structure of the transcoder in this particular case, with the same conventions for the numerical references as for the preceding figures. Furthermore, the 16 bits coming from the image memory are referenced BO to B15. The colors are coded on 3 bits denoted BcVcRc for the character color and BfVfRf for the background color. The different bits of the color words are conveyed by connections bearing the references 13, 14, 15 for BfVfRf and 16, 17, 18 for BcVcRc for a given character and, respectively, 22, 23, 24 and 25, 26, 27 for the next character. Connection 12 carries a signal concerning the presence of delimiters.

It will be noted, in FIG. 14a, that the input register comprises two additional registers 106 and 107 intended to receive the 16 bits (D'0, ..., D'7 and D'8, ..., D ' 15) of the character of rank n + 1, when the character of rank n is loaded in the registers 102, 103, 105.

Form F is coded on 7 bits (DO-D6); which are compared with the 7 bits XO-X6 of space in comparator 1402 whose output is referenced 21. Similarly for the 8 bits of space X8 to X15 which are compared to the 8 character bits from 102, 103 , 104 in the comparator 1403 whose output is referenced 20.

• - les 3 bits véhiculés par les 3 connexions 46, 47,48 issues d'une logique 805 représentée sur la figure 14e avec les 3 bits de Cc véhiculés par les connexions 16, 17, 18,
  • - les 3 bits de C'f et Cc,
  • - les 3 bits de C'f et C'c.

FIG. 14b shows three comparators 201, 201 ′ and 201 ″ whose function is to compare respectively:

• the 3 bits conveyed by the 3 connections 46, 47, 48 resulting from an 805 logic represented in FIG. 14e with the 3 bits of Cc conveyed by the connections 16, 17, 18,
  • - the 3 bits of C'f and Cc,
  • - the 3 bits of C'f and C'c.

The outputs of these comparators which are used are respectively noted 39, 40, 60 for the first, 41.42 for the second and 43 for the third.

FIG. 14c shows an embodiment for a first logic decision circuit 801. This circuit comprises two inverters 820, 821 connected to an OR gate 822; an inverter 823; AND gates 824 and 825; an inverter 826; a NAND gate 827; two inverters 829, 830; five AND gates 831, 832, 833, 834, 835 and finally an OR gate 836 whose output 31 constitutes the output of circuit 801.

The function of this circuit 801 is to select a code corresponding to a graphic space.

Figure 14d shows 3 other logic circuits. The first, referenced 803, comprises an inverter 840, two AND gates 841, 842, an inverter 843; an AND gate 844; two doors OR 845, 846; two AND gates 847, 848 and finally an OR gate 850 whose output 32 constitutes the general output of circuit 803. This circuit fulfills the function of selecting a full graphic block.

The circuit 803 ′ comprises two AND gates 861, 862 and an OR gate 863 of output 33. This circuit has the function of selecting, for RO, bits D7-DO of shape.

Finally, the circuit 803 "consists of a single AND output gate 864 34. The input marked 45 of this door corresponds to the output of door 824 of the circuit 801. The circuit 803" is used to select the bit D7 and the complementary bits D 6 = D 0 for R0.

Figure 14e shows other logic decision circuits. Circuit 805 includes: an OR gate 865; an AND 866 gate; a locking circuit 867 with three outputs 46, 47 and 48. The circuit 805 has the function of locking the background color when a delimiter or a graphic character is present.

Circuit 806 comprises a demultiplexer of type 2 → 3, the three outputs of which are referenced 50, 51, 52. This circuit 806 has for function the separation between delimiter, graphic character, alphanumeric character.

Finally, circuit 804 includes an OR gate 869; an AND 870 gate; a flip-flop 871; an inverter 872; an OR gate 873. It has outputs 53 and 54. Furthermore, this circuit 804 also includes an inverter 874 and an AND gate 875 of output 58.

The numerical references associated with the connections involved in all these logical decision circuits make it possible to establish the appropriate connections.

Figure 14f shows the output elements of the transcoder. Multiplexer 901 receives data in the form of bits E7-EO representing the graphic space code, of bits B7-B0 representing the full block code, of bits D7-DO representing the form, of bits D7 D 6 = D 0 representing the inverted form. This multiplexer 901 is controlled by the bits conveyed by the connections 31, 32, 33, 34 from the logic decision circuits 801, 803, 803 'and 803 "of FIGS. 14c and 14d, bits which are multiplexed beforehand in a multiplexer 906 type 4- 2, and whose outputs are referenced 29 and 30.

The elements represented in FIG. 14f also comprise a gate 907 receiving on the one hand the bits D14-D11 and on the other hand the attribute bits I, h, 1 by the connections 13, 14 and 15 as well as the bit flashing C1; this door 907 is controlled by a connection 35.

Finally, the circuit shown comprises a door 908 receiving the data D6-D4 and controlled by a connection 36.

The data which pass through the multiplexer 901 are loaded into the register 1108. Those which have passed through the gates 907 and 908 are loaded into the register 1109. These two registers are controlled by the sequencer by the connection 38 shown elsewhere in FIG. 14a .

These two registers respectively deliver bits C7-CO characterizing the form and bits A6-AO characterizing the attributes of the character.

• a) la sélection RO = F si l'on a un caractère semi-graphique hors effacement de page connexion (45) et si Cf > Cc (40) ou si l'on a un caractère alphanumérique (50) avec un signal "environnement graphique" non validé (54). La relation logique réalisée par 803' doit donc être:
  • 33 = (45 ET 40) ou (50 ET 54)
  
  Alors l'activation de 33 permettra au multiplexeur de sélectionner F.
• b) la sélection RO=F si l'on a un semi-graphique hors effacement de page et si Cf< Cc. La relation logique, réalisée par 803" doit donc être:
  • 34 = (45 ET 39)
  
  Alors l'activation de 34 permettra au multiplexeur de sélectionner F.
• c) la sélection "pavé plein" si l'on a:
  • c1) soit un espace alphanumérique (50 ET 21) dans un "environnement graphique" validé (53) ce qui implique 49 = (50 ET 21 ET 53) dans 801 avec 1 = 0 + (13) et Cf < Cc (39) ou 1 = 1 et Cf>Cc (40). L'opération logique effectuée par le circuit 803 est donc:
  • 49 ET [(39 ET i) OU (40 ET I)] c2) soit un délimiteur (52) suivi d'un graphique (56) et:
  • (C'f = Cc ET C'f < C'c) = (41 ET 43) OU C'f > Cf (42). D'où l'opération logique effectuée par le circuit 803:
  • (56 ET 52) ET [(41 ET 43) OU 42)

The role of the multiplexer 901 is to carry out:

• a) the selection RO = F if we have a semi-graphic character excluding deletion of the connection page (45) and if Cf> Cc (40) or if we have an alphanumeric character (50) with an "environment" signal graphic "not validated (54). The logical relation made by 803 'must therefore be:
  • 33 = (45 AND 40) or (50 AND 54)
  
  Then activating 33 will allow the multiplexer to select F.
• b) the selection RO = F if there is a semi-graph excluding page erasure and if Cf <Cc. The logical relation, realized by 803 "must therefore be:
  • 34 = (45 AND 39)
  
  Then activating 34 will allow the multiplexer to select F.
• c) the selection "full block" if you have:
  • c1) or an alphanumeric space (50 AND 21) in a validated "graphic environment" (53) which implies 49 = (50 AND 21 AND 53) in 801 with 1 = 0 + (13) and Cf <Cc (39) or 1 = 1 and Cf> Cc (40). The logical operation performed by circuit 803 is therefore:
  • 49 AND [(39 AND i ) OR (40 AND I)] c2) either a delimiter (52) followed by a graph (56) and:
  • (C'f = Cc AND C'f <C'c) = (41 AND 43) OR C'f> Cf (42). Hence the logical operation performed by circuit 803:
  • (56 AND 52) AND [(41 AND 43) OR 42)

• 32 = 49 [(39 ET i) OU (40 ET I) OU 56 ET 52 [(41 ET 43) OU 42)]
  • d) la sélection "espace" = RO si l'on a: d1) soit un délimiteur non suivi de graphique (52 ET 56);
  • d2) soit un délimiteur suivi de graphique et C'f = Cc et C'f ≥ C'c ou C'f < Cf donc 57, d3) soit un alphanumérique espace dans un environnement graphique (49) avec I = 0 et Cf ≥ Cc ou I = 1 et Cf _< Cc (55),
  • d4) soit un graphique d'effacement de page (51 ET 20 ET 21),
  • d5) soit on graphique hors effacement de page (45) avec Cf = Cc (60).
• Ces 5 conditions peuvent s'écrire de manière logique:
• RO = "espace"si:
• 31 = (52 ET 56) 57 OU 55 OU (51 ET 20 ET 21) OU 45 ET 60).

These two conditions can be written: RO = "full block" if:

• 32 = 49 [(39 E T i) OR (40 AND I) OR 56 AND 52 [(41 AND 43) OR 42)]
  • d) the selection "space" = RO if we have: d1) either a delimiter not followed by a graph (52 AND 56);
  • d2) either a delimiter followed by a graph and C'f = Cc and C'f ≥ C'c or C'f <Cf therefore 57, d3) or an alphanumeric space in a graphic environment (49) with I = 0 and Cf ≥ Cc or I = 1 and Cf _< Cc (55),
  • d4) or a page erasure graphic (51 AND 20 AND 21),
  • d5) or graph without erasing the page (45) with Cf = Cc (60).
• These 5 conditions can be written logically:
• RO = "space" if:
• 31 = (52 AND 56) 57 OR 55 OR (51 AND 20 AND 21) OR 45 AND 60).

• - ajout d'un comparateur 8 bits (1403) afin de détecter la configuration "graphique de remplissage";
• - ajout d'un démultiplexeur 806 pour distinguer le délimiteur (connexion 52 active), l'alphanumérique 50 et le graphique 51;
• - ajout d'une cellule de verrouillage 805 pour la couleur de fond, quand il y a un délimiteur 52 ou un semi-graphique; cette cellule est verrouillée sur une transition du signal véhiculé par la connexion 37 venant du séquenceur (sortie CLK) et si 52 ou 51 sont actifs. Les connexions 46, 47 et 48 délivrent les 3 bits de la couleur de fond Cf;
• - ajout de deux registres d'entrée 106 et 107 de 8 bits, pour stocker le caractère suivant;
• - ajout de deux comparateurs 3 bits 201', 201" pour comparer C'f-Cc et C'f-C'c et utilisation des connexions 41 pour C'f = Cc, 42 pour C'f > Cc et 43 pour C'f < C'c;
• - modification des signaux de commande du multiplexeur 901.

Compared to the transcoder of FIGS. 7, we therefore have the following modifications:

• - addition of an 8-bit comparator (1403) in order to detect the "filling graph"configuration;
• - addition of a demultiplexer 806 to distinguish the delimiter (connection 52 active), the alphanumeric 50 and the graph 51;
• - addition of a locking cell 805 for the background color, when there is a delimiter 52 or a semi-graphic; this cell is locked on a transition of the signal conveyed by the connection 37 coming from the sequencer (CLK output) and if 52 or 51 are active. Connections 46, 47 and 48 deliver the 3 bits of the background color Cf;
• - addition of two 8-bit input registers 106 and 107 to store the next character;
• - addition of two 3-bit comparators 201 ', 201 "to compare C'f-Cc and C'f-C'c and use of connections 41 for C'f = Cc, 42 for C'f> Cc and 43 for C 'f <C'c;
• - modification of the control signals of the multiplexer 901.

The timing diagram of FIG. 15 explains the operation of this variant of the transcoder. It is more complex than the previous one (Cf. figure 8) even if one finds there essentially the same phases. However, it includes an operation for loading the additional entry registers 106, 107 relating to the next character. It is phase 02 which is weighed down, because it takes a double memory addressing to acquire the next character (case of the delimiter).

For this phase 02, the sequencing is then the following sending of a first read signal RD to the page memory to acquire the character to be transcoded; this signal is followed by a signal for loading the input registers 101 to 105 (3rd line); the address counter 1202 has an up / down counting input (U / D) which is positioned for up counting; the sequencer sends a CK signal, which increments the address and a CLK signal locks the background color (case of the delimiter and the graphic). An RD signal is then sent to acquire the next character; the latter is followed by a signal for loading the input registers 106 and 107 and counting down the input of the counter; then the sequencer sends a new CK signal to return to the initial address and then puts the U / D input back into counting and sends the "valid character" signal.

Claims (7)

1. Colour transcoding process permitting the interconnection between:

- on the one hand an input equipment incorporating a page memory, whose content can define a mosaic-type image formed from characters, each defined by a shape (F), a character colour (Cc), a background colour (Cf) and various other attributes, the character colour (Cc) and background colour (Cf) being taken in a group having N thereof;

- and on the other hand an output equipement incorporating means for the display of the mosaic-type image with the aid of characters having a shape, a character colour and a background colour, the character and background colours being taken from a group having M thereof, M being less than N,
said transcoding process being characterized in that it comprises the following operations:

- to each of the M colours of the output equipment is allocated a binary word with m bits, the M words are classified in accordance with a certain order, said M words are completed to n bits and the M correspending words are classified (C0, C1, ..., CM-1) in a memory,

- for each character to be transcoded, storing takes place of a word of n bits corresponding to the character colour Cc and a word of n bits corresponding to the background colour Cf,

- the range Ci-Ci + in which is located word Cc and the range Cj-Cj + 1 in which is located the word Cf are determined,

- the character colour is taken either as the colour Ci, or the colour Ci + and the background colour is taken either as the colour Cj, or as the colour Cj + 1, the choice in this double alternative being dictated by the following criteria: the words Cf and Cc are compared:

A) if the word Cc is not equal to the word Cf, then the shape of the character is not modified and word Ci is compared with word Cj to determine whether Ci is equal to Cj or whether Ci is not equal to Cj:

Aa) if Ci is not equal to Cj:

Aa1) detemination takes place to establish which is the smaller of the two differences Cf-Cj and Cj+1-Cf; if Cf-Cj is the smaller difference then the colour Cj is chosen for the background colour, whereas in the opposite case the colour Cj + 1 is chosen for the background colour,

Aa2) it is established which is the smaller of the two differences Cc-Ci and Ci+1-Cc; if Cc-Ci is the smaller difference, then colour Ci is chosen for the character colour, whereas in the opposite case, colour Ci + 1 is chosen for the character colour:

Ab) if the word Ci is equal to the word Cj, determination takes place to establish whether Cf is smaller than Cc, in the affirmative the colour Ci is chosen for the background colour, and the colour Ci + for the character colour, whereas in the negative, the colour Ci + is chosen for the background colour and colour Ci for the character colour;

B) if the word Cf is equal to the word Cc, the shape of the character is taken as identical to the background and the common colour of the space is taken as equal to one of the colours Ci and Ci+1.

2. Colour transcoder permitting the interconnection between on the one hand an input equipment incorporating a page memory, whose content is able to define a mosaic-type image formed from characters each of which is defined by a shape (F), a character colour (Cc), a background color (Cf) and various other attributes, the character and background colours (Cc) and (Cf) being taken from the group having N thereof and on the other hand an output equipment incorporating a means for displaying the mosaic-type image in question with the aid of characters having a shape, a character colour and a background colour, the character and background colours being taken from a group having M thereof, M being smaller than N, said transcoder being characterized in that it comprises:

- a group of input registers (100) connected to the page memory of the input equipmemt and able to store digital data corresponding to the various characters to be displayed, said group in particular having a register (102) storing the word of n bits corresponding to the character colour Cc and a register (103) storing the word of n bits corresponding to the background colour Cf,

- a first comparator (201) with n bits having two inputs respectively connected to two input registers (102, 103), fromwhere they receive the words Cc and Cf and three outputs (3, 1, 4), whereof the binary state indicates whether Cc is smaller, equal to or higher than Cf,

- a read-only memory (1000) having M words (C0, C1, ..., CM-1) of m bits corresponding to M colours of the output equipment, said words being completed to n bits and classified in a given order, each word being addressable in the memory by a symbol (i or j) defining the order of the word,

- a first subassembly (300) making it possible to determine in which range Ci-Ci + 1 is located the word Cc, said first subassembly having a first input connected to the input register (102) from which it receives the word Cc and a second input connected to the read-only memory, as well as two outputs supplying the words Ci and Ci + 1 defining the range in which Cc is located,

- a second subassembly (400) making it possible to determine in which range Cj-Cj + 1 is located the word Cf, said second subassembly having a first input connected to the input register (103) from which it receives the word Cf and a second input connected to the read-only memory, as well as two outputs supplying the words Cj, Cj + defining the range in which Cf is located,

- a second comparator (500) having two inputs receiving the words Ci and Cj and having an output (2), whereof the binary state indicates whether Ci and Cj are or are not equal,

- a first comparison unit (600) able to calculate the differences Cc-Ci and Ci + 1-Cc and determine which of these two differences is the smaller, said first unit having first and second inputs respectively connected to the two outputs of the first subassembly (300) from where they receive the words Ci and Ci + 1, as well as a third input connected to the input register (102) from where it receives the word Cc, said first unit having an output (5), whose binary state indicates whether Cc-Ci is or is not smaller than Ci + 1-Cc,

- a second comparison unit (700) able to calculate the differences Cf-Cj and Cj + 1-Cf and determine which of said two differences is the smaller, said second unit having first and second inputs respectively connected to the two outputs of the second subassembly (400) from where they receive the words Cj and Cj + and a third input connected to the input register (103) from where it receives the word Cf, said second unit having an output (6), whereof the binary state indicates if Cf-Cj is or is not lower than Cj + 1-Cf,

- a logic decision circuit (800) incorporating at least six inputs respectively connected to the outputs (3, 1, 4) of the first comparator (201), to the output (5) of the first comparison unit (600), to the output (6) of the second comparison unit (700) and to the output (2) of the second comparator (500), said logic circuit having as the function the performance of the choice operation defined in claim 1, said circuit having three outputs, the first (7) supplying a first bit, the second (8) supplying a second bit and the third (9) supplying a third bit,

- a multiplexer means (900) having data input connected to the first and second subassemblies (300, 400) and receiving words characterizing the space and shape, as well as control inputs connected to the outputs (7, 8, 9) of the logic decision circuit, said multiplexer means having a data output,

- a group (1100) of output registers having an input connected to the output of the multiplexer means (900) and an output connected to the output equipment,

- a sequencing and address counting circuit (1200) having inputs respectively for initialization, transcoding request, character reading and incrementation clock, as well as outputs respectively control, page memory read, loading the group of input registers (10), loading the group of output registers (11), character validation and address output.

3. Transcoder according to claim 2, characterized in that the input register (100) comprises a register (101) allocated to a reversal bit (I).

4. Transcoder according to claim 2, characterized in that the input register (100) comprises two supplementary registers (106, 107) for storing information relative to the character following the processed character.

5. Transcoder according to claim 4, characterized in that it comprises two supplementary comparators (201' and 201") for comparing the current character colour Cc and the following character color C'f, as well as the colours C'f and C'c of the following character.

6. Transcoder according to claim 4, characterized in that it comprises a supplementary input register loaded by a bit (12) indicating the presence of a delimiter character.

7. Transcoder according to any one of the claims 2 to 6, characterized in that it comprises 3 bit units for processing N = 8 colours.

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