EP0109963B1 - Device for editing picture carriers of television signals - Google Patents

Abstract

1. Device for editing picture carriers of television signals by phase-locked cross-coupling of the picture carriers by means of linking the individual picture-carrier frequencies in each case to a reference frequency and by a defined frequency offset between said signals, with a PLL-circuit consisting of a phase-comparison circuit (6), an oscillator (5) of which the frequency is regulated by the latter, and a thus controlled mixer (2), in which PLL-circuit the phase-comparison circuit (6) is driven, firstly, by the television standard intermediate-frequency signal derived from the respective information signal and, secondly, by the reference intermediate-frequency signal obtained by the mixer (2) from the oscillator signal and from a reference signal, said reference signal originating from a reference-signal source (12), said reference intermediate-frequency signal being shifted by the amount of the offset frequency produced by an appropriate generator (23), wherein one of two digital frequency dividers (7, 8) with identical basic dividing factors is series-connected with each of the two inputs (D) of the phase-comparison circuit (6), one of which (7) being driven in such a manner by the offset signal that its dividing factor changes in phase with the offset signal.

Description

The invention relates to a device for image carrier processing of television signals by phase-locked coupling of the image carriers by connecting the individual image carrier frequencies to a reference frequency and by a defined frequency offset between these signals, with one of a phase comparison circuit, an oscillator whose frequency is controlled by the latter and one controlled thereby Mixer existing PLL circuit in which the phase comparison circuit on the one hand from the television standard IF signal derived from the respective useful signal and on the other hand from the offset by the offset frequency generated by a corresponding generator, by the mixer from the oscillator signal and a reference IF signal obtained from a reference signal source originating reference signal is driven.

Devices of this type, shown in principle in FIG. 1, are, for example, from the magazine publications “Improvement of Cable TV Transmission by an Optimal Coherent Carrier System,” Broadcasting Communications 1979, H. 5, p. 209 f., And “Increasing the Transmission Capacity of Cable TV Networks” , FUNKSCHAU 1979, H. 25, p. 75 f. and "Safety distances for the co-channel operation of television transmitters when modulated with PAL color television signals". Broadcasting communications 1969, H. 6, p. 284 f. Known. They serve to reduce the interference impression caused by single-channel reception due to co-channel interference (e.g. direct radiation of the local transmitter signal in the receiver or by overreaching of neighboring transmitters) and multi-channel transmission due to nonlinear distortion, for example in line amplifiers of broadband cable networks used.

With multi-channel transmission, the interference-reducing measures of phase-locked carrier coupling and the frequency offset either allow an increase in the channel occupancy, i.e. the program capacity in already existing networks, or an increase in the length of the link with the same number of amplifiers and thus a reduction in costs.

In practice, it has proven advantageous to choose an offset frequency of n / 12 x line frequency, where n is an integer and there is a particularly low interference impression for n = 8. This offset frequency, rounded up to 10.45 kHz, is more than three powers of ten below the reference IF; this makes it impossible to filter out the desired sideband (38.9 MHz-10.45 kHz) resulting from the mixing of these two frequencies because of its small distance from the carrier frequency (38.9 MHz), so that since then only the way of suppressing the carrier and of the unwanted sideband was available with the help of a single sideband mixer (SSM). However, this requires a complex adjustment, which not only has to be carried out for both inputs of the SSM in terms of phase and amplitude and for each offset frequency, but also requires high-quality and expensive measuring devices. In addition, the level at these two inputs must be kept constant, for which a further increase in circuit complexity is necessary.

The invention has for its object to design a device of the type mentioned in such a way that the interference-reducing measures are achieved with the least possible circuitry and labor.

This object is achieved in that each of the two inputs of the phase comparison circuit is preceded by one of two digital frequency dividers and one of them is controlled by the offset signal in such a way that its sub-factor changes in time with the offset signal.

The use of a digital frequency divider in a PLL circuit is known per se, for example, from the book "Radio technology without ballast by O. Limann, Franzis-Verlag, 12th edition 1972, p. 150, but not to solve the problem according to the invention and especially with a fixed sub-factor. In contrast to this, the partial factor of the frequency divider driven by the offset signal is switched in the invention in the cycle of the offset signal (for example from 40 to 41 or vice versa), the phase comparison circuit comparing the different period of the two digital divider output signals with one another and the drawing voltage generated for the oscillator. This adjusts until the reference IF and thus, in the desired manner, the frequency of the output signal of the device is changed by exactly the offset frequency. The frequency divider thus also acts as an adder or subtractor, while such a component is additionally required when using frequency dividers with a fixed part ratio.

In addition, the device according to the invention is able, in contrast to the known SSM, which has to be readjusted for each offset frequency because of its frequency dependency, to process offset frequency deposits from broadband 0.2 to approximately 800 kHz.

In addition, the operating frequency range of the phase comparison circuit is so low when using frequency dividers with practically meaningful sub-factors that cheap CMOS components can be used instead of the expensive discrete circuits or ECL modules required in the prior art.

In the device described in claim 1, the oscillator of the PLL changes its frequency in time with the offset signal, as a result of which the useful signal is frequency-modulated at the output mixer. In order to avoid this undesirable effect, a low-pass filter connected between the phase comparison circuit and the oscillator with a corresponding time constant is provided in accordance with the advantageous embodiment of the invention specified in claim 2.

The determination of the size of the two sub-factors is determined not only by the desired output frequency range of the frequency divider but also by the fact that the frequency divider in question switches less often with increasing difference in the sub-factors and the realization of the time constant of the low-pass filter becomes increasingly difficult as a result. It is therefore advantageous to choose the highest possible frequency of switching from one sub-factor to the other, and thus the smallest possible integer difference of the sub-factors for a given offset frequency. The embodiment according to claim 3 represents an optimal solution.

An essential simplification of the device according to the invention consists in providing a single reference signal source for generating the reference signals of all television channels to be processed. As a result, a separate reference preparation is no longer necessary for each channel.

A particularly expedient embodiment of this inexpensive reference signal source is described in claim 5. At the exit of the device, the image carrier frequencies are generated in a CCIR grid in accordance with the standards in a simple and elegant manner. The frequency of 1 MHz does not necessarily have to be generated by an oscillator, but rather can also be derived in a simple manner from a master frequency emitted, for example, by normal frequency transmitters. In this case it is also possible to operate television transmitters or converters with a precision frequency and / or precision offset of the image carrier output signal regardless of the accuracy of the input IF frequency.

An alternative to this embodiment according to claim 5 is given in claim 6. The frequency divider for generating the 250 kHz signal is saved, but the comb generator is more complex.

If an individual offset for each channel is desired, this is easily possible according to claim 7 by connecting an offset signal either via an adder to the frequency divider in the reference IF branch or directly to the frequency divider in the IF branch.

Claim 8 specifies a simple, but nevertheless reliably functioning configuration of the device according to the invention with particularly low circuit complexity.

By a supplement according to claim 9, this circuit can process offset and / or offset signals of twice the frequency.

• Modul 1, bestehend aus den beiden Frequenzteilern, der Phasenvergleichsschaltung incl, Tiefpaß, dem Mischer und je einem Begrenzerverstärker zwischen Mischer und dem einen Frequenzteiler, sowie zwischen dem anderen Frequenzteiler und dem ZF-Anschluß,
• Modul 2, bestehend aus einem 1-MHz-Oszillator mit nachgeschaltetem Kammgenerator,
• Modul 3, bestehend aus Offset-Generator und mechanischem Umschalter,
• Modul 4, bestehend aus einem Frequenzteiler zur Generierung des 250-kHz-Signals aus dem 1-MHz-Signal,
• Modul 5, bestehend aus den Modulen 3 und 4, sowie einer Addierschaltung.

The image carrier processing device according to the invention, in particular due to the design according to claims 1 and 4, in contrast to the prior art, is ideally suited for use and inexpensive construction in a modular system. For this come z. B. Consider the following building blocks:

• Module 1, consisting of the two frequency dividers, the phase comparison circuit incl, low-pass filter, the mixer and a limiter amplifier between the mixer and the one frequency divider, and between the other frequency divider and the IF connection,
• Module 2, consisting of a 1 MHz oscillator with a downstream comb generator,
• Module 3, consisting of an offset generator and a mechanical switch,
• Module 4, consisting of a frequency divider for generating the 250 kHz signal from the 1 MHz signal,
• Module 5, consisting of modules 3 and 4, and an adding circuit.

This makes it possible to modify the processing device in a simple manner according to the needs of the individual case either for connection to the local transmitter or for frequency coupling in multi-channel systems, both with harmonic and with incremental coupling, without or with an offset. This simplifies both the application and the circuitry.

Overall, the invention creates an extremely simple and inexpensive, practical image processing system.

FIGS. 2 to 4 show an exemplary embodiment of the image carrier processing device according to the invention for multi-channel transmission in a BK system. 2 shows a block diagram of its basic structure, FIG. 3 the basic circuit diagram of a frequency divider and FIG. 4 the most important signals of this circuit in a pulse diagram.

The respective image carrier IF signal output at the input E by an input converter (not shown) and decoupled via a tap 1 is offset in a PLL control loop with a corresponding one derived from the mixer 2 of the PLL circuit from a reference image carrier signal frequency-shifted reference picture carrier IF signal is phase locked and converted back to the picture carrier frequency position at output A with an output converter 3, the mixer 4 of the output converter 3 being switched on between input E and output A and its oscillator 5 also being a control oscillator the PLL circuit works.

A digital frequency divider 7, 8 is now connected upstream of the two inputs of the phase comparison circuit 6 of the PLL circuit, the partial factor of which can be switched from 40 to 41 in time with a digital offset signal. So that the frequency divider 7, 8 processable, that is, from the Obtain modulation-independent signals, the IF signals to be compared each run through a corresponding limiter amplifier 9, 10. Without an offset signal, the frequency dividers 7 have the sub-factor 40, so that signals of the frequency 1/40 X f _{RefzF are} initially at the inputs of the phase comparison _{circuit 6} or 1/40 X f _ZF ; The frequency of the oscillator 5 is then traced via the PLL control loop until the two signals have the same phase and thus also the same frequency, namely 38.9 / 40 MHz = 972.5 kHz. The division of the intermediate frequency into this frequency range enables the phase comparison circuit 6 to be constructed from inexpensive CMOS components (here “HEF 4046 B”).

If an offset signal is now fed into one of the two frequency dividers, in the present exemplary embodiment into the frequency divider 7 located in the reference branch, its partial factor changes from 40 to 41 in time with this offset signal. With each switchover to the partial factor 41, the output signal period of this frequency divider is 7 larger than that of the other frequency divider 8, so that the PLL circuit adjusts. A low-pass filter 11 connected between phase comparison circuit 6 and oscillator 5 avoids that the oscillator frequency changes in time with the offset signal and the image carrier output signal is thereby frequency-modulated.

As already stated, the realization of the time constant of this low-pass filter 11 is the easier, the higher the switching frequency of the partial factor. For a given offset frequency, there is therefore an optimal dimensioning for a partial factor change from n to n + 1, in the present exemplary embodiment thus from 40 to 41.

By switching the partial factor as described, the trailing of the oscillator frequency and thus the desired positive (or, if the offset signal is fed into the other frequency divider 8, negative) frequency offset of the image carrier output signal by the offset frequency without using a subtractor (or, at negative frequency offset of an adder) realized.

This saving results in a further reduction in expenditure and costs of the inexpensive digital frequency dividers 7, 8 which are already made per se (from commercially available ICs). These work broadband for offset frequencies between approximately 0.2 and 800 kHz; In contrast to SSM, they do not have to be readjusted every time the offset frequency changes and are therefore particularly suitable for use in modular systems. A highly accurate 1 MHz oscillator 13 with a comb generator 14 connected downstream is provided as the reference signal source 12. However, the mixer 2 of the PLL circuit is only supplied with signals whose frequencies are integer multiples of 1 MHz. To generate exact reference image carrier frequencies according to the Gerber standard, the values of which all end at 0.25 MHz, the 1 MHz signal, which is coupled out of the comb generator via a filter, is converted into a 250 kHz by means of a frequency divider 15 with the partial factor 4 -Signal formed, which is fed to the frequency divider 7 via an adder 16 together with an offset signal supplied by a precision offset generator 17. All relevant television picture carrier frequencies are thus advantageously generated with a single reference signal source. The offset frequency of 10.45 kHz (= _8/12 x line frequency) is derived from a 5.35 MHz crystal by division using a binary divider and is accurate to 0.3 Hz.

The frequency dividers 7, 8 each contain the actual divider IC 18, as well as a synchronization circuit consisting of two identical (combined in one IC) JK flip-flops 19, 20 for clockwise control of the divider IC 18, which is connected in such a way that that the partial factor is 40, the switchover signal e having the signal state H (= high).

For a better understanding of the mode of operation, a circuit according to FIG. 3 is initially assumed, in which the circuitry which is unimportant for explaining the basic mode of operation and the EXOR gate 21 are omitted and the second JK flip-flop 20 is driven directly by the output signal d . If an L-H (low-high) edge now occurs at connection C in the course of the offset signal c, the first JK flip-flop 19 is set. With the help of the second JK flip-flop 20, the switching signal e for the divider IC 18 is synchronized with its output signal d. Since the switchover signal e must be stable during the H-L edge of the output signal d, the second flip-flop 20 is taken over on the L-H edge of the output signal d. As soon as the signal is accepted, the JK flip-flop 19 is deleted with the aid of the signal f; on the next L-H edge of the output signal d, the switchover signal e is switched back again. The system now remains in this state until the JK flip-flop 19 is set again by the next L-H edge of the offset signal c.

Since in this circuit the second JK flip-flop 20 always takes over the state of the first JK flip-flop 19 with an LH edge of the output signal d, the maximum frequency of the offset signal c, at which the divider is still working properly, is on half the output frequency, i.e. 38.9 / 41 MHz: 2 = 474 kHz limited. In the present exemplary embodiment, a frequency of 250 kHz is added to the offset frequency in an adder 16. For the sake of simplicity, this is done by means of a frequency doubler circuit, in whose signal only the pulses corresponding to the offset signal frequency remain by corresponding pulse suppression. However, this results in a frequency component of 2 x 250 kHz = 500 kHz, which is above the limit frequency mentioned. By turning on the EXOR gate 21 shown in FIG. 3, the second JK flip-flop 20 reset half a period earlier, thus ends the switching pulse shortly after the HL edge of the output signal d and can therefore take over a new switching command of the first flip-flop 19 on its next LH edge. The synchronization circuit can thus process offset frequencies of up to 948 kHz.

• « Referenzsignalquelle 12, « Ausgangsumsetzer » 3, « Phasenvergleicher 22 und « Versatzgenerator 23. Der Begrenzerverstärker 9 im Referenzzweig des Phasenvergleichers 22 ist zwar bei Verwendung einer Referenzsignalquelle 12 gemäß dem Ausführungsbeispiel nicht nötig, er macht jedoch das Modul 22 unabhängig von der Art der Referenzsignalquelle 12 allgemein einsetzbar.

The individual circuit elements are combined into the following modules, which are suitable for the construction of processing devices for all television picture carriers and different offset frequencies:

• "Reference signal source 12," output converter "3," phase comparator 22 and "offset generator 23. Although the limiter amplifier 9 in the reference branch of the phase comparator 22 is not necessary when using a reference signal source 12 according to the exemplary embodiment, it makes the module 22 independent of the type of the reference signal source 12 generally applicable.

The same applies to the mechanical changeover switch 24 of the offset generator 23, via which the offset signal can be switched to one of the two frequency dividers 7, 8, depending on whether a positive or negative offset is to take place.

Overall, the image carrier processing device described is extremely simple and cost-saving, can be used in a wide range without any significant amount of work and is suitable for advantageous modular construction.

Claims (9)

1. Device for editing picture carriers of television signals by phase-locked cross-coupling of the picture carriers by means of linking the individual picture-carrier frequencies in each case to a reference frequency and by a defined frequency offset between said signals, with a PLL-circuit consisting of a phase-comparison circuit (6), an oscillator (5) of which the frequency is regulated by the latter, and a thus controlled mixer (2), in which PLL-circuit the phase-comparison circuit (6) is driven, firstly, by the television standard intermediate-frequency signal derived from the respective information signal and, secondly, by the reference intermediate-frequency signal obtained by the mixer (2) from the oscillator signal and from a reference signal, said reference signal originating from a reference-signal source (12), said reference intermediate-frequency signal being shifted by the amount of the offset frequency produced by an appropriate generator (23), wherein one of two digital frequency dividers (7, 8) with identical basic dividing factors is series-connected with each of the two inputs (D) of the phase-comparison circuit (6), one of which (7) being driven in such a manner by the offset signal that its dividing factor changes in phase with the offset signal.

2. Device as defined in Claim 1, wherein connected between phase-comparison circuit (6) and oscillator (5) is a low-pass filter (22) whose time constant is such that the oscillator frequency is not changed in phase with the offset signal.

3. Device as defined in Claim 1 or 2, wherein the change in the dividing factor of the relevant frequency divider (7) is a changeoverfrom n to n + 1.

4. Device as defined in any one of Claims 1 to 3, wherein a single reference signal source (12) is provided to produce the reference signals of all television channels to be conditioned.

5. Device as defined in Claim 4, wherein the reference signal source consists of a high-precision 1-MHz oscillator (13) with series-connected standard tone generator (14), and wherein a 250-kHz signal is derived from the 1-MHz signal by means of a frequency divider (15) and is supplied to the frequency divider (7) inserted between mixer (2) and phase-comparison circuit (6).

6. Device as defined in Claim 4, wherein the reference signal source consists of a 250-kHz oscillator with series-connected standard tone generator.

7. Device as defined in Claim 5, wherein an offset signal is directly connected to the 250-kHz offset signal via an adder (16) or to the divider (8) connected between the phase-comparison circuit (6) and the intermediate-frequency connection (1 ).

8. Device as defined in any one of Claims 1 to 7, wherein each frequency divider (7, 8) contains two flipflops (19, 20) by means of which if necessary the offset signal and/or the offset signal is suppliable and which are interconnected with the frequency dividers (7, 8) in such a way that offset signal and divider output signal are synchronized and hence the dividing factor is changed over at the divider-dependently correct time.

9. Device as defined in Claim -8, wherein an EXOR gate (21) with its inputs is connected between the outputs (D) of each frequency divider (7, 8) and of the second flipflop (20) and drives the latter with its output signal.

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