Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Definitions

• This invention relates to random access memories, and more particularly to a static KOS random access memory cell utilizing no sense amplifiers.
• a static random access memory cell having improved read out capabilities, operating at low voltage with low quiescent current.
• a memory cell for storing data having a data signal line and a bit signal line for receiving control signals, first and second control lines for receiving control signals and a c ⁇ ll voltage supply source.
• a first transistor is interconnected to the data signal line and to . ' the bit signal line and is activated by a control signal.
• a second transistor is provided and is connected to the- first transistor and to the first control line for being activated by a control signal.
• a third transistor is provided and is connected to the first transistor and to the second control line for being activated by a control signal.
• a first inverter is coupled to the cell voltage supply and to the second and third transistors.
• a second inverter is coupled to the cell voltage supply and to the second and third transistors. The first and second inverters are cross- coupled to the second and third transistors for storing data within the memory cell.
• FIGURE 1 is a schematic circuit diagram of the memory cell of the present invention.
• FIGURE 2 is a schematic diagram of the cross-coupled inverters illustrated in FIGURE 1.
• Memory cell 10 is utilized as " part of an array of numerous such cells arranged in rows and columns in a conventional manner to form a random access memory.
• the random access memory thereby formed using memory cell 10 may be fabricated on a single semiconductor chip and is primarily intended for such fabrication utilizing metal-oxide-semiconductor technology.
• memory cells 10 When arranged in an array of memory cells, memory cells 10 are interconnected to a common data line 12. Data stored within a memory cell 10 is read from, memory cell 10 via data line 12 which is initially precharged using a data line input circuit (not shown) . Access from a memory cell 10 to data line 12 is provided by an access transistor 14. The gate of access transistor 14 receives the bit enable control signal via bit enable line 16. The bit enable control- signal selects a particular memory cell 10 along data line 12 which is to be read from or written into. The drain terminal of access transistor 14 is interconnected to data line 12. The source terminal of access transistor 14 is interconnected to the drain terminals of transistors 20 and 22. Transistors 20 and 22 are address transistors for memory cell 10. The gate terminal of address transistor 20 receives a control signal WRITE 0 via signal line 24. The gate terminal of address transistor 22 receives a control signal WRITE 1/READ via signal line 26.
• inverters 30 and 32 Interconnected across the source terminals of address transistors 20 and 22 are cross-coupled inverters generally identified by the numerals 30 and 32.
• the source terminal of transistor 20 is interconnected to the input of inverter 30 to form a node 34.
• the output terminal of inverter 30 is interconnected to the source terminal of transistor 22 to form a node 36.
• the input terminal of inverter 32 is interconnected to node 36.
• the output terminal of inverter 32 is interconnected tc node 34.
• the voltage level on data line 12 is pulled to a logic low by the data line input circuit.
• the bit enable control signal for the particular memory cell 10 being accessed will be pulled to a logic high, such that access transistor 14 will be activated.
• the WRITE 0 control signal is pulled high to activate transistor 20.
• the WRITE 1/READ control signal is low at this time, such that transistor 22 is inactive. Since access transistor 14 has been activated in addition to transistor 20, node 34 is pulled low to the value on data line 12, thereby storing a logic low value at node 34 within memory cell 10. '
• the WRITE 0 control signal is pulled low and the WRITE 1/READ control signal pulls signal line 26 high, to thereby activate transistor 22.
• node 36 is pulled low to the value of data line 12.
• the value on node 36 is then inverted by inverter 32 to store a logic high at node 34, thereby storing a logic high within memory cell 10.
• data line 12 is initially precharged to a logic high.
• the bit enable control signal for the particular memory cell 10 being accessed is pulled high such that access transistor 14 is activated.
• the control signal WRITE 1/READ pulls signal line 26 high, such that transistor 22 is activated.
• the voltage level stored at node 36 will then control the voltage level on data line 12. If a logic high was stored in node 36, since transistors 14 and 22 are activated, the initialized precharged value on data line 12 will remain high to thereby read a logic 1. If a logic 0 were stored in node 36, the voltage on data line 12 will be pulled low through transistors 14 and 22 to thereby indicate that a logic 0 was stored in node 36.
• FIGURE 2 illustrates circuitry comprising inverters - 30 and 32 which may comprise, for example, CMOS inverters. Inverter 30 includes transistors 40 and 42.
• transistors 40 and 42 are interconnected to node 34.
• the drain terminals of transistors 40 and 42 are interconnected to node 36.
• Inverter 32 includes transistors 44 and 46.
• the gate terminals of transistors 44 and 46 are interconnected to node 36.
• the drain terminals of transistors 44 and 46 are interconnected to node 34.
• Transistors 40 and 44 may comprise, for example, P-channel MOS transistors.
• Transistors 42 and 46 may comprise, for example, N-channel MOS transistors.
• present memory cell 10 having no sense amplifiers, operates with low quiescent current. Additionally, the present memory cell 10 operates at low voltages.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Static Random-Access Memory (AREA)

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• 1980
  • 1980-12-24 WO PCT/US1980/001725 patent/WO1982002277A1/en unknown
  • 1980-12-24 EP EP19810901723 patent/EP0067816A1/de not_active Withdrawn

Non-Patent Citations (1)

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