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EP0051531B1 - Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit - Google Patents

Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit Download PDF

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Publication number
EP0051531B1
EP0051531B1 EP81401716A EP81401716A EP0051531B1 EP 0051531 B1 EP0051531 B1 EP 0051531B1 EP 81401716 A EP81401716 A EP 81401716A EP 81401716 A EP81401716 A EP 81401716A EP 0051531 B1 EP0051531 B1 EP 0051531B1
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EP
European Patent Office
Prior art keywords
current
integrator circuit
circuit
event
charging
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Expired
Application number
EP81401716A
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English (en)
French (fr)
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EP0051531A1 (de
Inventor
Michel Geesen
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Thales SA
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Electronique Serge Dassault SA
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Priority to AT81401716T priority Critical patent/ATE13780T1/de
Publication of EP0051531A1 publication Critical patent/EP0051531A1/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time
    • G04F10/105—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time with conversion of the time-intervals
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC

Definitions

  • the invention relates to a dating device according to the preamble of claim 1.
  • This time interval is determined by dating the respective arrival of each of these laser pulses on the satellite using a clock with which the satellite is provided and by measuring the difference between the two corresponding dates. This last measurement can be carried out on the ground using the information retransmitted by the satellite on the respective dates of arrival of the two pulses.
  • the present invention solves this problem and allows dating with very high precision events such as the arrival of a laser pulse on a satellite.
  • the present invention starts from a device as defined above, characterized in that it includes a reference clock supplying tooth pulses that which immediately follows the pulse representative of the first event is taken as reference this time of the second event, in that the discharge means act at the latest as soon as the load is interrupted by the switching means, and in that the switching means comprise two active switching members, substantially identical, mounted respectively and separately in series on the independent circuit and on the integration circuit, and controlled in opposition by the control means.
  • the charge signal is composed by the superposition of the first predetermined current and a discharge current, of much smaller amplitude and in the opposite direction to the first current, which is applied to the integration circuit from the start of the charging period.
  • a discharge current of much smaller amplitude and in the opposite direction to the first current, which is applied to the integration circuit from the start of the charging period.
  • the pre mier predetermined current is again switched to pass through the first circuit and the discharge current remains applied at least until the end of the discharge period of the integration circuit.
  • the control of this discharge current outside of the charge and discharge periods can be carried out using a switching device which establishes a short circuit at the terminals of the integration device through which the current flows. discharge outside the operating periods of the latter.
  • provision is made to regulate the first predetermined current in order to maintain the current flowing through the first circuit at a constant level at the output of the first switching member to compensate for variations in the electrical characteristics of the latter.
  • this indirectly provides regulation of the level of current at the output of the second switching device in the integration circuit during short periods of operation under load of the latter.
  • a delay circuit is provided for delaying the instant of interruption of the charge (and therefore the start of the discharge) of the integration circuit for a time. at least equal to the time taken by the latter to reach a linear charge regime after the reception of the pulse representative of the event to be dated.
  • the duration of discharge of the integration circuit provides a measure of the time interval separating the arrival of the event to date from the clock pulse which immediately follows.
  • means are used for timing this discharge duration for counting the pulses of the reference clock employed for locating the pulse representative of the event to be dated.
  • the discharge duration is preferably read by letting these counting means operate continuously and by reading the instantaneous state of the counter at the beginning and at the end of the discharge period in response to the corresponding signals.
  • the invention is advantageously used for dating laser pulses received by a satellite, in particular for the synchronization of atomic clocks located at separate sites on the ground.
  • Satellite S which can be a “spinned” satellite, that is to say stabilized by rotation, comprises an optical apparatus 21 (FIG. 2) suitable for projecting onto a photoelectric converter 22 a laser brush coming from one and / or the other of a multiplicity of stations P1, P2, P3, etc., each equipped with a clock, for example an atomic clock.
  • the purpose of the installation is to synchronize said clocks by determining the time interval which separates a pulse from one clock from a pulse from another clock, in order to determine the synchronism difference between the clocks.
  • the converter 22 can comprise a photodiode or other single photoelectric cell, as shown, or else a multiplicity of photodiodes, each of which is assigned to a wavelength used by one or more transmitting stations.
  • Each station P emits a laser pulse in a time slot assigned to it, and advantageously benefits from a multiplicity of slots, for example, one hundred, so that the measurement corresponds to an average of measurements.
  • the emissions of laser pulses by each of the stations are dated using their atomic clock and the installation carried by satellite S aims to date the arrival of a laser pulse emitted by a station and the arrival from that issued by another station so that it is possible to know the time interval separating these arrivals and to make on the atomic clocks of one and / or the other station the adjustments required to bring these last in exact synchronism to take account of their offset or to be informed about the value thereof.
  • the information on the instant of impact of each laser pulse on the satellite S, instant determined by reference to clock signals available on the satellite is, for this purpose, sent by telemetry each of the stations or, preferably , to a station central C linked by telemetry not only to satellite S but also to the various stations.
  • the optical equipment 21 comprises a reflector for reflecting towards each station the laser brush that it receives from said station.
  • the measurement at each station, for example at said station P1, of the time interval which separates the instant of emission from the pulse of the echo thus received by reflection provides information on the travel time of l pulse between said station and the satellite.
  • the optical apparatus 21 comprises means for directing the laser energy reaching the satellite towards a photodiode 22 through an optic such as a lens not shown.
  • the electrical output 24 of the photodiode 22 is connected through an amplifier-detector 25 to an input CE27 of a flip-flop 28 of type D, the input D29 of which is fixed at a stable level equivalent to a logic level 1 permanently.
  • the flip-flop 28 has a reset input R30 and two outputs, direct and reverse, respectively Q31 and Q32.
  • the output Q31 of the flip-flop 28 is connected, on the one hand, to a control input 35 of a switching circuit 36 of its own, in a first condition, short-circuiting two terminal terminals 37 and 38 and, in a second condition, to interrupt the short circuit between terminals 37 and 38.
  • the output Q31 is also connected to the input D40 of a flip-flop 41 of type D, by a link 33.
  • the flip-flop 41 receives on its clock input CE42 of the output signals of an amplifier 43, itself supplied by a clock circuit 44, operating in the example chosen at a frequency of 15 MHz.
  • the flip-flop circuit 41 includes an output Q45 connected, through a delay circuit 46, which can be constituted by a series connection of two logic gates, to an input 47 of an OR gate 48 whose other input 49 is connected to the output Q32 of the flip-flop 28.
  • the output of the delay circuit 46 is also connected to an interface circuit 50 by a link 51 transmitting to this circuit information known as the start of conversion. Given the operating time of the interface 50, it is also possible to connect the line 51 upstream of the delay circuit 46. From this interface 50 comes a line 53 for resetting to zero reset connected to the input R30 of flip-flop 28.
  • the interface 50 also receives on an input 54 signals from an inverting output 55 of the clock signal amplifier 43. This interface also has a certain number of outputs which will be explained below. .
  • the OR gate 48 has a direct output 58 and an inverting output 60, the first output 58 being connected to the base 61 of an NPN type transistor Q71 while the inverting output 60 of the OR gate 48 is connected to the base 62 of a transistor Q72 chosen to have characteristics as close as possible to those of transistor Q71.
  • These two transistors Q71 and Q72 have their transmitters connected in common to a terminal 65 of an adjustable current generator 66 supplying a current designated hereinafter by the letter I.
  • the generator 66 is connected to a voltage source which, in the example considered, is -15 volts.
  • the nominal current of generator 66 is approximately 20 milli-amperes in this example.
  • the current generator 66 has an input 68 capable of receiving a voltage signal from a comparison circuit 70 controlling the level of current supplied by this generator for regulatory purposes as will be explained below.
  • the comparison circuit 70 receives on its input 73 a voltage signal taken from the collector 75 of the transistor Q71 to which this input 73 is connected.
  • the comparator circuit 70 has a second input 74 capable of receiving a reference voltage stabilized by a Zener diode and providing a reference from which the current level of the generator 66 is regulated.
  • the collector 75 of transistor Q71 is connected to ground M via a resistor R78. An input terminal 37 of the switching circuit 36 is also grounded.
  • the collector 76 of the transistor Q72 is directly connected to the terminal 38 of the switching circuit 36, this terminal 38 being itself connected to one end of a second constant current generator 80, the other end 81 of which is connected to a source voltage, for example + 12 volts.
  • This generator 80 is capable of producing a current to which reference will be made below under the designation i, i being in the example chosen of an order of magnitude of 20 micro-amps, that is to say approximately one thousand times weaker than current 1.
  • a capacitor C84 is also connected between terminals 37 and 38, its armature 85 being connected to terminal 37 and therefore to ground, while its armature 86 is connected to terminal 38.
  • This armature 86 is also connected to the input of a level detector 88 whose output 90 is connected, on the one hand to an end of conversion line 92 suitable for transmitting information when the discharge of the capacitor C84 has ended, and on the other hand, via a line 94, to an input 95 of the switching circuit 36 in order to re-establish the connection between the terminals 37 and 38 as soon as a signal appears on the output 90 of the comparator or detector of level 88.
  • the input 35 of the switching circuit 36 is connected (FIG. 6) to an armature of a capacitor 103, the other armature of which is connected to the base 104 of a PNP transistor 105 and, through a resistor 107 to the input 95 of circuit 36 from output 90 of detector 88.
  • a resistor 110 connected between a source of negative potential (-v) and the base 104 forms with the resistor 107 a bias circuit of this base at a sufficiently low value, when the detector 88 is at rest, so that the transistor 105, whose emitter 111 is connected to junction 37 and the collector 113 to junction 38 through a resistor 112, or passing.
  • the transistor 105 short-circuits the capacitor C84 maintaining only between the plates 85 and 86 a residual voltage equal to the drop in. current of the resistor 112.
  • This drop in potential is always greater than the offset voltage of the comparator 88 in order to allow a frank switching of the latter when a charge signal from the capacitor is applied to its negative input 120, l positive input 121 being connected to ground.
  • FIG. 2 Detailed operation will be clearly understood if reference is made to FIG. 2 at the same time as to the signal diagrams represented in FIG. 5.
  • the switching circuit 36 Before receiving a laser pulse, the switching circuit 36 is in its closed position (level 0 in diagram A of FIG. 5).
  • the Q31 output is at level 0, Q32 being at level 1 ( Figure 5 C).
  • the clock 44 produces a crenellated signal H, as shown in FIG. 5 D, on the input CE42 of the flip-flop 41; the output Q45 of this rocker is on level 0; the base of Q71 is supplied by the output Q32 of the flip-flop 28 through the OR gate 48, which keeps the transistor Q71 in the conducting state.
  • the base of Q72 is not supplied and this latter transistor is blocked (FIG. 5G).
  • the capacitor C84 is discharged, its armatures being short-circuited by the switching circuit 36 (FIG. 5H).
  • Terminal 38 is therefore now connected to current generator 66 and capacitor C84, the armatures of which are no longer short-circuited, begins to charge negatively (Figure 5H) under the effect of a current equal to (Ii ) if we ignore for the moment the base emitter current of transistor Q72.
  • the signal of the output Q31 (FIG. 6) charges the capacitor 103 at a level which causes the transistor 105 to switch off. Under the effect of the charge of the capacitor C84, the level voltage at the output of detector 88 rises and confirms by input 95 the non-conduction polarization of base 104.
  • the capacitor C84 begins to discharge under the effect of the current i, the current I being deflected by the transistor Q71.
  • This discharge is represented in FIG. 5H by the line of low positive slope which, in reality is about a thousand times less inclined than the straight line of negative slope charge preceding it.
  • the duration of this discharge is timed by means which will be explained below.
  • the return of the armature 86 to a potential level close to 0, causes the output voltage 90 of the detector 88 to drop.
  • the voltage of the base 104 drops and the transistor 105 allows sufficient current to pass through to prevent capacitor C84 from charging substantially in the opposite direction under the action of current i at an undesirable level.
  • the fallout of the output voltage 90 of the detector 88 controls the transfer of the dating information in a memory described below, and at the end of this, the resetting of the flip-flop 28 whose outputs Q31 and Q32 change state and cause, on the one hand, the return to its resting voltage of the capacitor C84 and on the other hand, to the next clock signal, the delivery of the output Q45 to its initial state.
  • the capacitor C84 is returned to its resting voltage when the output Q31 returns to its initial state by reducing the bias voltage of the base 104 to a level which restores the full conduction of the transistor 105 (FIG. 6).
  • the clock signal specific to the satellite from circuit 44 for example, is 15 MHz
  • the corresponding period between two clock fronts is very large compared to the accuracy, one nanosecond or less, required to date the arrival of the above-mentioned laser pulses.
  • the circuit which has just been described makes it possible to locate in time the position of the arrival of such a pulse between two successive clock fronts, such as FA on the Figure 5 D, by measuring the discharge time of the capacitor. This time is, in fact, very long and can be measured by counting a corresponding number of slots of this same clock.
  • the capacitor discharge rate is a thousand times lower than the latter's charge rate
  • the charge level corresponding to the continuous integration between two successive clock slots will be discharged over an expanded time interval corresponding to a thousand slots of this same clock. If the timed discharge time corresponds for example to 600 slots, it is deduced therefrom that the laser pulse had been received at an instant preceding the arrival of the clock signal which triggered the discharge by an interval equal to sixty percent ( 60%) of the period of this clock to within a constant depending on the delay 8.
  • the curve representing the charge of the capacitor C84 is shown in FIG. 4. It has an initial non-linear part a, followed by a tinear part b. Charging continues until the time H of arrival of the delayed clock signal on the input 47 of the OR gate 48. The transistor Q72 is blocked, while the transistor Q71 is turned on and the capacitor C84 is discharged linearly.
  • the dotted line is shown in FIG. 4, on the right of the theoretical charge of the capacitor C84 after the arrival of the laser pulse at time t 1 .
  • the theoretical and real charge and discharge curves have also been shown for a laser pulse arriving at time t 2 .
  • the signals at the end of the conversion are provided respectively at times T 1 and T 2 for the real curves (solid line) and T ' 1 and T' 2 for the theoretical curves (dotted line).
  • T 1 -T 2 T ' 1 T' 2 and therefore that the dating information corresponds to the theoretical conditions as long as the clock signal passing from fast charge to slow discharge occurs on a straight part of the charge curve.
  • the delay circuit 46 shown in FIG. 2 has the function of delaying the application to the OR gate 48 of the clock signal immediately following the arrival of the laser pulse for a time ⁇ at least equal to the time 8 necessary for the capacitor C84 to acquire a linear charge regime.
  • the instant H at which the transistors Q71 and Q72 are switched to approach the discharge of C84 is therefore always separated from the arrival of the laser pulse by an interval ⁇ which can be taken for example, equal to tenth of the period of the clock 44.
  • the discharge cannot start at a point on a non-linear portion of the charge curve of the capacitor C84.
  • the number of pulses counted during the discharge of the capacitor may be slightly greater than K, K being the expansion factor of the time scale used to date the reception of a laser pulse between two pulses clock.
  • transistors Q71 and Q72 are used having characteristics as close as possible .
  • the charging current of capacitor C84 is not strictly equal to the difference (1-i) of the currents from generators 66 and 80, but to the difference between the collector current (point 76) of transistor Q72 and current i.
  • This collector current is itself equal to the difference of current 1 and of base-emitter current of transistor Q72. Since the base-emitter current of this transistor may vary, the current I is regulated and, since the transistor Q72 only comes into operation for short periods, regulation of the collector current 071 is preferably carried out.
  • the collector voltage (voltage at point 75) is taken by comparator 70 and compared to a reference voltage admitted on input 74 of this comparator.
  • the current of the generator 66 is adjusted as a function of the error signal appearing at the output of the comparator 70.
  • the collector voltage signal is representative of the collector current passing through the resistor R78. Since the transistors Q71 and Q72 are very close to each other, as regards both their environment and their characteristics, the compensation of the current I, to take account of variations in the base-emitter current of one, is suitable , except for a very small error, to take account of variations in the base-emitter current of the other. When the transistor Q72 goes into conduction, its collector current, which ensures the charge of the capacitor C84 in combination with the current i is thus well maintained at a constant value, with an accuracy dependent on that of the reference voltage Zener on the entry 74.
  • the interface 50 of FIG. 2 has a role of conversion or adaptation of the signals produced or received by the circuits shown, which are produced in ECL logic, in a TTL or C MOS logic, in which the other portions are found. of the information processing and dating system according to the invention.
  • a reset reset signal is applied to the input 205 of the interface, which causes the flip-flop 28 to be reset by the line 53.
  • An output 201 of the interface 50 supplies the clock signals to frequency signals present on line 54.
  • An output 203 transmits outside the interface a conversion start signal as soon as such a signal appears on line 51.
  • line 92 connected to the output of the detector level 88 transmits an end of conversion signal as explained above.
  • the measurement circuit represented in this figure is intended for timing the discharge time of the circuit of the capacitor C84 under the action of the discharge current.
  • a counter 221 is supplied on its input 223 by the clock pulses coming from the output 201 of the interface 50 at the frequency of these pulses at the input of the flip-flop 41.
  • This counter "rotates" freely, this is that is, it counts continuously from its initial value to its maximum capacity, after which it resumes counting at its initial value and so on, and this as long as it receives pulses d 'clock. It is connected, by a multi-bit link 219, to two registers 218 and 229.
  • the register 218 has a control input 217 connected to the output 203 of the interface 50 to read in the register 218 the content of the counter when the the conversion start pulse is generated at the output 203 of the interface 50.
  • the register 229 is suitable for reading the state of the least significant stages, for example twelve in number, of the counter 221 when its input 231 receives the indication of the end of conversion signal from line 92 of FIG. 2. It therefore records the instantaneous state of these least significant stages of the counter 221 at the moment when the end of the discharge is detected.
  • the outputs of registers 218 and 229 are respectively connected to the inputs 225 and 234 of a writing device which introduces the contents of the two registers 218 and 219 into a memory 237 by a line 235 connecting the output of the writing device to the entry 236 of this memory.
  • the memory 237 is associated with a reading device 238 which controls the serial output of the information stored on an output 242 via a control line 240.
  • This reading circuit comprises two inputs, a timing input 241 and a transfer authorization input 239 to allow control by the read circuit of the bit-by-bit transfer out of the memory on the output 242.
  • serial output bits on line 242 are transmitted by telemetry to a ground station responsible for centralizing the information necessary for synchronizing the clocks.
  • the very high operating precision of the dating circuit which has just been described makes it possible to take advantage of very large time scale expansion ratios, greater than 500 and possibly exceeding one thousand, for measuring the time separating the arrival. of the pulse to date from the next clock pulse.
  • Such expansion factors which result from the ratio between the charge and discharge rate of the capacitor used for expansion would be illusory in the absence of very high precision in time of the switching operations linked to the dating, precisions authorized by the various implementation characteristics which have been described.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Optical Radar Systems And Details Thereof (AREA)
  • Pulse Circuits (AREA)
  • Time Recorders, Dirve Recorders, Access Control (AREA)
  • Gyroscopes (AREA)
  • Electric Clocks (AREA)

Claims (11)

1. Einrichtung für die Datierung eines ersten Ereignisses bezogen auf ein zweites Ereignis, bestehend aus:
- Einer Integrationsschaltung (76, 38, C84, M);
- Vorrichtungen für die Aufladung (66) dieser Integrationsschaltung die geeignet sind, einen vorbestimmten Strom (I) zu erzeugen;
- Schaltvorrichtungen (Oder Gatter 48, Q71, Q72), die zwei Schaltzustände haben und geeignet sind, im ersten Zustand den vorbestimmten Strom (I) in die Integrationsschaltung und im zweiten Zustand diesen Strom (I) in einen Ableitkreis (75, R78, 37, M), welcher von der Integrationsschaltung unabhängig ist, fliessen zu lassen;
- Entladevorrichtungen (80) für die Integrationsschaltung die, bezogen auf die Aufladegeschwindigkeit, eine niedrige Entladegeschwindigkeit sicherstellen;
- Steuereinrichtungen (28, 41, 46) um die Schaltvorrichtungen in den einen oder anderen der vorgenannten Zustände zu bringen. Diese Steuereinrichtungen setzen die Schalteinrichtungen, als Antwort auf einen Impuls, der das erste Ereignis darstellt, in ihren ersten Zustand um die Integrationsschaltung (76, 38, C84, M) aufzuladen, und sie setzen die Schaltvorrichtungen als Antwort auf einen Impuls, der das zweite Ereignis darstellt, in ihren zweiten Zustand, um die Aufladung zu unterbrechen; und
- Messmitteln (88, 221, 218, 229, 226, 237, 238) die auf die Entladung der Integrationsschaltung (C84) reagieren, um die Zeit zwischen den beiden Ereignissen zu bestimmen. Diese Messmittel messen die Zeitdauer an deren Ende die Integrationsschaltung einen vorbestimmten Entladezustand erreicht hat. Diese Messmittel sind dadurch gekennzeichnet, dass sie eine Referenzuhr enthalten (44), die Impulse liefert, unter denen sich derjenige befindet, der unmittelbar auf den Impuls folgt, der das erste zu datierende Ereignis darstellt und als Referenzzeit für das Ereignis herangezogen wird, weiterhin sind diese Messmittel dadurch gekennzeichnet, dass die Entladeeinrichtung (80) spätestens nach Unterbrechung der Aufladung durch die Umschalteinrichtung (Oder Gatter 48, Q71, Q72) einsetzt zu arbeiten, und sie sind dadurch gekennzeichnet, dass die Umschaltvorrichtungen zwei aktive Schaltelemente (Q71, Q72) enthalten, die einander sehr gleichen, die getrennt hintereinander in die unabhängige Schaltung (75, R78, 37, M) und in die Integrationsschaltung (76, 38, C84, M) eingefügt sind und durch die Steuermittel (28, 41, 46) entgegengesetzt geschaltet werden.
2. Einrichtung entsprechend dem Anspruch 1, die dadurch gekennzeichnet ist, dass die genannten Lademittel einen Stromgenerator (66) enthalten, der an einen gemeinsamen Punkt (65) der genannten unabhängigen Schaltung und der genannten Integrationsschaltung angeschlossen ist, und zwar vor den genannten Schaltmitteln (Q71, Q72).
3. Einrichtung entsprechend dem Anspruch 2, dadurch gekennzeichnet, dass sie einen Amplitudendetektor (70) für den Strom, der durch die unabhängige Schaltung (R78) fliesst, enthält und der vor dem Schaltorgan (071) an das die unabhängige Schaltung angeschlossen ist, angeordnet ist. Der genannte Stromgenerator (66) ist regelbar und zwar über diesen Amplitudendetektor der Stromstärke (70), so dass der genannte Strom auf einem stabilen Wert, unabhängig von eventuellen Schwankungen der elektrischen Eigenschaften der genannten Schaltmittel, gehalten wird.
4. Einrichtung entsprechend dem Anspruch 1, dadurch gekennzeichnet dass die beiden Schaltorgane aus zwei Transistoren Q71 und Q72 bestehen und deren Emitter beide mit Punkt 65 der Integrationsschaltung und der unabhängigen Schaltung verbunden sind, und deren Basen (61, 62) mit zwei Ausgängen (58, 60) eines Logik Gatters (Oder 48), geeignet für die Erzeugung von zwei invertierten logischen Signalen, verbunden sind, wobei das genannte logische Gatter am Eingang der Steuermittel angeschlossen ist.
5. Einrichtung entsprechend einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Schaltmittel (28, 41, 46) geeignet sind die Entladung der genannten Integrationsschaltung zu bewirken, sobald das Ladesignal unterbrochen wird.
6. Einrichtung entsprechend einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass sie einen Generator für den Entladestrom (i) umfasst, dessen Amplitude sehr weit unter der des vorbestimmten Stromes (I) liegt, und dadurch, dass die Steuereinrichtungen (28, 41, 46, 36) geeignet sind, diesen Entladestrom (i) in die Integrationsschaltung einzuführen (C84), und zwar vom Beginn der Aufladung der Integrationsschaltung an, wobei dieser Strom in der Richtung dem eingeprägten Strom (I) entgegengesetzt ist, während die Entladung der Integrationsschaltung durch die Feststellung eines vorbestimmten Entladeniveaus (88) unterbrochen wird (36).
7. Einrichtung entsprechend dem Anspruch 6, dadurch gekennzeichnet, dass die Steuereinrichtungen (28, 41, 46, 36) eine Umschaltvorrichtung (36) für den Entladestrom (i) umfassen, die geeignet ist, in einer ersten Stellung die Integrationsschaltung (C84) kurzzuschliessen und in einer zweiten Stellung den Entladestrom (i) durch die Integrationsschaltung hindurchfliessen zu lassen.
8. Einrichtung entsprechend einem beliebigem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die Schalteinrichtungen unter anderem ein erstes Flip-Flop (28) enthalten, das als Reaktion auf den genannten Impuls, der das erste Ereignis darstellt, umgeschaltet wird und ein zweites Flip-Flop (41), das als Reaktion auf die Ankunft des Impulses, der das erste Ereignis darstellt, vorbereitet wird, um als Reaktion auf das Eintreffen des Impulses, der das zweite Ereignis darstellt, die genannten Schaltorgane (Q71, Q72), welche von den erwähnten beiden Flip-Flops gesteuert werden, umzuschalten.
9. Einrichtung entsprechend einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die Steuereinrichtungen (28, 41, 46, 36) eine Verzögerungsschaltung (46) enthalten, die geeignet ist, die Aufladung der Integrationsschaltung für eine Dauer zu verzögern, die mindestens der Zeit entspricht, die diese Integrationsschaltung benötigt, um in den linearen Teil ihrer Ladekurve zu gelangen.
10. Einrichtung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, dass die genannten Vorrichtungen (88, 221, 218, 229, 226, 237, 238) für die Zeitmessung Einrichtungen umfassen (221), die die Impulse der Referenzuhr zählen.
11. Einrichtung entsprechend dem Anspruch 10, dadurch gekennzeichnet, dass die Mittel für die Zeitmessung unter anderem Vorrichtungen umfassen (228), die es erlauben, den jeweiligen Stand dieser Zähleinrichtungen (221) am Anfang und am Ende der Entladephase abzulesen, ohne die Funktion der genannten Zähleinrichtungen, bezogen auf die genannten Impulse der Referenzuhr zu ändern.
EP81401716A 1980-10-31 1981-10-27 Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit Expired EP0051531B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81401716T ATE13780T1 (de) 1980-10-31 1981-10-27 Einrichtung zur genauen datierung eines ereignisses bezueglich einer referenzzeit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8023404A FR2493553A1 (fr) 1980-10-31 1980-10-31 Appareillage pour la datation precise d'un evenement par rapport a une reference de temps
FR8023404 1980-10-31

Publications (2)

Publication Number Publication Date
EP0051531A1 EP0051531A1 (de) 1982-05-12
EP0051531B1 true EP0051531B1 (de) 1985-06-12

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EP81401716A Expired EP0051531B1 (de) 1980-10-31 1981-10-27 Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit

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US (1) US4408895A (de)
EP (1) EP0051531B1 (de)
AT (1) ATE13780T1 (de)
CA (1) CA1171290A (de)
DE (1) DE3170949D1 (de)
ES (1) ES8300207A1 (de)
FR (1) FR2493553A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3332485A1 (de) * 1983-09-08 1985-03-28 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur messung von zeiten
DE3332484A1 (de) * 1983-09-08 1985-03-28 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur messung kurzer zeiten
US4516861A (en) * 1983-10-07 1985-05-14 Sperry Corporation High resolution and high accuracy time interval generator
JPH02297021A (ja) * 1989-05-12 1990-12-07 Nippon Soken Inc 物理量測定装置
FR2730830B1 (fr) * 1995-02-22 1997-06-06 Dassault Electronique Chronometrie electronique tres precise d'un evenement
DE69707851T2 (de) * 1996-04-02 2002-05-16 Lecroy Corp., Chestnut Ridge Verfahren und vorrichtung zum hochgenauen messen von zeitintervallen

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983481A (en) * 1975-08-04 1976-09-28 Ortec Incorporated Digital intervalometer
US4104590A (en) * 1976-11-30 1978-08-01 Sergei Vasilievich Zhevnerov Digital device for measuring instantaneous parameter values of slowly varying processes
US4301360A (en) * 1979-10-25 1981-11-17 Tektronix, Inc. Time interval meter
US4339712A (en) * 1980-05-01 1982-07-13 The Boeing Company Method and system for measuring width and amplitude of current pulse
US4362394A (en) * 1980-09-30 1982-12-07 Marconi Instruments Limited Time interval measurement arrangement

Also Published As

Publication number Publication date
US4408895A (en) 1983-10-11
CA1171290A (en) 1984-07-24
ATE13780T1 (de) 1985-06-15
EP0051531A1 (de) 1982-05-12
FR2493553A1 (fr) 1982-05-07
FR2493553B1 (de) 1985-05-03
ES506724A0 (es) 1982-10-01
DE3170949D1 (en) 1985-07-18
ES8300207A1 (es) 1982-10-01

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