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EP0050301A1 - Circuit d'attaque pour un relais bistable - Google Patents

Circuit d'attaque pour un relais bistable Download PDF

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Publication number
EP0050301A1
EP0050301A1 EP81108279A EP81108279A EP0050301A1 EP 0050301 A1 EP0050301 A1 EP 0050301A1 EP 81108279 A EP81108279 A EP 81108279A EP 81108279 A EP81108279 A EP 81108279A EP 0050301 A1 EP0050301 A1 EP 0050301A1
Authority
EP
European Patent Office
Prior art keywords
flip
circuit
flop
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81108279A
Other languages
German (de)
English (en)
Other versions
EP0050301B1 (fr
Inventor
Hiromi Nishimura
Yoshie Watari
Yuusaku Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SDS Elektro GmbH
Panasonic Electric Works Co Ltd
Original Assignee
Euro Matsushita Electric Works AG
SDS Elektro GmbH
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14353680A external-priority patent/JPS5767246A/ja
Priority claimed from JP14353780A external-priority patent/JPS5767247A/ja
Priority claimed from JP8322981A external-priority patent/JPS57199134A/ja
Application filed by Euro Matsushita Electric Works AG, SDS Elektro GmbH, Matsushita Electric Works Ltd filed Critical Euro Matsushita Electric Works AG
Priority to AT81108279T priority Critical patent/ATE8944T1/de
Publication of EP0050301A1 publication Critical patent/EP0050301A1/fr
Application granted granted Critical
Publication of EP0050301B1 publication Critical patent/EP0050301B1/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/22—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
    • H01H47/226—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil for bistable relays

Definitions

  • the invention relates to a driver circuit for a bistable relay, which maintains its respective position even when the excitation voltage disappears after the relay has responded and switched.
  • this type of relay does not require excitation direct current for the relay coil in order to hold the relay in the respective position.
  • Corresponding driver or control circuits are known, for example, from Japanese Utility Model Publication No. 48 702/1977 (hereinafter referred to as the first prior publication) and from German Patent No. 1,279,777 (hereinafter referred to as the second prior publication).
  • circuits are designed so that a capacitor and a bistable relay are connected in series to a supply voltage of 100 to 200 volts, so that when a switch is closed, a direct current flows through the coil of the relay to be actuated until the capacitor is charged after a predetermined time is and interrupts the current, after which the bistable relay is then held mechanically in a respective position.
  • the switch When the switch is opened, the capacitor discharges, so that the discharge current flows in the opposite direction through the relay coil and through a semiconductor switch, such as a transistor, so that the relay changes position.
  • the arithmetic unit could switch the relay in a very short time, for example 100 f.s, through 8 output bits. Meanwhile, the time required for switching the bistable relay is i.e. the time period during which the relay coil has current flowing through it, 100 ms, is therefore considerably longer than the previously mentioned time.
  • bistable relay cannot follow such a rapid switching command. A circuit that takes this into account is not provided.
  • the invention has for its object to provide a driver circuit for a bistable relay, which not only solves the problem mentioned above, but includes a new development in manufacture and application in such a way that the first and the second input signal influence a flip-flop that first control signal and the inverse control signal alternately emitted, supplied to a timer and used as time-limiting output signals, so that even if the first and second input signals are extremely short, a semiconductor circuit is driven and for the necessary duration of an operating current to switch the polarized Relay remains switched on, which takes into account the high speed of the changeover signal.
  • Another object of the invention is to provide a driver circuit for a bistable relay, in which the flip-flop contains a delay circuit for suppressing interference signals on the input side, so that faulty switching of the relay is prevented.
  • Another object of the invention is to provide a driver circuit for a bistable relay which is provided with a flip-flop which has two series circuits comprising a delay circuit and contains a logic element, wherein an input / output connection of one of the series circuits is fed back to an input / output connection of the other series circuit, so that when the logic levels of both outputs temporarily assume the same value, set and reset signals of the same duration for the Timers are generated and the first and the second input signal is distinguished from interference signals.
  • Another object of the invention is to provide a driver circuit for a. to provide a bistable relay which includes a timer which comprises flip-flops connected in series in stages and a multivibrator which periodically supplies an oscillation signal to the flip-flop of the first stage, while the output signal of the flip-flop of the last stage stops the multivibrator and forms the output signal of the timer , wherein gate circuits are provided which block the reception of successive input signals and thereby suppress the subsequent signals which are applied to the bistable relay during its work.
  • Another object of the invention is to provide a bistable relay driver circuit that detects a supply voltage at a semiconductor switch and maintains the flip-flop in a predetermined stable state when the supply voltage is below the predetermined discriminator level so that the flip-flops even if for example, the power supply is interrupted while the relay is operating, always be kept in the reset state, thereby preventing the reset condition from being for only one of a number of relays is present.
  • the driver circuit for a bistable relay comprises a semiconductor circuit 1 which contains a bistable relay 2 with a single coil. If an excitation current flows in the direction of the arrows 4, 5 in this relay coil 3, a relay contact 6 led outwards changes its switching state in accordance with the direction of the excitation current, so that the switching condition is maintained even after the excitation current has been lost.
  • One connection of the relay coil 3 is connected to a connection point 80 between a first transistor 7 and a second transistor 8, the other connection of the relay coil is connected to a connection point 81 between a third transistor 9 and a fourth transistor 10.
  • the output of an amplifier 11 is connected to the base of transistor 10 and to the base of transistor 7 via an inverter N1.
  • the output of another amplifier 12 is at the base of the transistor 8 and via an inverter N2 to the base of transistor 9.
  • the inputs of the amplifiers 11 and 12 are connected to the outputs of AND gates G1, G2.
  • FIG. 2 shows the circuit diagram of the flip-flop 13 in FIG. 1, the one output QF of which is connected to one of the inputs of the AND gate G1 and the inverted output QF of which is connected to one of the inputs of the AND gate G2.
  • the set input S of the flip-flop 13 is connected to a NOR gate G3, which is followed by a delay circuit 82, which consists of a resistor 14, a capacitor 15 and two inverters 16, 17.
  • the reset input R of the flip-flop 13 is connected to a NOR gate G4.
  • the input signals at connections S and R are alternately changed by output bits of an arithmetic unit (not shown) at a high speed of 100 p.s.
  • the NOR gate G4 is followed by a further delay circuit 83 which comprises a resistor 18, a capacitor 19 and two inverters 20, 21.
  • the delay circuits 82, 83 serve to suppress an extremely short interference signal.
  • the output of the inverter 17, that is to say the set output QF of the flip-flop 13, is connected to a further input of the NOR gate G4.
  • the output of the inverter 21, that is to say the reset output QF of the flip-flop 13, which normally supplies the inverted signal with respect to the output QF, is connected to a further input of the NOR gate G3.
  • the NOR gates G3, G4 receive a surge signal from a surge circuit 22, which is initially applied to the input T of this circuit and
  • inverter 23 is inverted by an inverter 23. This signal is shown in Fig. 3 - (1).
  • the output of the inverter 22 is connected to the one input of a NAND element 27 via an inverter 24 and an RC element, which comprises a series resistor 25 and a parallel capacitor 26. Furthermore, the output of the inverter 23 is connected directly to the second input of the NAND gate 27.
  • the output signal of the NAND gate 27 is shown in Fig.3- (3).
  • the output signal of the NOR gate G3 is shown in Fig.3- (4).
  • the output signal of the inverter 17, that is to say at the set output QF of the flip-flop 13, is shown in FIG. 3- (5).
  • the output signal of the NOR gate G4 is shown in Fig.3- (6).
  • the output signal of the inverter 21, that is to say at the reset output QF of the flip-flop 13, is shown in FIG. 3- (7).
  • the described circuit of the flip-flop 13 leads to the fact that the set output QF and the reset output QF have the same logic level only during the times T 1 and T 2 shown in FIG. 3, as a result of which the first and the second input signal be distinguished from interference signals.
  • the circuit according to FIG. 1 contains four pulse shapers 28 to 31, of which the pulse shapers 29 to 31 are constructed in the same way in accordance with the circuit diagram shown in FIG.
  • a pulse shaper comprises resistors 32 to 36, integration capacitors 37 to 41 and Inverters 42 to 45 and a NAND gate G6, which receives at its one input the output signal of the circuit parts comprising the integration capacitors 40, 41.
  • Inverters 42 to 45 supply the signals shown in FIGS. 5- (2) to 5- (5) when a signal according to FIG. 5- (1) is applied.
  • the signal shown in Fig. 5- (6) then results at the output of the NAND gate G6.
  • 1 further comprises a timer 49 consisting of four flip-flops 50 to 53 connected in series with clock inputs T, and a multivibrator 54, which first supplies the flip-flop 50 with a periodic signal according to the diagram in FIGS. 7- (1) as long as the reset output Q4 of the flip-flop 53 of the last stage is high.
  • 7- (2) to 7- (5) show the course of the respective output signals at the outputs Q1 to Q4 of the flip-flops 50 to 52.
  • a monostable signal according to the diagram in Fig. 8- (1) is present.
  • This signal first passes through a level trigger Schmittrigger 58 to prevent malfunctions during the rise and fall times, as well as by low-level interference signals.
  • the signal then passes through pulse shaper 28.
  • Fig. 9- (1) shows the input signal of the pulse shaper 28.
  • Fig. 9- (2) shows the output signal of the pulse shaper 28.
  • Fig. 9- (3) shows the output signal of a NOR gate G7, which is part of a double function lock 59 .
  • a NAND gate G8 connected downstream of the NOR gate G7 supplies a signal according to FIG. Fig. 9- (3) inverted signal to the clock input T of the fliflop 13, so that the set output QF of the fliflop 13 according to Fig. 9- (4) becomes high and the reset output QF becomes low according to Fig. 9- (5).
  • a NAND gate G10 the inputs of which are connected to the set output QF and the reset output QF of the flip-flop 13, supplies the signal illustrated in FIG. 9- (6) at its output.
  • the output of the NAND gate G10 is only low during the time during which both outputs QF and QF are high and thereby resets the flip-flops 50 to 53 of the timer 49.
  • the NAND gate G10 thereby prevents the AND condition for the AND gates G1 and G2 from being met.
  • the reset output Q4 of the flip-flop 53 becomes high as a result of the reset signal coming from the NAND gate G10 and thereby activates the timer 49.
  • the output signals Q3 and Q4 of the flip-flops 52, 53 are shown in FIGS. 9- (7) and 9- ( 8).
  • the double function lock 59 contains a further NOR gate G9, the inputs of which are connected to the reset outputs Q3 and Q4 of the flip-flops 52, 53 of the clock generator 59.
  • the output signal of this NOR gate G9 is shown in Fig. 9- (9).
  • T4 determined by the timer 49
  • the output Q4 of the flip-flop 53 is also connected in parallel to one input of each of the AND gates G1 and G2. After the time interval T3 has elapsed, the output signal of the AND gate Gl switches the transistors 7 and 10 through the amplifier 11, so that a current flows through the excitation winding 3 of the relay in the direction of arrow 4.
  • the diagram in Fig. 8- (2) shows the corresponding output signal of the AND gate Eq.
  • the time interval is the time that is required for switching the excitation winding or relay coil 3 of the bistable relay 2 and which was assumed to be 100 ms here.
  • the time interval T3 supplied by the timer 49 is selected to be somewhat longer than the time required for switching the relay contact 6 of the bistable relay 2.
  • the current surge signal shown in the diagram in FIGS. 10- (1) which is fed to the input terminal P2, reaches the double-function lock 59 via a Schmit trigger 60 and the pulse shaper 29 and leads to the ones in FIGS. 10- (2 ⁇ and Fig. 10- (3) output signals of the AND gates G1, G2, therefore the relay contact 6 changes its position each time the impulse signal is applied.
  • the flip-flop 13 When a set signal shown in Fig. 11- (1) is applied to the input terminal P3, the flip-flop 13 is set via a smith trigger 61, the pulse shaper 30 and an OR gate G14.
  • the AND gate G1 therefore provides the signal shown in FIG. 11- (2) each time the set signal is applied, while the output of the AND gate G2 remains low, as shown in FIG. 11- (3).
  • FIG. 13 shows a circuit 69 with a bistable relay 68 with two excitation windings.
  • This circuit 69 can take the place of the circuit 1 in FIG. 1.
  • the bistable relay 68 changes the switching position of an output relay contact 71 when an excitation current flows through an excitation winding 70 and then holds the contact in this position.
  • the relay contact 71 changes its position again and remains in this new position.
  • Excitation windings 70, 72 are in series with transistors 73, 74, the bases of which are connected to amplifiers 11 and 12, respectively.
  • the circuit 69 can be used in the context of the invention in the same way as the circuit 1.
  • the signals of the connection points 75, 76 of the excitation windings 70, 72 with the transistors 73, 74 can be detected and thus allow an indirect control of whether the bistable relay 68 works.
  • the stabilized voltage Vcc of a constant voltage source is connected to the series circuit comprising a resistor 84 and a capacitor 85, the common connection point of which is connected to one input of an AND gate Gll and to its other input via an inverter N3 , the inverter being designed as a level discriminator.
  • the capacitor 85 charges.
  • the AND gate G11 outputs a high-level signal, by means of which the flip-flops 50 to 53 of the timer 49 are reset.
  • the discriminator level of the inverter N3 is chosen to be higher than the lowest voltage, so that the other reproduced components of the circuit are fed by the constant voltage source and work properly.
  • the output signal of the inverter N3 is fed to the first input of 2 AND gates G12 and G13.
  • the constant voltage source also feeds a resistor 86, which is in series with a switch 87.
  • the connection point of the resistor 86 to the switch 87 is connected to the second input of the AND gate G13 and via an inverter N4 to the second input of the AND gate G12, whose output signal sets the flip-flop 13 via the OR gate G14, while the Output signal of the AND gate G13 resets the flip-flop 13 via the OR gate G15.
  • the AND gate G13 delivers a high-level output signal as long as the voltage across the capacitor 85 is below the discriminator level of the inverter N3. This output signal of the AND gate G13 resets the flip-flop 13. If the stabilized supply voltage is applied or a brief electrical interruption disappears while switch 87 is closed, AND gate G12 provides a high level output signal as long as the voltage across capacitor 85 is below the discriminator level of inverter N3. The flip-flop 13 is set by this output signal of the AND gate G12. If the voltage across the capacitor 85 is higher than the discriminator level, the outputs of the AND gates Gll, G12 and G13 low, so that the circuit operates in accordance with the signals present at the input connections P1 to P4, as previously described.
  • a contact of the bistable relay 2 can be used for the switch 87, which contact is closed when the relay winding 3 has current flowing through it in the direction of the arrow 4 and is open when, conversely, the excitation current flows in the direction of the arrow 5.
  • the relay contact 6 of the bistable relay 2 is always returned to the reset position from the position before the supply voltage was applied or when a brief electrical interruption occurred, even after the supply voltage was switched on or the short-term electrical interruption disappeared. In this way, automatic setting and resetting is achieved, so that a bistable relay, which is connected, for example, to 8 bits of an arithmetic unit, is not set to a position that deviates from the specified program.

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  • Relay Circuits (AREA)
EP81108279A 1980-10-13 1981-10-13 Circuit d'attaque pour un relais bistable Expired EP0050301B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81108279T ATE8944T1 (de) 1980-10-13 1981-10-13 Treiberschaltung fuer ein bistabiles relais.

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP14353680A JPS5767246A (en) 1980-10-13 1980-10-13 Latching relay driving circuit
JP143536/80 1980-10-13
JP143537/80 1980-10-13
JP14353780A JPS5767247A (en) 1980-10-13 1980-10-13 Latching relay driving circuit
JP83229/81 1981-05-31
JP8322981A JPS57199134A (en) 1981-05-31 1981-05-31 Latching relay drive circuit

Publications (2)

Publication Number Publication Date
EP0050301A1 true EP0050301A1 (fr) 1982-04-28
EP0050301B1 EP0050301B1 (fr) 1984-08-08

Family

ID=27304161

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81108279A Expired EP0050301B1 (fr) 1980-10-13 1981-10-13 Circuit d'attaque pour un relais bistable

Country Status (4)

Country Link
US (1) US4433357A (fr)
EP (1) EP0050301B1 (fr)
CA (1) CA1169953A (fr)
DE (1) DE3165425D1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2510809A1 (fr) * 1981-07-31 1983-02-04 Diehl Gmbh & Co Montage de commande electronique destine a produire un comportement monostable dans un relais bistable
FR2536904A1 (fr) * 1982-11-29 1984-06-01 Merlin Gerin Circuit electronique de commande d'un appareillage a fonctionnement multiple equipe d'un mecanisme a electro-aimant
EP0103040B1 (fr) 1982-09-14 1986-01-15 BROWN, BOVERI & CIE Aktiengesellschaft Interrupteur à télécommande avec un circuit électronique de réception et de contrôle
FR2579821A1 (fr) * 1985-03-26 1986-10-03 Merlin Gerin Appareil de coupure multipolaire a telecommande
FR2583192A1 (fr) * 1985-06-11 1986-12-12 Hager Electro Perfectionnement aux appareils de telecommande electriques
EP0362085A1 (fr) * 1988-09-30 1990-04-04 Merlin Gerin Appareil de coupure de courant à télécommande
WO1994017544A1 (fr) * 1993-01-22 1994-08-04 Honeywell Inc. Circuit de commande a relais a impulsions
EP0614206A1 (fr) * 1993-03-05 1994-09-07 Molex Incorporated Retour de l'état d'un relais

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154614A (ja) * 1983-02-23 1984-09-03 Hitachi Ltd 電流駆動回路
FR2564232B1 (fr) * 1984-05-09 1986-10-17 Option Circuit de commande d'un solenoide bistable
US4804864A (en) * 1987-03-09 1989-02-14 Rockwell International Corporation Multiphase CMOS toggle flip-flop
IT1215501B (it) * 1987-05-18 1990-02-14 Sgs Microelettronica Spa Circuito a ponte a transistori moscon ricircolo veloce di corrente abassa diddipazione.
US6392864B1 (en) 1999-09-10 2002-05-21 Alliedsignal Truck Brake Systems Co. Electrical driver circuit for direct acting cantilever solenoid valve
WO2001035432A1 (fr) * 1999-11-11 2001-05-17 Raytheon Company Systeme de commutation redondant insensible aux defaillances pour dispositif critique
US20080055024A1 (en) * 2006-08-31 2008-03-06 Motorola, Inc. System and method for protection of unplanned state changes of a magnetic latching relay
CN111624901B (zh) * 2019-02-28 2024-03-01 施耐德电器工业公司 控制方法、控制装置
CN111352374B (zh) * 2020-03-26 2021-11-16 青岛中加特电气股份有限公司 一种闭锁查询设备及其使用方法
CN113300701B (zh) * 2021-06-21 2024-05-28 深圳市誉娇诚科技有限公司 一种可防止高压继电器误动作的硬件防抖自锁电路

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US3931550A (en) * 1974-11-25 1976-01-06 The United States Of America As Represented By The Secretary Of The Navy Electronic latching relay control
DE2624913B1 (de) * 1976-06-03 1977-10-13 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung bistabiler relais
DE2747607A1 (de) * 1977-10-24 1979-04-26 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung eines bistabilen relais
DE2907673A1 (de) * 1977-10-24 1980-01-03 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung eines bistabilen relais

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CH575187A5 (fr) * 1974-02-14 1976-04-30 Sulzer Ag
US4012673A (en) * 1975-09-15 1977-03-15 Richdel, Inc. Timing valve control system
IT1110628B (it) * 1979-01-30 1985-12-23 Sp El Srl Circuito per la protezione automatica dei transistori di potenza particolarmente per convertitori a commutazione o simili

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931550A (en) * 1974-11-25 1976-01-06 The United States Of America As Represented By The Secretary Of The Navy Electronic latching relay control
DE2624913B1 (de) * 1976-06-03 1977-10-13 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung bistabiler relais
DE2747607A1 (de) * 1977-10-24 1979-04-26 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung eines bistabilen relais
DE2907673A1 (de) * 1977-10-24 1980-01-03 Sds Elektro Gmbh Schaltungsanordnung zur ansteuerung eines bistabilen relais

Non-Patent Citations (3)

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Title
ELECTRONIC DESIGN, Band 25, Nr. 22, 25. Oktober 1977, P. BACHMANN "Solid-State-Relay applications require more than just basic relays to be widely useful. Amplifier, pulse and timing circuits can broaden SSR use" Seiten 68 bis 73 *
PATENTS ABSTRACTS OF JAPAN, Band 3, Nr. 135, 10 November 1979, Seite 48, (E150); & JP-A-54 112 158 (SANYO ELECTRIC CO) (01-09-1979) *
PATENTS ABSTRACTS OF JAPAN, Band 4, Nr. 133, 18 September 1980, Seite 131, (E26); & JP-A-55 087 405 (NIPPON CARBURETER) (02-07-1980) *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2510809A1 (fr) * 1981-07-31 1983-02-04 Diehl Gmbh & Co Montage de commande electronique destine a produire un comportement monostable dans un relais bistable
EP0103040B1 (fr) 1982-09-14 1986-01-15 BROWN, BOVERI & CIE Aktiengesellschaft Interrupteur à télécommande avec un circuit électronique de réception et de contrôle
FR2536904A1 (fr) * 1982-11-29 1984-06-01 Merlin Gerin Circuit electronique de commande d'un appareillage a fonctionnement multiple equipe d'un mecanisme a electro-aimant
EP0112740A1 (fr) * 1982-11-29 1984-07-04 Merlin Gerin Circuit électronique de commande d'un appareillage à fonctionnement multiple équipé d'un mécanisme à électro-aimant
US4578734A (en) * 1982-11-29 1986-03-25 Merlin Gerin Electronic circuit controlling a multiple operation apparatus fitted with an electromagnetic mechanism
EP0199612A1 (fr) * 1985-03-26 1986-10-29 Merlin Gerin Appareil de coupure multipolaire à télécommande
FR2579821A1 (fr) * 1985-03-26 1986-10-03 Merlin Gerin Appareil de coupure multipolaire a telecommande
FR2583192A1 (fr) * 1985-06-11 1986-12-12 Hager Electro Perfectionnement aux appareils de telecommande electriques
EP0212993A1 (fr) * 1985-06-11 1987-03-04 Hager Electro S.A. Perfectionnement aux appareils de télécommande électriques
EP0362085A1 (fr) * 1988-09-30 1990-04-04 Merlin Gerin Appareil de coupure de courant à télécommande
FR2637414A1 (fr) * 1988-09-30 1990-04-06 Merlin Gerin Appareil de coupure de courant a telecommande
WO1994017544A1 (fr) * 1993-01-22 1994-08-04 Honeywell Inc. Circuit de commande a relais a impulsions
EP0614206A1 (fr) * 1993-03-05 1994-09-07 Molex Incorporated Retour de l'état d'un relais

Also Published As

Publication number Publication date
EP0050301B1 (fr) 1984-08-08
DE3165425D1 (en) 1984-09-13
US4433357A (en) 1984-02-21
CA1169953A (fr) 1984-06-26

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