EP0000480B1 - Method of passivating semiconductor elements by applying a silicon layer - Google Patents
Method of passivating semiconductor elements by applying a silicon layer Download PDFInfo
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- EP0000480B1 EP0000480B1 EP78100268A EP78100268A EP0000480B1 EP 0000480 B1 EP0000480 B1 EP 0000480B1 EP 78100268 A EP78100268 A EP 78100268A EP 78100268 A EP78100268 A EP 78100268A EP 0000480 B1 EP0000480 B1 EP 0000480B1
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- silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/958—Passivation layer
Definitions
- a major problem with semiconductor components is keeping the current-voltage characteristics stable.
- rectifiers and transistors these are, in particular, the characteristic curves in the reverse direction, while in the case of thyristors attention should be paid to the stability of the characteristic curves in the reverse direction and in the tilt direction.
- DE-B-1 185 896 describes a passivation method in which silicon is vapor-deposited on the surface of a semiconductor element in a high vacuum.
- the evaporation can be carried out at comparatively lower temperatures than in the thermal decomposition of a silicon compound. This enables passivation of components that have already been contacted and assembled.
- the invention accordingly relates to a method for passivating semiconductor components, in which a silicon layer is evaporated onto the surface of the semiconductor elements in a high vacuum.
- the invention is therefore based on the object of developing this passivation method in such a way that low reverse currents can be achieved.
- the invention is characterized in that the vapor-deposited silicon layer is annealed at such a temperature between the room temperature and the crystallization temperature of the vapor-deposited silicon that a desired reduction in the blocking currents is achieved.
- the semiconductor element of a thyristor is shown in section. It has four zones, of which the cathode-side emitter zone is designated 1, the cathode-side base zone 2, the inner base zone 3 and the anode-side emitter zone 4. There are pn junctions 5, 6, 7 between the zones mentioned.
- the semiconductor element consists of silicon and the zones mentioned are doped in a conventional manner depending on the intended use of the semiconductor component.
- a protective layer 8 made of silicon is vapor-deposited onto the edge of the semiconductor element, at least at the points at which the pn junctions come to the surface, which can be, for example, 0.1 ⁇ m or thicker, for example 1 ⁇ m.
- the areas of the semiconductor element that are not to be vaporized are covered before the vapor deposition.
- a further protective layer 9 can be applied to the evaporated silicon layer 8, which can consist, for example, of normal rubber or another protective lacquer.
- the evaporated silicon layer 8 can contain dopants such as boron or phosphorus to adjust the specific resistance. A content of the mentioned dopants is increased by evaporating one or more of these substances with the silicon.
- the layer 8 can also contain one or more metals such as aluminum for setting the specific resistance. The metals can also be built into the silicon by vapor deposition. The potential relationships at the edge of the semiconductor element can be adjusted by changing the specific resistance of layer 8.
- the layer 8 may be, for example doped with phosphorus and have a resistivity of 10 ohm cm a.
- the silicon layer 8 was in a vacuum evaporation system at a pressure of about 6.5. 10- 4 Pa (5. 10-6 Torr) by vapor deposition.
- a silicon block can be used as the silicon source.
- the silicon can be evaporated using an electron beam. With an acceleration voltage of 8 kV and a current of around 0.5 A, a vapor deposition rate of 0.25 ⁇ m / min was achieved. It can also be increased, for example, to 0.5 .mu.m / min and above by increasing the energy of the electron beam.
- the silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It it is also possible to evaporate the silicon by radiant heat.
- the layer 8 can also consist of several successively vapor-deposited layers, each with different properties. A change in the specific resistance via the thickness and an influence on the potential relationships on the edge surface of the semiconductor element are thus obtained.
- the evaporated silicon layer is annealed.
- the annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon.
- the crystallization temperature of the silicon is between 427-627 ° C (700 and 900 ° K).
- the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization.
- the reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing.
- FIG. 2 shows that the blocking current Isp for a certain type of semiconductor without the annealing at 2.
- Evaporation of the silicon itself can be carried out at room temperature.
- the temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.
- FIG. 3 in which the shape of the space charge zone is shown when the pn junction 7 is stressed in the reverse direction.
- the boundaries 11, 12 of the space charge zone 10 run parallel to the pn junctions, for example. If there is a blocking load for a long time, the space charge zone widens in that the boundary 12 of the space charge zone 10 at the edge of the semiconductor element shifts in the direction of the pn junction 6. At the same time, the boundary 11 of the space charge zone 10 moves away from the pn junction 7, but only to a much weaker extent, since the zone 4 is more heavily doped than the zone 3.
- the expansion of the space charge zone is shown in dashed lines in the figure.
- the reverse current increases until the so-called punch-through effect occurs at the edge when the pn junction 6 is reached, where the pn junction 7 loses its blocking ability.
- the widening also takes place at the pn junction 6 when the semiconductor element is loaded with a voltage in the reverse direction, that is to say the tilting direction.
- the space charge zone 10 no longer widens at the edge. This can be determined, for example, using the known photoelectric method for examining the space charge zones at the edge of a semiconductor element. This means that the reverse currents do not increase, in other words that the characteristic curves remain stable in the reverse direction.
- the invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the area in which the pn junctions appear on the surface of the half-meter element.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Ein wesentliches Problem bei Halbleiterbauelementen besteht darin, die Strom-Spannungskennlinien stabil zu halten. Bei Gleichrichtern und Transistoren sind dies insbesondere die Kennlinien in Sperrichtung, während bei Thyristoren das Augenmerk auf die Stabilität der Kennlinien in Sperrichtung und in Kipprichtung zu lenken ist.A major problem with semiconductor components is keeping the current-voltage characteristics stable. In the case of rectifiers and transistors, these are, in particular, the characteristic curves in the reverse direction, while in the case of thyristors attention should be paid to the stability of the characteristic curves in the reverse direction and in the tilt direction.
Es sind bereits Verfahren beschrieben worden, durch die ein Halbleiterelement mittels einer thermisch aufwachsenden Siliciumschicht passiviert wird (vergleiche NL-A-7613893, DE-A-26 18 733, FR-A-2 290040). Die dort beschriebenen Passivierungsverfahren benutzen die bekannte thermische Zersetzung einer gasförmigen Siliciumverbindung, um polykristallines Silicium auf der Oberfläche des Halbleiterelements abzuscheiden. Diese Verfahren erfordern daher Temperaturen zwischen 600 und 700°C, was eine Anwendung bei bereits kontaktierten und eventuell verlöteten Bauelementen unmöglich macht. Das Silicium muß außerdem an denjenigen Stellen, an denen es nicht benötigt wird, weggeätzt werden. Weiter kann dieses Verfahren zu einer starken Herabsetzung der Trägerlebensdauer im Volumen und an der Oberfläche führen.Methods have already been described by which a semiconductor element is passivated by means of a thermally growing silicon layer (compare NL-A-7613893, DE-A-26 18 733, FR-A-2 290040). The passivation processes described there use the known thermal decomposition of a gaseous silicon compound in order to deposit polycrystalline silicon on the surface of the semiconductor element. These processes therefore require temperatures between 600 and 700 ° C, which makes application with components that have already been contacted and possibly soldered impossible. The silicon must also be etched away where it is not needed. Furthermore, this method can lead to a sharp reduction in the carrier life in volume and on the surface.
In der DE-B-1 185 896 ist ein Passivierungsverfahren beschrieben worden, bei dem Silicium im Hockvakuum auf die Oberfläche eines Halbleiterelements aufgedampft wird. Das Aufdampfen kann bei vergleichsweise niedrigeren Temperaturen als bei der thermischen Zersetzung einer Siliciumverbindung durchgeführt werden. Damit ist eine Passivierung von bereits kontaktierten und montierten Bauelementen möglich.DE-B-1 185 896 describes a passivation method in which silicon is vapor-deposited on the surface of a semiconductor element in a high vacuum. The evaporation can be carried out at comparatively lower temperatures than in the thermal decomposition of a silicon compound. This enables passivation of components that have already been contacted and assembled.
Die Erfindung bezieht sich demnach auf ein Verfahren zum Passivieren von Halbleiterbauelementen, bei dem auf die Oberfläche der Halbleiterelemente im Hochvakuum eine Siliciumschicht aufgedampft wird.The invention accordingly relates to a method for passivating semiconductor components, in which a silicon layer is evaporated onto the surface of the semiconductor elements in a high vacuum.
Bei der Kennlinienmessung solcher Art passivierter Halbleiterbauelemente wurde herausgefunden, daß die Kennlinien zwar stabil sind, daß die Sperrströme jedoch viel zu hoch liegen.When measuring the characteristics of such a type of passivated semiconductor device, it was found that the characteristics are stable, but that the reverse currents are much too high.
Der Erfindung liegt daher die Aufgabe zugrunde, dieses Passivierungsverfahren so weiterzubilden, daß niedrige Sperrströme erzielt werden können.The invention is therefore based on the object of developing this passivation method in such a way that low reverse currents can be achieved.
Die Erfindung ist dadurch gekennzeichnet, daß die aufgedampfte Siliciumschicht bei einer derartigen zwischen der Raumtemperatur und der Kristallisationtemperatur des aufgedampften Siliciums liegenden Temperatur getempert wird, daß eine gewünschte Absenkung der Sperrströme erreicht wird.The invention is characterized in that the vapor-deposited silicon layer is annealed at such a temperature between the room temperature and the crystallization temperature of the vapor-deposited silicon that a desired reduction in the blocking currents is achieved.
Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Developments of the invention are the subject of the dependent claims.
Die Erfindung wird an Hand eines Ausführungsbeispiels in Verbindung mit den Fig. 1 und 3 und an Hand eines Diagramms (Fig. 2) näher erläutert:The invention is explained in more detail using an exemplary embodiment in conjunction with FIGS. 1 and 3 and using a diagram (FIG. 2):
In Fig. 1 ist das Halbleiterelement eines Thyristors im Schnitt dargestellt. Es hat vier Zonen, von denen die kathodenseitige Emitterzone mit 1, die kathodenseitige Basiszone mit 2, die innere Basiszone mit 3 und die anodenseitige Emitterzone mit 4 bezeichnet ist. Zwischen den genannten Zonen liegen pn-Übergänge 5, 6, 7. Das Halbleiterelement besteht aus Silicium und die genannten Zonen sind in üblicher Weise je nach Verwendungszweck des Halbleiterbauelements dotiert.In Fig. 1, the semiconductor element of a thyristor is shown in section. It has four zones, of which the cathode-side emitter zone is designated 1, the cathode-
Auf den Rand des Halbleiterelements wird wenigstens and den Stellen, an denen die pn-Übergänge an die Oberfläche treten, eine Schutzschicht 8 aus Silicium aufgedampft, die beispielsweise 0.1 ,um oder auch dicker sein kann, beispielsweise 1 ,um. Die nicht zu bedampfenden Flächen des Halbleiterelements werden vor dem Bedampfen abgedeckt. Zur Erhöhung der dielektrischen Überschlagsfestigkeit und zur Verbesserung des mechanischen Schutzes kann auf die aufgedampfte Siliciumschicht 8 eine weitere Schutzschicht 9 aufgebracht werden, die beispielsweise aus normalem Kautschuk oder einem anderen Schutzlack bestehen kann.A
Die aufgedampfte Siliciumschicht 8 kann zur Einstellung des spezifischen Widerstands Dotierstoffe wie zum Beispiel Bor oder Phosphor enthalten. Einen Gehalt an den genannten Dotierstoffen erhölt man dadurch, daß mit dem Silicium einer oder mehrere dieser Stoffe verdampft werden. Die Schicht 8 kann zur Einstellung des spezifischen Widerstands auch ein oder mehrere Metalle wie zum Beispiel Aluminium enthalten. Die Metalle können ebenfalls durch Aufdampfen mit dem Silicium in dieses eingebaut werden. Mit Änderung des spezifischen Widerstands der Schicht 8 lassen sich die Potentialverhältnisse am Rand des Halbleiterelements einstellen. So kann die Schicht 8 beispielsweise mit Phosphor dotiert sein und einen spezifischen Widerstand von 10a Ohm cm haben.The evaporated
Die Siliciumschicht 8 wurde in einer Vakuum-Bedampfungsanlage bei einem Druck von c.a. 6,5 . 10-4 Pa (5 . 10-6 Torr) aufgedampft. Als Siliciumquelle kann beispielsweise ein Siliciumblock verwendet werden. Das Silicium kann mittels eines Elektronenstrahls verdampft werden. Mit einer Beschleunigungsspannung von 8 kV und einem Strom von rund 0,5 A wurde eine Aufdampfrate von 0,25 ,um/min erzielt. Sie läßt sich durch Erhöhung der Energie des Elektronenstrahls auch beispielsweise auf 0,5 ,um/min und darüber steigern.The
Das Silicium kann auch durch einen lonenstrahl, durch direkten Stromdurchfluß oder durch induktive Erhitzung verdampft werden. Es ist auch möglich, das Silicium durch Strahlungswärme zu verdampfen.The silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It it is also possible to evaporate the silicon by radiant heat.
Die Schicht 8 kann auch aus mehreren nacheinander aufgedampften Schichten mit jeweils verschiedenen Eigenschaften bestehen. Damit erhält man eine Änderung des spezifischen Widerstands über die Dicke und eine Beeinflussung der Potentialverhältnisse an der Randfläche des Halbleiterelements.The
Anschließend an das Bedampfen des Halbleiterelements wird die aufgedampfte Siliciumschicht getempert. Das Tempern findet bei einer Temperatur zwischen Zimmertemperatur und der Kristallisationstemperatur des Siliciums statt. Die Kristallisationstemperatur des Siliciums liegt nach Literaturangaben zwischen 427-627°C (700 und 900°K). Bei bereits kontaktierten Halbleiterelementen wird das Tempern bei einer Temperatur vorgenommen, die unterhalb der Schmelztemperatur des zum Kontaktieren verwendeten Materials, zum Beispiel Weichlot, oder einer anderen Metallisierung liegt. Durch das Tempern lassen sich der Sperrstrom in Sperrichtung und der Sperrstrom in Kipprichtung des Halbleiterelements drastisch absenken. In Fig. 2 ist dargestellt, daß der Sperrstrom Isp bei einem bestimmten Halbleitertyp ohne das Tempern bei 2 . 103 nA lag. Nach einer Temperzeit von drei Stunden bei 280°C lag der Sperrstrom für drei Meßexemplare zwischen 3 und 5 . 101 nA. Nach 23 und 41 Stunden Temperzeit bei 280°C wurden weitere Absenkungen der Sperrströme beobachtet.Subsequent to the vapor deposition of the semiconductor element, the evaporated silicon layer is annealed. The annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon. According to the literature, the crystallization temperature of the silicon is between 427-627 ° C (700 and 900 ° K). In the case of semiconductor elements which have already been contacted, the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization. The reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing. FIG. 2 shows that the blocking current Isp for a certain type of semiconductor without the annealing at 2. 10 3 nA was. After an annealing time of three hours at 280 ° C, the blocking current for three test samples was between 3 and 5. 10 1 nA. After 23 and 41 hours of tempering at 280 ° C, further reductions in the blocking currents were observed.
Das Aufdampfen des Siliciums selbst kann bei Zimmertemperatur durchgeführt werden. Die Temperatur der anschließenden Wärmebehandlung kann dann so gewählt werden, daß die gewünschte Absenkung der Sperrströme erreicht wird, ohne daß zum Beispiel bereits kontaktierte Bauelemente in Mitleidenschaft gezogen werden. Damit ist es möglich, bereits aufgelötete und kontaktierte Chips zu passivieren, so daß keine Maskierung oder kein selektives Ätzen der Chips erforderlich ist.Evaporation of the silicon itself can be carried out at room temperature. The temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.
Halbleiterelemente, die durch Aufdampfen einer Siliciumschicht und nachfolgendes Tempern passiviert wurden, wiesen eine überraschend gute Stabilität der Kennlinien bei niedrigem Stromniveau auf. Dies galt sowohl für die Sperrkennlinien in Rückwärtsrichtung bei Dioden und Transistoren als auch für die Sperrkennlinien in Rückwärtsrichtung und Kipprichtung bei Thyristoren. Bei Thyristoren trat auch der sogenannte Yoshida-Effekt nicht mehr auf, der eine drastische Erhöhung der Sperrströme nach vorhergehender Durchlaßbelastung bewirkt.Semiconductor elements, which were passivated by vapor deposition of a silicon layer and subsequent annealing, showed a surprisingly good stability of the characteristics at a low current level. This was true both for the reverse blocking characteristics for diodes and transistors and for the reverse blocking characteristics for the thyristors. In the case of thyristors, the so-called Yoshida effect no longer occurred, which causes a drastic increase in the reverse currents after the forward load.
Die Stabilität der Kennlinien läßt sich anschaulich an Hand der Fig. 3 erklären, in der die Gestalt der Raumladungszone dargestellt ist, wenn der pn-Übergang 7 in Sperrichtung beansprucht ist. Zu Anfang der Sperrbelastung verlaufen die Grenzen 11, 12 der Raumladungszone 10 zum Beispiel parallel zu den pn-Übergängen. Liegt längere Zeit Sperrbelastung an, so weitet sich die Raumladungszone dadurch auf, daß sich die Grenze 12 der Raumladungszone 10 am Rand des Halbleiterelement in Richtung auf den pn-Übergang 6 verschiebt. Gleichzeitig entfernt sich die Grenze 11 der Raumladungszone 10 vom pn-Übergang 7, jedoch nur in erheblich schwächerem Maße, da die Zone 4 stärker als die Zone 3 dotiert ist. Die Aufweitung der Raumladungszone ist in der Fig. gestrichelt dargestellt. Mit größer werdender Aufweitung der Raumladungszone nimmt der Sperrstrom zu, bis mit Erreichen des pn-Übergangs 6 am Rand der sogenannte Punch-Through-Effekt eintritt, wo der pn-Übergang 7 seine Sperrfähigkeit verliert. Die Aufweitung findet auch am pn-Übergang 6 statt, wenn das Halbleiterelement in der umgekehrten Richtung, das heißt der Kipprichtung, mit einer Spannung belastet wird.The stability of the characteristic curves can be clearly explained with reference to FIG. 3, in which the shape of the space charge zone is shown when the
Mit der Passivierungsschicht gemäß der Erfindung weitet sich die Raumladungszone 10 am Rand nicht mehr auf. Dies läßt sich beispielsweise mit der bekannten lichtelektrischen Methode zur Untersuchung der Raumladungszonen am Rand eines Halbleiterelements feststellen. Dies bedeutet, daß sich die Sperrströme nicht erhöhen, mit anderen Worten, daß die Kennlinien in Sperrichtung stabil bleiben.With the passivation layer according to the invention, the
Die Erfindung wurde in Verbindung mit einem Halbleiterelement für einen Thyristor beschrieben. Sie läßt sich jedoch auch bei Dioden, Transistoren und anderen Halbleiterbauelementen verwenden. Sie ist gleichermaßen für Mesa- oder Planarstrukturen verwendbar. Wesentlich ist, daß auf mindestens denjenigen Bereich, in dem die pn-Übergänge an die Oberfläche des Halbleterelements treten, Silicium aufgedampft wird.The invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the area in which the pn junctions appear on the surface of the half-meter element.
Claims (3)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2730367 | 1977-07-05 | ||
| DE19772730367 DE2730367A1 (en) | 1977-07-05 | 1977-07-05 | PROCESS FOR PASSIVATING SEMICONDUCTOR ELEMENTS |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0000480A1 EP0000480A1 (en) | 1979-02-07 |
| EP0000480B1 true EP0000480B1 (en) | 1981-08-12 |
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ID=6013203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP78100268A Expired EP0000480B1 (en) | 1977-07-05 | 1978-06-28 | Method of passivating semiconductor elements by applying a silicon layer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4322452A (en) |
| EP (1) | EP0000480B1 (en) |
| JP (1) | JPS5417672A (en) |
| CA (1) | CA1111149A (en) |
| DE (1) | DE2730367A1 (en) |
| GB (1) | GB1587030A (en) |
| IT (1) | IT1096857B (en) |
Families Citing this family (13)
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|---|---|---|---|---|
| DE3021175A1 (en) * | 1980-06-04 | 1981-12-10 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PASSIVATING SILICON COMPONENTS |
| AT380974B (en) * | 1982-04-06 | 1986-08-11 | Shell Austria | METHOD FOR SETTING SEMICONDUCTOR COMPONENTS |
| AT384121B (en) * | 1983-03-28 | 1987-10-12 | Shell Austria | Method for gettering of semiconductor components |
| US4860066A (en) * | 1987-01-08 | 1989-08-22 | International Business Machines Corporation | Semiconductor electro-optical conversion |
| EP0381110B1 (en) * | 1989-02-01 | 1994-06-29 | Siemens Aktiengesellschaft | Protection layer for electroactive passivation layers |
| ES2072321T3 (en) * | 1989-02-01 | 1995-07-16 | Siemens Ag | ELECTROACTIVE LIABILITY LAYER. |
| US5213670A (en) * | 1989-06-30 | 1993-05-25 | Siemens Aktiengesellschaft | Method for manufacturing a polycrystalline layer on a substrate |
| JP2501641B2 (en) * | 1989-07-19 | 1996-05-29 | 住友重機械工業株式会社 | Long feeding device for lateral feed |
| US5451550A (en) * | 1991-02-20 | 1995-09-19 | Texas Instruments Incorporated | Method of laser CVD seal a die edge |
| DE4137341C1 (en) * | 1991-11-13 | 1993-04-29 | Siemens Ag, 8000 Muenchen, De | |
| US6885522B1 (en) | 1999-05-28 | 2005-04-26 | Fujitsu Limited | Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation |
| DE10358985B3 (en) | 2003-12-16 | 2005-05-19 | Infineon Technologies Ag | Semiconductor element e.g. power semiconductor switch, with pn-junction and passivation layer at surface of semiconductor body acting as screening layer for edge structure limitation |
| US10581082B2 (en) * | 2016-11-15 | 2020-03-03 | Nanocomp Technologies, Inc. | Systems and methods for making structures defined by CNT pulp networks |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2789258A (en) * | 1955-06-29 | 1957-04-16 | Raytheon Mfg Co | Intrinsic coatings for semiconductor junctions |
| SE300472B (en) * | 1965-03-31 | 1968-04-29 | Asea Ab | |
| DE2018517B2 (en) * | 1970-04-17 | 1973-02-22 | Hitachi, Ltd , Tokio | EXPERIENCE TO MANUFACTURE A SEMICONDUCTOR COMPONENT |
| US3765940A (en) * | 1971-11-08 | 1973-10-16 | Texas Instruments Inc | Vacuum evaporated thin film resistors |
| US3806361A (en) * | 1972-01-24 | 1974-04-23 | Motorola Inc | Method of making electrical contacts for and passivating a semiconductor device |
| JPS532552B2 (en) * | 1974-03-30 | 1978-01-28 | ||
| JPS6022497B2 (en) * | 1974-10-26 | 1985-06-03 | ソニー株式会社 | semiconductor equipment |
| JPS6041458B2 (en) * | 1975-04-21 | 1985-09-17 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JPS51128268A (en) * | 1975-04-30 | 1976-11-09 | Sony Corp | Semiconductor unit |
| FR2335951A1 (en) * | 1975-12-19 | 1977-07-15 | Radiotechnique Compelec | SEMICONDUCTOR DEVICE WITH A PASSIVE SURFACE AND METHOD OF OBTAINING THE PASSIVATION STRUCTURE |
| DE2632647A1 (en) * | 1976-07-20 | 1978-01-26 | Siemens Ag | SEMICONDUCTOR COMPONENT WITH PASSIVATING PROTECTIVE LAYER |
| DE2642413A1 (en) * | 1976-09-21 | 1978-03-23 | Siemens Ag | Silicon passivating layer for thyristor - can be metallised, or deposited by vacuum, electron beam or ion beam and can be electrically, or inductively applied |
| US4179528A (en) * | 1977-05-18 | 1979-12-18 | Eastman Kodak Company | Method of making silicon device with uniformly thick polysilicon |
| US4134125A (en) * | 1977-07-20 | 1979-01-09 | Bell Telephone Laboratories, Incorporated | Passivation of metallized semiconductor substrates |
-
1977
- 1977-07-05 DE DE19772730367 patent/DE2730367A1/en active Granted
-
1978
- 1978-05-25 GB GB22229/78A patent/GB1587030A/en not_active Expired
- 1978-06-28 EP EP78100268A patent/EP0000480B1/en not_active Expired
- 1978-06-30 IT IT25181/78A patent/IT1096857B/en active
- 1978-07-04 CA CA306,759A patent/CA1111149A/en not_active Expired
- 1978-07-05 JP JP8187078A patent/JPS5417672A/en active Granted
-
1980
- 1980-08-18 US US06/178,750 patent/US4322452A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| IT1096857B (en) | 1985-08-26 |
| CA1111149A (en) | 1981-10-20 |
| EP0000480A1 (en) | 1979-02-07 |
| DE2730367A1 (en) | 1979-01-18 |
| JPS6158976B2 (en) | 1986-12-13 |
| US4322452A (en) | 1982-03-30 |
| GB1587030A (en) | 1981-03-25 |
| JPS5417672A (en) | 1979-02-09 |
| IT7825181A0 (en) | 1978-06-30 |
| DE2730367C2 (en) | 1988-01-14 |
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