EP0000169B1 - Semiconductor junction capacitor in integrated method of construction and bootstrap circuit with such a capacitor - Google Patents

Description

The invention relates to a semiconductor junction capacitance in integrated design according to the preamble of claim 1 and their use. in a bootstrap circuit.

When designing digital systems, it is often necessary to use two different integrated circuit technologies, for example bipolar and field effect arrangements, if the specified performance range for the circuit is to be achieved. Bipolar circuits are often used for applications in logic circuits and for clocks, whereas field effect circuits are used for memory applications. Since bipolar circuits generally operate at voltages well below the values required to operate field effect circuits, buffer circuits are required to raise the bipolar signal levels to the level of field effect circuits. Bipolar circuits are usually used to implement this buffer function.

Since field effect circuits tend to generate voltage drops the size of a threshold voltage (typically 0.5 to 1.5 V) per logic stage, it is particularly important that the input signals for field effect circuits be as close as possible to the supply potential of the drain electrode Circles lie (typically 8 to 15 V). Emitter followers are used almost exclusively; To eliminate or reduce the voltage drop base / emitter that inevitably occurs in such circuits, capacitive charge retention or a bootstrap element is used in one form or another. For example, in U.S. Patent 3,656,004, the built-in capacitance between the base and emitter itself is used to provide additional stored charge that allows the output emitter follower to remain conductive for a sufficient period of time after the base driver circuitry has been completed has become non-conductive, so that the output voltage reaches the value of the supply potential. The article "Bipolar Bootstrap Circuit" in IBM Technical Disclosure Bulletin, Feb. 76, pages 2818 to 2819 describes a similar charge storage technique in which the base-collector capacitance of a bipolar transistor is used to add additional current deliver with which the driver circuit is kept in a conductive state after switching its source. In both examples, the amount of charge that can be retained is limited by the large interference capacitances between the circuit elements and the substrate of the integrated circuit, and by the time required for charging the internal capacitances after the output signal has started.

In the article "Clock Drivers for Dynamic MOS-FET Shift Register Matrices" in IBM Technical Disclosure Bulletin, Feb. 1974, pages 2767 to 2768 and in US Pat. No. 4002931, a bootstrap capacity is used which is between the output of the emitter follower and its Entrance lies; this results in a high voltage level with which the output circuit is kept conductive after the input signal for the driver circuit has normally already decayed. Fig. 1 shows a simplified drive circuit of bootstrap type in which _an input signal V is applied to T1, and an inverted output signal Vout appears at the voltage node A. If V is _a high level logic signal, T1 is conducting, and thus T4, which connects node A to ground. When T1 conducts, the base of T2 is near ground potential and T ₂ is off. The voltage drop across R1 allows the feedback capacitor Cfb to charge to approximately VL minus _{Vbe of} the diode D1. When the input signal transitions from its high to low logic level, T1 and T4 are turned off. The base of T2 then rises in potential and thus turns on T2, which also makes T3 conductive and causes the output signal V _{out to} rise. The rate at which the potential in node A increases is determined by the size of the applied capacitive load (which is not shown), the size of Cfb and the size of various parasitic capacities, which are summarized as variable capacitance Cp. The larger Cp, the larger Cfb must be, so that sufficient feedback to node B is available to supply current to the base of T2 and to keep it conductive until node A reaches the supply potential VH of the drain electrode. In many cases, Cfb is too large to accommodate a capacitor of the appropriate capacitance on the same substrate as the rest of the circuit; it is therefore designed as a discrete external component. The above-mentioned US Pat. No. 4,002,931 describes an integrated capacitance with a thin oxide layer, as shown in FIG. 2. The output at node A is conductively connected to an N + -doped semiconductor region, the P + isolation wells in the on a P -Substrate grown type N epitaxial layer are formed. The capacitance Cfb between the contacts A and B is constant, but the capacitance between the contact A and the substrate contains a PN boundary layer biased in the reverse direction. FIG. 3A is a schematic representation of the in FIG. 2 shows the capacitor, FIG. 3B is a representation of the capacitive effects of the capacitor when the potential at node A increases. The characteristics of the reverse polarity diode correspond to a variable capacitor CP, the capacitance of which increases as the potential at node A increases. Since the ratio of Cfb to Cp can be small, the effectiveness of the feedback is reduced. Although other capacitor structures, for example junction capacitance as in US Pat. No. 3,474,309 can be used, they also have large parasitic capacitances which are coupled to the capacitor connections and reduce the effectiveness of this circuit.

As further prior art that is of interest here can be genant: US Patent 3,641,368, in which an NPN transistor is used with short-circuited collector-emitter as the capacitance and the US patent ^g hrift 3,678,348, in a bipolar multi-emitter transistor is shown, in which a plurality of contacts are connected in common to a single emitter electrode and a separate multi-contact base electrode.

From the German published patent application DE-A 17 64 148 a semiconductor junction capacitance in an integrated design is known. knows, in which the first and second boundary layer diodes are arranged, the second diode having the opposite polarity with respect to the other and in which all the diodes are operated in the reverse direction (cf. preamble of claim 1). It is also known from this document that the pn-junction diodes are formed as a structure corresponding to a transistor on a single semiconductor chip, the first pn-junction diode comprising an area corresponding to the emitter together with an area corresponding to the base and the second pn -Border-. Layer diode the area corresponding to the base together with an area corresponding to the collector, wherein a plurality of areas corresponding to the emitter are further arranged in a area corresponding to the base and connected to a common output terminal. However, such a construction of a semiconductor junction capacitance does not allow parasitic capacitances, e.g. in bootstrap circuits.

Accordingly, the object of the present invention is to provide an improved integrated bipolar semiconductor junction capacitance, with which in particular the disturbing effects of parasitic capacitances in bootstrap circuits are reduced.

This object is achieved by the invention characterized in claims 1 and 5; Particular embodiments of the invention are characterized in the subclaims.

The invention uses a semiconductor junction capacitance with a plurality of semiconductor boundary layers, in which three pn boundary layers connected in series are arranged between a reference potential and an output terminal, and in which the middle pn boundary layer is reversely polarized with respect to the other two boundary layers. By keeping all of these boundary layers polarized in the reverse direction, an input signal that is fed between the two boundary layers closest to the output terminal creates a voltage-dependent capacitance between the input signal and the output terminal, while the middle PN boundary layer provides a capacitive separation between the input signal and the reference potential . The use of the voltage-dependent capacitance as Bootstrap _- capacity in a bipolar driver circuit provides a circuit which has a wide working range, mainly due to the built-in load capacitance, which is provided for the input signal by the capacity of the central pn junction.

One way of carrying out the invention will now be explained in more detail with reference to drawings.

• Fig. 1 einen schematischen Schaltkreis einer bipolaren Bootstrap-Treiberschaltung nach dem Stand der Technik,
• Fig. 2 einen schematischen Querschnitt einer Kondensatorstruktur (Kapazität) nach dem Stand der Technik,
• Fign. 3A und 3B schematische Schaltkreise mit zwei verschiedenen elektrischen Darstellungen der in Fig. 2 dargestellten Kapazität,
• Fig. 4 einen schematischen Schaltkreis einer bipolaren Bootstrap-Treiberschaltung in der die erfindungsgemäße Halbleitersperrschicht-kapazitat als bipolarer Transistor dargestellt ist,
• Fign. 5A und 5B schematische Schaltbilder alternativer elektrischer Schaltkreise Halbleitersperrschichtkapazität von Fig. 4,
• Fig. 6 ein schematisches Schaltbild einer anderen Ausführung des bipolaren Bootstrap-Treiberschaltkreises,
• Fig. 7A eine Aufsicht auf eine Ausführungsform der Halbleitersperrschichtkapazitat mit mehrfachen emitterähnlichen und basis- ähnlichen Kontaktbereichen des in Fig. 6 dargestellten kapazitiven Elements T5,
• Fig. 7B einen Querschnitt der Halbleitersperrschichtkapazität von Fig. 7A links der Linie B-B mit dem vertikalen Profil der Struktur.

Show it:

• 1 shows a schematic circuit of a bipolar bootstrap driver circuit according to the prior art,
• 2 shows a schematic cross section of a capacitor structure (capacitance) according to the prior art,
• Fig. 3A and 3B are schematic circuits with two different electrical representations of the capacitance shown in FIG. 2,
• 4 shows a schematic circuit of a bipolar bootstrap driver circuit in which the semiconductor junction capacitance according to the invention is shown as a bipolar transistor,
• Fig. 5A and 5B are schematic circuit diagrams of alternative electrical circuits semiconductor junction capacitance of FIG. 4,
• 6 is a schematic diagram of another embodiment of the bipolar bootstrap driver circuit;
• 7A is a plan view of an embodiment of the semiconductor junction capacitance with multiple emitter-like and base-like contact areas of the capacitive element T5 shown in FIG. 6.
• 7B is a cross section of the semiconductor junction capacitance of FIG. 7A to the left of line BB with the vertical profile of the structure.

Fig. 4 shows an embodiment of the invention in the form of a bipolar bootstrap driver circuit with an emitter follower of the Darlington type. When an input signal V _{e; "} , which is supplied by a bipolar logic circuit, is applied, the circuit is intended to deliver an output signal V _out , the voltage of which Level between the ground potential and the supply voltage V _µ for the drain electrodes of a driven field effect transistor (FET) circuit. The circuit comprises an input transistor T ₁ , the base of which is coupled to V _a and the collector of which is connected to the input of a Darlington amplifier pair T2 and T3. The emitter of T1 is grounded through resistor R2 and is connected directly to the base of transistor T4, which is used to quickly step down the output signal. The collector of T1 is also connected via a transistor connected as a diode, resistor R1 is further connected to a low-level voltage VL. The amplifier or driver part of the circuit contains transistors T2 and T3, the collectors of which are connected to the supply potential VH of the PET drain electrodes. The output of the amplifier is connected to the collector of transistor T4 at voltage node A. Between the node A and the output terminal V _{out there} is an element T5 which is similar to a bipolar transistor and whose base is connected to both the node A and to V _out . The collector of T5 is connected to VH, the emitter to voltage node B between R1 and D1. The bias of T5 is such that no transistor effect occurs and the element acts only as a pair of boundary layer capacitances which give the output signal V _out via the feedback capacitance Cfb to node B and couple the output signal V _out to VH via the internal load capacitance CLi.

In operation, the circuit works according to Figure 4 is as follows:. If V assumes _a high level, T1 is conductive and a current flows from VL through D1, R1, T1 and R2 to ground. Current through R2 causes the base of T4 to rise above the value Vbe and thus turns on the transistor T4, which then sets the nodes A and Vout to ground potential. The voltage division by D1, R1 and R2 keeps the base potential of T2 so low that T2 and T3 remain non-conductive. However, node B maintains a voltage that is approximately equal to VL minus Vbe of D1, and thus causes the emitter / base interface of T5 to be reverse biased and charges Cfb. The collector of T5 connected to VH supplies a reverse voltage for the collector-base boundary layer, which loads the CLi.

When V _{eln changes} to the low level, T1 switches off and thus also T4, so that the output signal is no longer held at ground potential. When T1 is switched off, the potential at the base of T2 increases, both T2 and T3 switch on and the potential at node A and the voltage V _out increase in the direction of VH. Assuming for a moment that T5 is absent, the transistor effect of T2 would be limited to the area where node A is more than about two to three Vbe voltage drops below VL because R1 would not be able to carry current to deliver to the base of T2 when the voltage difference at R1 becomes zero. In the present circuit, the voltage due to the precharge on Cfb is capacitively coupled to node B, which thereby rises to a potential V _out plus the precharge voltage (VL minus Vbe) and thus causes node B to rise considerably above the precharge potential (VL minus Vbe) . The voltage rise enables T2 and T3 to remain conductive until V _out essentially reaches VH; the desired goal has been achieved. As V _out increases, the internal load capacitance CLi, which is formed by blocking the collector-base junction of T5, acts as a limiter for the rise time of the output signal. As will be explained later, the ratio of Cfb and CLi can be adjusted during the manufacturing process so that both the desired feedback and the desired internal load capacity result. It should be noted here that, unlike in the prior art (FIG. 1), this circuit does not have a relatively large parasitic capacitance Cp between the output and ground.

Fig. 5A is an illustration of the diode characteristics of the capacitive element T5; thereafter it consists of pn-junction diodes connected in series, namely the emitter-base diode, ie the first pn-junction diode 10, the base-collector diode ie the second pn-junction diode 12 and the collector-isolation diode, ie the third pn - Boundary layer diode, 14. All of these three pn boundary layers are permanently polarized in the reverse direction. The first pn junction diode 10 is initially kept at the voltage (VL minus Vbe) via the output terminal B and at zero V via the input terminal A. The second pn junction diode 12 lies between the voltages VH and and zero V. When V _out rises, the first pn junction diode 10 remains polarized in the reverse direction, since the output terminal B is capacitively coupled so that it assumes a higher potential than the input terminal A. ; the second pn junction diode 12 is _made between the voltages VH and V,

Fig. 5B shows schematically the purely capacitive effect of T5 between terminals A and B. It should be noted that Cfb and CLi are shown as variable capacitances, since they are formed by reverse polarized pn boundary layers (junction capacitance), the different Reverse voltage conditions are subject. The third pn junction diode 14 in Fig. 5A is shown as a fixed capacitance Cp; it actually has no influence on the functioning of the circuit. In cases where Cp is large, as in Fig. 3B, care must be taken that Cp does not affect the effect of bootstrap capacity Cfb.

6 shows a second embodiment of the invention in the form of a NAND driver circuit with two input signals. In Fig. 6 and FIG. 4 corresponding reference numerals relate to elements with similar functions. The circuit consists of an AND gate with two inputs A and B, which are connected to the emitters of the transistors T6A and T6B. The transistor D4 connected as a diode between the base and the collector of T6A and T6B prevents them from reaching deep into the saturation region. The T6A and T6B collectors are coupled to the bases of T1 and T7 via resistor R7. The emitters of T1 and T7 are connected to the base of transistor T4, which serves to reduce the voltage to ground potential. The collector of T1 is connected to the input of the amplification transistor T2, as well as to the diodes D2 and D3, which are coupled to VH via R4 to avoid deep saturation of T1. The emitter of T2 is connected to the base of the output driver transistor T3, the emitter of which is in turn connected to the output V _out . The collector of T7 is coupled to the base of T8, whose emitter is connected to the base of T3 to provide additional driver current for T3. The current for driving T2 is provided by the combination T9, R1, R12 and R13, which together are functionally equivalent to D1 and R1 in FIG. 4. The element T5 supplies the voltage-dependent capacitances Cfb and Cli, which are coupled to the output at the emitter of T3. To achieve the desired characteristics, T5 is designed as a bipolar element with five emitters and multiple base contacts; this structure will be discussed in more detail later. Transistors D8, D5 and D6, connected as diodes, help to supply current via T1 and T7 to T4 when the output signal is driven to ground by the value VH. The diode D7 prevents T2 from reaching deep into the saturation range.

• Widerstand R1 zwischen der Basis von T2 und den Emittern entsprechenden Bereichen von T5:
  • R = 2 k9 Ω Widerstand R2 zwischen Emitter von T1 und
• Masse:
  • R2 = 0,4 kΩ Widerstand R3 parallel zu D8:
  • R3 = 2 k9 Widerstand R4 zwischen VH und Kollektor von
• D2:
  • R4 = 5,8 kΩ Widerstand R5 zwischen den Kollektoren von
• D2 und D4:
  • R = 0,2 kQ Widerstand R6 zwischen den Basisanschlüssen von T6A und D4: R6 = 1 k9
  • Widerstand R7 zwischen den Kollektoren von T6A, T6B und der Basis von T1:
    • R7 = 0,5 kQ Widerstand R8 zwischen Basis und Emitter von
  • T1:
    • R8 = 3 kΩ Widerstand R9 zwischen VH und der Basis von
  • T8:
    • R9 = kΩ Widerstand R10 zwischen VH und dem Kollektor von T3:
    • R10 = 20 Ω Widerstand R11 zwischen dem Emitter von T3 und dem Kollektor von T4:
    • R11 = 20 Ω Widerstand R12 zwischen VH und dem Kollektor von T9:
    • R12 = 0,15 kΩ Widerstand R13 zwischen VH und der Basis von
  • T9:
    • R13 = 3 kΩ Widerstand R 14 zwischen der Basis von T9 und dem einem Kollektor entsprechenden Bereich von T5: R14 = 7 kQ.

An example of the dimensioning of the resistors used in the circuit according to FIG. 6 is given below:

• Resistance R1 between the base of T2 and the areas of T5 corresponding to the emitters:
  • R = 2 k9 Ω resistor R2 between emitter of T1 and
• Dimensions:
  • R2 = 0.4 kΩ resistor R3 parallel to D8:
  • R3 = 2 k9 resistor R4 between VH and collector of
• D2:
  • R4 = 5.8 kΩ resistor R5 between the collectors of
• D2 and D4:
  • R = 0.2 kQ resistor R6 between the base connections of T6A and D4: R6 = 1 k9
  • Resistor R7 between the collectors of T6A, T6B and the base of T1:
    • R7 = 0.5 kQ resistor R8 between base and emitter of
  • T1:
    • R8 = 3 kΩ resistor R9 between VH and the base of
  • T8:
    • R9 = kΩ resistor R10 between VH and the collector of T3:
    • R10 = 20 Ω resistor R11 between the emitter of T3 and the collector of T4:
    • R11 = 20 Ω resistor R12 between VH and the collector of T9:
    • R12 = 0.15 kΩ resistor R13 between VH and the base of
  • T9:
    • R13 = 3 kΩ resistor R 14 between the base of T9 and the area of T5 corresponding to a collector: R14 = 7 kQ.

In operation, the circuit of Figure 6 operates in a similar manner to that of Figure 4 when that; additional logical AND gate at the input is taken into account. If one or both of the input signals A and / or B 'are at the low logic level (zero V), then either T6A or T6B conducts or both and result in the base of T1 and T7 having a potential close to the ground potential ( See zero V). Since T1 and T7 do not conduct, T4 also remains non-conductive. At this point in time, the output signal V _out has already reached a value of essentially VH and maintains this potential until both input signals A and B 'have returned to the high logic level. If both input signals A and B 'have a sufficiently high potential that the transistors T6A and T6B no longer conduct, the potential at the base of T1 and T7 increases so that they become conductive. A current then flows through T1 and T7, to the base T4, which attaches to the transistor T4 and thus pulls V _out against the ground potential. The diodes D8, D5 and D6 together with T1 and T7 supply additional current to T4, depending on the load on the output terminal. The diode D6 connected between the collectors of T1 and T7 balances the collector currents of these two transistors.

When the output signal V _{out is} at ground, T2 and T3 are not conductive. Resistor voltage divider R13 and R14 is now between VH and ground (excluding the base of T5) and the potential at the base of T9 turns on T9 and charges the multiple emitters of T5 to a potential that is approximately one Vbe voltage drop below the potential lies, which is determined by the voltage divider R13 and R14. The This feeds back capacitance Cfb to the same potential. At the same time, the internal load capacity CLi is loaded onto VH. If one or both of the input signals A and / or B fall sufficiently strong to turn on T6A or T6B and thus T1, T7 and T4 go into the blocking state, the potential at the base of both T2 and T8 against VH, T2 and T8 increases conductive, thus T3 and V _out can also rise. As described earlier, the rise in V _out leads to capacitive coupling of the reverse emitters of T5 and to a sufficiently high potential to lower current at T2 until V _out rises to the value VH. If the potential at the multiple emitters of T5 increases, T9 blocks because its emitter has a higher potential than its base.

FIGS. 7A and 7B show the structure of the element T5 as it is built into the circuit of FIG. 6; a common manufacturing process is used for all transistors. The capacitive element is formed in an insulated diffusion trough in the form of a region 16 made of epitaxial N silicon which corresponds to the collector and was produced on a P substrate 18; the tub is delimited by the insulation areas 20. The diffusion well is essentially identical to that used for the other bipolar elements on the circuit board. Although the remaining transistor structures on the substrate use a buried N + subcollector, one is missing in the capacitive element in order to minimize the density of the insulation faults (so-called pipe faults) and to achieve maximum collector resistance. For the same reason, the contact to the collector is made in an extension of the area 16 corresponding to the collector. A single region 22 corresponding to the base having a P-type conductivity is diffused within the region 16 corresponding to the collector and a plurality of regions 24, for example 5, corresponding to the emitter are diffused within the region 22 corresponding to the base. A suitable insulation layer 26 covers the surface of the Elements with the exception of the contact holes, at which the conductor tracks not shown above the structure form an ohmic contact with the different parts of the semiconductor substrate shown. All areas corresponding to the emitter are connected to a common conductor which has finger-like emissions which extend along the areas 24 corresponding to the emitter. In a similar manner, multiple contacts, for example six, are provided for contacting the area 22 corresponding to the base.

The capacitance of the feedback capacitor Cfb can be varied by increasing or decreasing the number and size (i.e. the area of the boundary layer) of the emitter regions. The value of Cfb can be changed with little or no change in the capacitance of the base-collector interface so that the ratio of Cfb to CLi can also be adjusted. Since the area 16 corresponding to the collector is connected directly to VH, the normally large capacitance collector insulation and collector substrate are isolated from the active terminals of the element.

The description so far has referred to NPN transistors; however, it is readily possible for the person skilled in the art to use PNP-type ones instead of NPN transistors with the aid of the known replacement rules. The capacitive element labeled T5 has been shown in the drawings with the symbols for a bipolar transistor; this was done mainly to underline the structural similarities of the element with conventional bipolar transistors. However, it must be emphasized that element 5 does not operate in an area where transistor action occurs.

Claims (10)

1. Integrated semiconductor barrier layer capacitance having a first p-n junction diode (10, Fig. 5a) and a second p-n junction diode (12) which is oppositely poled with respect to the first p-n junction diode, and in which all the p-n junction diodes are operated in the backward direction, characterized in that the first diode (10), the second diode (12) and a third p-n junction diode (14) are arranged in series between a reference potential (ground, Fig. 5A) and an output terminal (B), the third diode (14) being poled in the same direction as the first diode (10), and that an input terminal (A) is connected between the first and the second p-n junction diodes, and that a bias potential (VH) is connected to a terminal between the second and the third p-n junction diodes so that the capacitance of the first p-n junction diode provided between the input terminal (A in Fig. 5) and the output terminal (B in Fig. 5) is separated by the capacitance of the second p-n junction diode from the reference potential connected to the third p-n junction diode.

2. Semiconductor barrier layer capacitance as claimed in claim 1, characterized in that the p-n junction diodes are provided by a single transistor structure having an emitter, a base and a collector formed in a semiconductor chip, the first p-n junction diode comprising a region (24, Fig. 7) corresponding to the emitter of the transistor and a region (22) corresponding to the base of the transistor, the second p-n junction diode comprising the region (22) corresponding to the base and a region (16) corresponding to the collector, and the third p-n . junction diode comprising the region (16) corresponding to the collector and an isolation region (18, 20) isolating the transistor structure in the semiconductor chip.

3. Semiconductor barrier layer capacitance as claimed in claim 2, characterized in that a plurality of the regions (24, Fig. 7A) each corresponding to the emitter are arranged in a common region (22) corresponding to the base, and are connected to a common output terminal.

4. Semiconductor barrier layer capacitance as claimed in claim 2 or 3, characterized in that a constant biasing potential (VH) is applied at the bias potential terminal.

5. Bootstrap circuit comprising a semiconductor barrier layer capacitance as claimed in any one of claims 1 to 4, characterized in that the semiconductor barrier layer capacitance (T5, Fig. 4) is arranged as a feedback device in an integrated bipolar bootstrap circuit, that the output signal of at least one amplifier stage (T2, T3) is connected to the input terminal (A) of the semiconductor barrier layer capacitance, and that the output terminal (B) of the semiconductor barrier layer capacitance transfers the feedback signal.

6. Bootstrap circuit as claimed in claim 5, characterized in that the amplifier stage comprises an emitter follower (T2, T3) of the Darlington type.

7. Bootstrap circuit as claimed in claim 6, characterized in that the bias potential terminal (VH, Fig. 5A) of the semiconductor barrier layer capacitance (T5) is connected to a current source for the amplifier stage.

8. Bootstrap circuit as claimed in one of claims 5 to 7, characterized in that between the supply voltage and the input terminal (A) of the semiconductor barrier layer capacitance (T5) a voltage divider (R13, R14) is arranged having its centre tap connected to the base of a transistor (T9) which with its collector is connected via a resistor (R12) to the supply voltage, and with its emitter to the output terminal of the semiconductor barrier layer (T5), as well as via a resistor (R1) to the base of the first transistor (T2) of the emitter follower.

9. Bootstrap circuit as claimed in claim 8, characterized in that the base and the emitter of an input transistor (T1 ) are respectively connected to the base and the emitter, of a second transistor (T7), that the collector of the second transistor (T7) is connected to the base of a third transistor (T8) and via a resistor (R9) to the supply voltage, and that the collector of the third transistor (T8) is connected to the supply voltage and its emitter to the base of the second transistor (T3) of the emitter follower.

10. Bootstrap circuit as claimed in claim 9, characterized in that the collector of the input transistor (T1) is connected to the collector of a fourth transistor (D6) which is connected as a diode and has its emitter connected to the collector of the second transistor (D7), that the, base of the fourth transistor (D6) is connected to the emitter of a fifth transistor (D5) which is connected as a diode and has its collector connected to the base of the second transistor (T3) of the emitter follower, and that a diode (D8) is connected across the base and emitter of the second transistor (T3) of the emitter follower.

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