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DK2657939T3 - En halvlederhukommelse med næsten ens RAM- og ROM-celler - Google Patents

En halvlederhukommelse med næsten ens RAM- og ROM-celler Download PDF

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Publication number
DK2657939T3
DK2657939T3 DK12165659.9T DK12165659T DK2657939T3 DK 2657939 T3 DK2657939 T3 DK 2657939T3 DK 12165659 T DK12165659 T DK 12165659T DK 2657939 T3 DK2657939 T3 DK 2657939T3
Authority
DK
Denmark
Prior art keywords
memory cell
memory
transistor
semiconductor memory
cell circuit
Prior art date
Application number
DK12165659.9T
Other languages
English (en)
Inventor
Dan Christian Raun Jensen
Original Assignee
Gn Resound As
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gn Resound As filed Critical Gn Resound As
Application granted granted Critical
Publication of DK2657939T3 publication Critical patent/DK2657939T3/da

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Claims (12)

1. En halvlederhukommelse med et array af volatile hukommelsesceller, hvor individuelle volatile hukommelsesceller har transistorer, der er forbundet i et første hukommelsescellekredsløb, og med mindst én ikke-volatil hukommelsescelle, der har transistorer, der er forbundet i et andet hukommelsescellekredsløb, hvor det første hukommelsescellekredsløb har mindst én transistor, der er tilføjet det andet hukommelsescellekredsløb, og hvor lækstrømme tvinger det andet hukommelsescellekredsløb ind i dets logiske tilstand, når halvlederhukommelsen strømforsynes, kendetegnet ved, at en forskel mellem et antal transistorer i det første hukommelsescellekredsløb og et antal transistorer i det andet hukommelsescellekredsløb opnås ved udeladelse af diffusion of en n- eller p-region for en transistor i det andet hukommelsescellekredsløb.
2. En halvlederhukommelse ifølge krav 1, hvor det første hukommelsescellekredsløb er et statisk første hukommelsescellekredsløb.
3. En halvlederhukommelse ifølge krav 1 eller 2, hvor det første hukommelsescellekredsløb indbefatter transistorer, der er forbundet som to krydskoblede invertere.
4. En halvlederhukommelse ifølge krav 3, hvor de to krydskoblede invertere omfatter felt-effekt transistorer.
5. En halvlederhukommelse ifølge krav 3, hvor de to krydskoblede invertere omfatter bipolære transistorer.
6. En halvlederhukommelse ifølge et hvilket som helst af de foregående krav, fremstillet i CMOS.
7. En halvlederhukommelse ifølge et hvilket som helst af de foregående krav, hvor hukommelsen er en multiport hukommelse.
8. En halvlederhukommelse ifølge et hvilket som helst af de foregående krav, hvor de ikke-volatile hukommelsesceller er maske-programmerbare ikke-volatile hukommelsesceller.
9. En halvlederhukommelse ifølge krav 8, hvor det andet hukommelsescellekredsløb opnås ved tilvejebringelse af en tilsvarende diffusionsmaske.
10. Et høreapparat med en digital signalprocessor med en halvlederhukommelse ifølge et hvilket som helst af de foregående krav.
11. Et høreapparat ifølge krav 10, hvor halvlederhukommelsens ikke-volatile hukommelsesceller indeholder en bootstrap loader.
12. Et høreapparat ifølge krav 10, hvor halvlederhukommelsens ikke-volatile hukommelsesceller indeholder et program til høretabskompensation.
DK12165659.9T 2012-04-26 2012-04-26 En halvlederhukommelse med næsten ens RAM- og ROM-celler DK2657939T3 (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP12165659.9A EP2657939B1 (en) 2012-04-26 2012-04-26 A semiconductor memory with similar RAM and ROM cells

Publications (1)

Publication Number Publication Date
DK2657939T3 true DK2657939T3 (da) 2015-08-24

Family

ID=46044480

Family Applications (1)

Application Number Title Priority Date Filing Date
DK12165659.9T DK2657939T3 (da) 2012-04-26 2012-04-26 En halvlederhukommelse med næsten ens RAM- og ROM-celler

Country Status (2)

Country Link
EP (1) EP2657939B1 (da)
DK (1) DK2657939T3 (da)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101653314B1 (ko) * 2014-09-17 2016-09-01 엘지전자 주식회사 의류처리장치

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538246A (en) 1982-10-29 1985-08-27 National Semiconductor Corporation Nonvolatile memory cell
US4510584A (en) 1982-12-29 1985-04-09 Mostek Corporation MOS Random access memory cell with nonvolatile storage
US4575819A (en) * 1983-08-01 1986-03-11 Motorola, Inc. Memory with RAM cells and ROM cells
IT1215224B (it) 1983-08-04 1990-01-31 Ates Componenti Elettron Microcalcolatore a struttura integrata munito di memoria ram non volatile.
US5353248A (en) 1992-04-14 1994-10-04 Altera Corporation EEPROM-backed FIFO memory
US5923582A (en) 1997-06-03 1999-07-13 Cypress Semiconductor Corp. SRAM with ROM functionality
JP2004103128A (ja) 2002-09-10 2004-04-02 Renesas Technology Corp 半導体メモリおよび半導体メモリ書き込み制御装置
US6768669B2 (en) * 2002-09-17 2004-07-27 Texas Instruments Incorporated Volatile memory cell reconfigured as a non-volatile memory cell
US7710761B2 (en) * 2007-01-12 2010-05-04 Vns Portfolio Llc CMOS SRAM/ROM unified bit cell
US7760537B2 (en) * 2007-05-31 2010-07-20 Kabushiki Kaisha Toshiba Programmable ROM
WO2009026532A1 (en) * 2007-08-22 2009-02-26 Personics Holdings Inc. Orifice insertion devices and methods
US7920411B2 (en) * 2009-02-25 2011-04-05 Arm Limited Converting SRAM cells to ROM cells

Also Published As

Publication number Publication date
EP2657939A1 (en) 2013-10-30
EP2657939B1 (en) 2015-05-27

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