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DE969465C - Semiconductor element with sharp p-n or p-n-p junctions - Google Patents

Semiconductor element with sharp p-n or p-n-p junctions

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Publication number
DE969465C
DE969465C DES34551A DES0034551A DE969465C DE 969465 C DE969465 C DE 969465C DE S34551 A DES34551 A DE S34551A DE S0034551 A DES0034551 A DE S0034551A DE 969465 C DE969465 C DE 969465C
Authority
DE
Germany
Prior art keywords
protective layer
semiconductor
covered
layer
sharp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DES34551A
Other languages
German (de)
Inventor
Dr Karl Siebertz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to NL109229D priority Critical patent/NL109229C/xx
Priority to NLAANVRAGE7906612,A priority patent/NL189573B/en
Priority to NL269213D priority patent/NL269213A/xx
Priority to NL269212D priority patent/NL269212A/xx
Priority to NL101504D priority patent/NL101504C/xx
Priority to NL107276D priority patent/NL107276C/xx
Priority to DES11109D priority patent/DE911529C/en
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DES34551A priority patent/DE969465C/en
Priority to DES34714A priority patent/DE1115838B/en
Priority to DES34794A priority patent/DE977619C/en
Priority to DES38554A priority patent/DE1012378B/en
Priority to FR1112727D priority patent/FR1112727A/en
Application granted granted Critical
Publication of DE969465C publication Critical patent/DE969465C/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement or ion-optical arrangement
    • H01J37/147—Arrangements for directing or deflecting the discharge along a desired path
    • H01J37/15—External mechanical adjustment of electron or ion optical components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Description

AUSGEGEBEN AM 4. JUNI 1958ISSUED JUNE 4, 1958

S 34551 VIII c 121gS 34551 VIII c 121g

Dr. Karl Siebertz, MünchenDr. Karl Siebertz, Munich

ist als Erfinder genannt wordenhas been named as the inventor

Patenterteilung bekanntgemaciit am 22. Mai 1958Patent announced May 22, 1958

Bei Halbleiterelementen mit scharfen p-n- oder p-n-p-Übergängen, wie z. B. Flächenrichtleitern, Flächentransistoren, Fototransistoren u. dgl., z. B. aus Germanium, Silizium, Verbindungen von EIementen der III. und V. bzw. II. und VI. Gruppe usw., besteht die Gefahr, daß die Oberfläche des Halbleiters keine genügende Isolation besitzt, so daß die scharfen Übergänge von der p- zur n- oder von der n- über die p- zur n-Sohicht durch Oberflächenleitung überbrückt werden. Man hat versucht, zur Vermeidung derartiger ' Oberflächenleitungen die Oberflächen zu formieren und gegebenenfalls mit einem Lack- oder Wachsüberzug zu versehen, welcher elektrisch isolierend und feuchtigkeitsundurchlässig ist. Dk bisherigen Maßnahmen haben jedoch nicht zufriedengestellt. Es sind auch Flächenhalbleiter anordnungen mit festen Schutzschichten bekannt, welche aus Kunststoffen, z. B. aus Araldk, bestehen. Diese boten ebenfalls keinen hinreichenden Schutz gegen Feuchtigkeit, ao Auch bei dem an sich bekannten Einpressen der Transistoren in plastische bzw. polymerisierende Kunststoffmassen, welche zwar elektrisch isolieren, zeigte sich nach mehrmaligem Gebrauch der Transistoren, daß die Masse nicht feuchtigkeitsundurchlässig war. Ein Einbetten der Kontaktspitze mit isolierendem Kunststoff bei Spitzenkristallgkichrichtern diente der Festlegung der Elektrode, nicht aber der Vermeidung von Kriechströmen, wie sie sich bei Halbleiteramofdnüngen mit p-n-Übergängen als schädlich herausgestellt haben.For semiconductor elements with sharp p-n or p-n-p junctions, such as B. surface directional conductors, surface transistors, phototransistors and the like. B. of germanium, silicon, compounds of elements of the III. and V. or II. and VI. group etc., there is a risk that the surface of the semiconductor does not have sufficient insulation, so that the sharp transitions from the p- to the n- or from the n- via the p- to the n-layer are caused by surface conduction be bridged. Attempts have been made to avoid such surface conduction to shape the surfaces and, if necessary, to coat them with a lacquer or wax coating provided, which is electrically insulating and impermeable to moisture is. However, the measures taken so far have not been satisfactory. There are also planar semiconductor arrangements with fixed Protective layers known, which are made of plastics, e.g. B. from Araldk. These also offered no adequate protection against moisture, even with the known pressing in of the Transistors in plastic or polymerizing plastic compounds, which insulate electrically, After repeated use of the transistors, it was found that the mass was not impermeable to moisture was. Embedding the contact tip with insulating plastic in the case of tip crystal rectifiers was used to fix the electrode, but not to avoid leakage currents, as they are with semiconductor fertilizers with p-n junctions turned out to be harmful.

Erfindungsgemäß wird bei einer Flächenihalbleiteranordnung, beispielsweise Flächenrichtleiter,According to the invention, in a surface semiconductor arrangement, for example surface guide,

809 524/15809 524/15

Flächentransistor od. dgl. mit scharfen, p-n- oder p-n-p- bzw. n-p-n-Übergängen eine einwandfreie Isolation der Oberfläche gegen Kriechströme "dadurch erzielt, daß die Oberfläche des Halbleiterkörpers mindestens längs des scharfen Überganges bzw. der scharfen Übergänge mit einer derartigen festen Schutzschicht bedeckt ist, die elektrisch isoliert, feuchtigkeitsundurohlässig ist, auf der Halbleiteroberfläche durch Adhäsion haftet und aus anorganischem Stoff, vorzugsweise einem Oxyd, beispielsweise Quarz, besteht.Flat transistor or the like with sharp, p-n or p-n-p or n-p-n junctions a perfect insulation of the surface against leakage currents "thereby achieved that the surface of the semiconductor body at least along the sharp transition or the sharp transitions are covered with such a solid protective layer that electrically insulates, is moisture-proof on the semiconductor surface adheres by adhesion and made of inorganic material, preferably an oxide, for example Quartz.

Die Isolationsschicht wird z. B. im Hochvakuum aufgedampft, so daß sie einen glasurartigen Überzug bildet, der gleichzeitig elektrisch isoliert und feuchtigkeitsundurchlässig ist. Als derartige Oberflächenbeläge kommen auch Emaillierungs- oder Glasschichten in Frage.The insulation layer is z. B. evaporated in a high vacuum, so that they have a glaze-like coating that is electrically insulated and impermeable to moisture at the same time. As such surface coverings enamelling or glass layers are also possible.

Zweckmäßig wird vor Aufbringen einer solchen Schutzschicht die Oberfläche an der Stelle, an der ao die Schicht aufgebracht wird; einem an sich bekannten Reinigungsverfahren unterzogen. Als besonders zweckmäßig erweist sich eine .Reinigung durch Kathodenzerstäubung, die im selben Gefäß vorgenommen werden kann, in dem nachträglich bzw. anschließend die Hochvakuumbedampfung vorgenommen wird.Before applying such a protective layer, the surface is expediently at the point where ao the layer is applied; subjected to a cleaning process known per se. As special A cleaning by cathodic sputtering in the same vessel proves to be useful can be made in the subsequent or subsequent high vacuum vapor deposition is made.

In der Zeichnung ist eine Ausführungsform der Anordnung nach der Erfindung beispielsweise dargestellt. In the drawing, an embodiment of the arrangement according to the invention is shown for example.

In Fig. ι ist ein Flächentransistor dargestellt, der aus zwei η-Schichten und einer zwischen diesen befindlichen äußerst dünnen ρ-Schicht besteht, i, 2 und 3 bedeuten die drei Elektrodenzuführungen. Erfindungsgemäß ist auf der Oberfläche des Halbleiterkristalls eine die ρ-Schicht vollständig bedeckende Glasurschicht 4 aus reinem, elektrisch gut isolierendem Quarz angeordnet. Das so erhaltene Halbleiterelement bedarf unter Umständen keines weiteren Gehäuseeinbaus. Es liegt im Rahmen der Erfindung, daß unter Umständen die von der Glasur nicht bedeckten Stellen des Halbleiterkörpers, im Beispielsfall die beiden Enden rechts und links, vonKappen, Lackschichten od. dgl. umhüllt sind, welche einen mechanischen Schutz dieser Stellen des Halbleiterkörpers bieten sollen. Eine andere Möglichkeit besteht darin, daß das ganze Halbleiterelement oberflächlich mit Quarz bestäubt und entsprechend von einer Glasurschicht eingehüllt wird.In Fig. Ι a surface transistor is shown, which consists of two η-layers and an extremely thin ρ-layer between them, i, 2 and 3 mean the three electrode leads. According to the invention is on the surface of the semiconductor crystal a glaze layer 4 completely covering the ρ-layer made of pure, electrically well insulating quartz arranged. The semiconductor element thus obtained may need no further housing installation. It is within the scope of the invention that under certain circumstances the areas of the semiconductor body not covered by the glaze, in the example the two Ends right and left, of caps, layers of lacquer or the like. Are encased, which have a mechanical Should provide protection of these points of the semiconductor body. Another possibility is to that the entire semiconductor element is dusted on the surface with quartz and accordingly with a layer of glaze is enveloped.

In Fig. 2 ist eine Fotozelle dargestellt, die aus zwei Halbleiterschichten η und p besteht. 5 und 6 sind die beiden Elektroden. Erfindungsgemäß ist der p-n-Übergang mit einer ringförmigen Quarzglasurschicht 7 durch Aufdampfen im Hochvakuum versehen.In Fig. 2, a photocell is shown, which consists of two semiconductor layers η and p . 5 and 6 are the two electrodes. According to the invention, the pn junction is provided with an annular quartz glaze layer 7 by vapor deposition in a high vacuum.

Das Wesen der Erfindung besteht darin, die isolierende und feuchtigkeitsundurchlässige Schicht durch Adhäsion bzw. Kohäsion auf der Halbleiteroberfläche anzuordnen. An Stelle der Aufbringung durch Bedampfen im Hochvakuum kann sinngemäß auch ein anderes Verfahren -verwendet werden, daß eine Adhäsion bzw. Kohäsion der Schicht bewirkt. Die Schicht kann beispielsweise auch aufgespritzt werden. Es liegt ferner im Rahmen der Erfindung, auf dieselbe Weise auch Oberflächenkriechströme bei. Spitzentransistoren, z. B. zwischen den Kontaktspitzen bzw. -schneiden, zu vermeiden. Bei der Wahl anderer Schutzschichten als Quarz sind unter Umständen solche Stoffe zu bevorzugen, deren Moleküle mindestens teilweise Dipolcharakter haben und die Oberflächenatome des Halbleiterkristalls, vorzugsweise -einkristalle — z. B. durch Oxydation — mindestens teilweise auch chemisch binden.The essence of the invention consists in the insulating and moisture-impermeable layer to be arranged by adhesion or cohesion on the semiconductor surface. Instead of applying By vapor deposition in a high vacuum, a different method can also be used that an adhesion or cohesion of the layer is effected. The layer can for example can also be sprayed on. It is also within the scope of the invention in the same way as well Surface leakage currents at. Tip transistors, e.g. B. between the contact tips or cutting edges, to avoid. When choosing protective layers other than quartz, such layers may be necessary To prefer substances, the molecules of which have at least some dipole character and the surface atoms of the semiconductor crystal, preferably single crystals - z. B. by oxidation - at least partly also chemically bind.

Claims (6)

Patentansprüche:Patent claims: 1. Flächenhalbleiteranordnung, beispielsweise Flächenrichtleiter, Flächentransistor od. dgl. mit scharfen p-n- oder p-n-p- bzw. n-p-n-Übergängen, dadurch gekennzeichnet, daß die Oberfläche des Halbleiterkörpers mindestens längs des scharfen Überganges bzw. der scharfen Übergänge mit einer derartigen festen Schutzschicht bedeckt ist, die elektrisch isoliert, feuchtigkeitsundurchlässig ist, auf der Halbleiteroberfläche durch Adhäsion haftet und aus anorganischem Stoff, vorzugsweise einem Oxyd, beispielsweise Quarz, besteht.1. Area semiconductor arrangement, for example area directional conductor, area transistor or the like with sharp p-n or p-n-p or n-p-n transitions, characterized in that, that the surface of the semiconductor body at least along the sharp transition or the sharp transitions is covered with such a strong protective layer that electrically insulates, is impermeable to moisture, adheres to the semiconductor surface by adhesion and off inorganic substance, preferably an oxide, for example quartz. 2. Anordnung nach Anspruch 1, dadurch ge- go kennzeichnet, daß die ganze Halbleiteranordnung mit der Schutzschicht überzogen ist.2. Arrangement according to claim 1, characterized ge go indicates that the entire semiconductor device is covered with the protective layer. 3. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß die nicht von der Schutzschicht überzogenen Teile des Halbleiterkristalle von einer mechanischen Schutzschicht, beispielsweise einer Lackschicht, überzogen oder von Kappen eingehüllt sind.3. Arrangement according to claim 1, characterized in that that the parts of the semiconductor crystals not covered by the protective layer covered by a mechanical protective layer, for example a layer of lacquer or are encased in caps. 4. Verfahren zur Aufbringung der Schutzschicht nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die Schicht im Hochvakuum aufgedampft oder in einer trockenen Schutzatmosphäre bzw. im Vakuum aufgespritzt wird.4. A method for applying the protective layer according to any one of claims 1 to 3, characterized characterized in that the layer is vapor-deposited in a high vacuum or in a dry protective atmosphere or in a vacuum is sprayed on. 5. Verfahren nach Anspruch 4, dadurch gekennzeichnet, daß die mit der Schutzschicht zu überziehende Oberfläche des Halbleiterkristalls vorher chemisch oder elektrisch gereinigt wird.5. The method according to claim 4, characterized in that the with the protective layer to coating surface of the semiconductor crystal is chemically or electrically cleaned beforehand. 6. Verfahren nach Anspruch 4 und 5, dadurch gekennzeichnet, daß die Oberfläche des Halbleiterkrißtalls vor Aufbringen der Schutzschicht mindestens an der Stelle, an der diese Schutzschicht aufgebracht wird, durch Kathodenzerstäubung gereinigt wird.6. The method according to claim 4 and 5, characterized in that the surface of the Semiconductor crystal before application of the protective layer at least at the point where this protective layer is applied, is cleaned by cathodic sputtering. 115115 In Betracht gezogene Druckschriften: Proc. IRE, Bd. 40, 1952, Nr. 11, S. 1410; USA.-Patentschrift Nr. 2 524 033; schweizerische Patentschrift Nr. 262415; britische Patentschrift Nr. 713 996; iaoDocuments considered: Proc. IRE, Vol. 40, 1952, No. 11, p. 1410; U.S. Patent No. 2,524,033; Swiss Patent No. 262415; British Patent No. 713,996; iao Lexikon der Physik, 1950, Stuttgart, S. 624, rechte Spalte.Lexicon of Physics, 1950, Stuttgart, p. 624, right column. Hierzu 1 Blatt Zeichnungen1 sheet of drawings ©609580/382 8.56 (809524/15 5.58)© 609580/382 8.56 (809524/15 5.58)
DES34551A 1941-08-06 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions Expired DE969465C (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
NL269213D NL269213A (en) 1953-07-28
NL269212D NL269212A (en) 1953-07-28
NL101504D NL101504C (en) 1953-07-28
NL107276D NL107276C (en) 1953-07-28
NL109229D NL109229C (en) 1953-07-28
NLAANVRAGE7906612,A NL189573B (en) 1953-07-28 HINGE FOR A WINDOW WITH A FRAME MADE FROM STRING PROFILES.
DES11109D DE911529C (en) 1941-08-06 1941-08-06 Process for the production of stereo images with the aid of corpuscular beam devices
DES34551A DE969465C (en) 1953-07-28 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A DE1115838B (en) 1953-07-28 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A DE977619C (en) 1953-07-28 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A DE1012378B (en) 1953-07-28 1954-04-05 Semiconductor arrangement with p-n transition
FR1112727D FR1112727A (en) 1953-07-28 1954-07-28 semiconductor element and method of manufacturing said element

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DES34551A DE969465C (en) 1953-07-28 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A DE1115838B (en) 1953-07-28 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A DE977619C (en) 1953-07-28 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A DE1012378B (en) 1953-07-28 1954-04-05 Semiconductor arrangement with p-n transition

Publications (1)

Publication Number Publication Date
DE969465C true DE969465C (en) 1958-06-04

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Family Applications (4)

Application Number Title Priority Date Filing Date
DES34551A Expired DE969465C (en) 1941-08-06 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A Pending DE1115838B (en) 1941-08-06 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A Expired DE977619C (en) 1941-08-06 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A Pending DE1012378B (en) 1941-08-06 1954-04-05 Semiconductor arrangement with p-n transition

Family Applications After (3)

Application Number Title Priority Date Filing Date
DES34714A Pending DE1115838B (en) 1941-08-06 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A Expired DE977619C (en) 1941-08-06 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A Pending DE1012378B (en) 1941-08-06 1954-04-05 Semiconductor arrangement with p-n transition

Country Status (3)

Country Link
DE (4) DE969465C (en)
FR (1) FR1112727A (en)
NL (6) NL101504C (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1163978B (en) * 1961-08-30 1964-02-27 Licentia Gmbh Process for the production of a protective layer on the surfaces of semiconductor bodies for semiconductor components
DE1172777B (en) * 1960-08-30 1964-06-25 Int Standard Electric Corp Semiconductor component with at least one pn junction and method for manufacturing
DE2700463A1 (en) * 1977-01-07 1978-07-13 Siemens Ag Semiconductor component edge passivating process - involves stacking of semiconductor components and passivating outer surface of stack

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Publication number Priority date Publication date Assignee Title
DE1246886B (en) * 1960-07-30 1967-08-10 Elektronik M B H Process for stabilizing and improving the blocking properties of semiconductor components
DE1246888C2 (en) * 1960-11-24 1975-10-23 Semikron, Gesellschaft für Gleichrichterbau und Elektronik m.b.H., 8500 Nürnberg PROCESS FOR PRODUCING RECTIFIER ARRANGEMENTS IN A BRIDGE CIRCUIT FOR SMALL CURRENTS
DE1244966B (en) * 1962-01-17 1967-07-20 Telefunken Patent Process for the production of surface-stabilized semiconductor components
DE2413608C2 (en) * 1974-03-21 1982-09-02 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method for manufacturing a semiconductor component

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CH262415A (en) * 1945-04-28 1949-06-30 Hugh Brittain Francis Crystal rectifier and process for its manufacture.
US2524033A (en) * 1948-02-26 1950-10-03 Bell Telephone Labor Inc Three-electrode circuit element utilizing semiconductive materials
GB713996A (en) * 1951-04-28 1954-08-18 Rca Corp Improvements in transitor devices

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Also Published As

Publication number Publication date
DE1012378B (en) 1957-07-18
NL101504C (en) 1900-01-01
NL109229C (en) 1900-01-01
NL107276C (en) 1900-01-01
FR1112727A (en) 1956-03-19
NL269213A (en) 1900-01-01
DE977619C (en) 1967-08-31
NL269212A (en) 1900-01-01
DE1115838B (en) 1961-10-26
NL189573B (en) 1900-01-01

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