DE9321385U1 - Single-row memory module - Google Patents

Description

lG-78 529

Sun Microsystems, Inc.

SINGLE ROW MEMORY MODULE

BACKGROUND OF THE INVENTION

1. Related applications

This application is related to U.S. patent application serial number 07/795,699, entitled "High-Speed Electrical Signal Interconnect Structure," filed November 21, 1991, and to U.S. patent application serial number 07/886,671, entitled "Bus Architecture for Integrated Data and Video Memory," filed concurrently with this application.

2. Field of the invention

The present invention relates to the field of computer systems and storage hardware. In particular, the invention relates to modular circuit boards that can be combined to form a storage structure in a computer system.

3. Technical background

Single in-line memory modules ("SIMMs") are compact circuit boards designed to accommodate surface mount memory chips. SIMMs are designed to provide compact and easy-to-handle modular memory devices for installation by a user into computer systems designed to accommodate such SIMMs. SIMMs are generally easy to plug into an interconnect in the computer system, from which the SIMM thus receives all of its required power, ground and logic signals.

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A SIMM typically comprises a plurality of random access memory ("RAM") chips mounted on a printed circuit board. Depending on the user's needs, the RAM memory chips may be dynamic RAM (DRAM), non-volatile static RAM (SRAM), or video RAM (VRAM). Because DRAM memory is larger and less expensive than SRAM memory cells, DRAMs are widely used as the primary building blocks of main memory in computer systems. SIMMs with SRAMs and VRAMs have more limited uses for special purposes, such as extremely fast cache memories and video frame buffers, respectively. Because DRAMs make up the majority of a computer system's memory, it is therefore desirable for memory modules to meet a user's computing needs in a flexible manner as the user's requirements change over time. Moreover, it is desirable that the SIMM modules be added to the computer system with as little difficulty as possible for the user, especially with regard to configuring a SIMM in a particular memory structure. To date, SIMMs have generally been designed to provide memory expansion increments of one or more megabytes (MB), but the memory expansion comprises only a portion of the full data path used in the computer system. A leading prior art example of organization and structure is that disclosed in U.S. Patent No. 4,656,605, issued April 7, 1987 to Clayton. Clayton discloses a compact, modular memory circuit board on which are mounted nine memory chips adapted to provide memory expansions with data widths of eight bits (one byte), plus parity bits. Thus, because most computer systems use 32-, 64-, or more-bit data paths, the Clayton-designed SIMM cannot provide memory expansion for the entire data path. Instead, the user must obtain and install multiple SIMMs, and must also perform any other configuration requirements necessary to cause the separate SIMMs to function as a single memory unit, such as setting base addresses for the installed SIMMs.

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As a result, a user who wishes to increase his usable main memory by adding state-of-the-art SIMMs must typically install multiple SIMMs to obtain a memory extension for the entire data path of his computer. This is a consequence of the typical state-of-the-art SIMM architecture, in which the SIMM is constructed on the basis of DRAM devices that have memory extensions that are one byte wide. Thus, in a data path that is 32 bits wide, where a byte is eight bits, a one megabyte main memory extension using state-of-the-art SIMMs would require four one megabyte SIMM modules each to obtain a one megabyte extension of the entire data path.

As will be explained in more detail in the following detailed description, the present invention, among other features, provides a way to provide full data path width memory expansion, thereby freeing the user from configuring and installing multiple SIMM modules to obtain any desired memory expansion.

SUMMARY OF THE INVENTION

A single in-line memory module (SIMM) for memory expansion of a dynamic random access memory (DRAM) is disclosed. A printed circuit board having a plurality of DRAM memory elements mounted thereon is arranged in a 14 4 bit wide data path. The SIMM of the present invention further includes on-board drivers for buffering and driving signals arranged closely adjacent to the memory elements. In addition, electrically conductive traces are routed on the board in a manner to reduce loading and trace capacitance to prevent signal distortion in the distributed memory elements.

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The SIMM also features a high-density dual readout interconnect structure with electrical traces fed from both sides of the board for increased functionality. The SIMM is installed in dedicated sockets one SIMM at a time to provide full-width memory expansion. Finally, symmetrical power and ground traces on the interconnect structure ensure that the SIMM cannot be inserted incorrectly, and physically flipping the SIMM in the connector slot will not reverse the power supply to the SIMM.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present invention will become apparent from the following detailed description given below and from the accompanying drawings of the preferred embodiment of the invention, in which:

Fig. 1a illustrates the electrical circuit diagram of a first side of the single in-line memory module (SIMM) according to the teachings of the present invention,

Fig. Ib illustrates the electrical circuit diagram for a mirror-image arrangement, in which left and right are swapped, of memory elements on a second side of the SIMM,

Fig. 2 illustrates the physical arrangement of the memory elements and drivers arranged on the SIMM,

Fig. 2a is an enlarged view of the dual readout interconnect structure on the SIMM,

Fig. 3 illustrates the conductive layers separated from insulating dielectric material and stacked on top of each other, which are required to make the connections for the electrical circuit diagram shown in Fig. la and 1b,

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Fig. 4 is a description of data, address and logic lines and a summary of address, data and control signals supplied to the SIMM,

Fig. 5 illustrates the connection arrangement of the high-density dual readout interconnect structure used to connect the SIMM to the memory system,

Fig. 6 is a summary of the pinout for signals transmitted to and from the SIMM.

DETAILED DESCRIPTION OF THE INVENTION

A bus architecture for an integrated data and video

memory is disclosed. In the following description, for purposes of explanation, exact numbers, timing, signals, etc. are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these precise details. In other instances, well-known circuits and devices are shown in block diagram form in order not to unnecessarily obscure the present invention.

The preferred embodiment of the SIMM described herein is designed and intended for use with the integrated data and video memory bus disclosed in co-pending U.S. patent application Serial No. 07/886,671, filed May 19, 1992, entitled "A Bus Architecture for Integrated Data and Video Memory."

However, it will be apparent to those skilled in the art that the specifications disclosed herein can and may be changed without departing from the scope of the present invention. Although the preferred embodiment of the present invention is disclosed in terms of the data path width being identical to that of the integrated circuit disclosed in the above-mentioned U.S. patent application

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disclosed data and video memory bus, it will be appreciated that a variation in the design of the bus is within the scope of the present invention, whereby the SIMM can be adapted to the data path width of the integrated memory bus.

Reference is now made to Fig. 1a, which shows an electrical block diagram of memory elements mounted on a first, front side of the SIMM. In Fig. 1a, a plurality of dynamic RAMs (DRAMs) 10 are grouped into two groups 10a and 10b. Each group has nine DRAMs 10. A driver 15 receives control signals and address signals from an external bus arrangement (not shown) via a double-sided connector 30. A plurality of control lines 20 carry RAS (row

access strobe), CAS (column access strobe), WE (write enable) and OE (output enable) control signals from the driver 15 to all DRAMs 10 attached to the SIMM 5. In addition, the driver 15 buffers address signals 21 and then distributes them to all DRAMs 10 attached to the SIMM 5. For the sake of clarity, the exact routing of the data, address and control lines to all DRAMs 10 has been omitted from the present figure. However, as can be seen from Fig. 1a, all DRAMs 10 have four data lines, with DRAMs 10 being any of several commercially available DRAMs having an ¹¹ X 4" configuration. As can be seen below in connection with Fig. 1b, the DRAMs 10 of each of DRAM groups 10a and 10b correspond to mirror-image DRAMs 10 mounted on the opposite side of SIMM 5 and in electrical communication by electrical paths traversing a plurality of vias (not shown).

The exact course of the electrical paths on the SIMM 5 depends on the exact architecture of the memory chips chosen for an implementation of the SIMM 5 in a particular case. However, all SIMMs 5 constructed according to the teachings of the present invention have a full-width data path that extends from the connection

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nector 30 to all components operating on the SIMM 5, including all DRAMs 10, driver 15, and all other logic elements required to implement the desired function of the SIMM 5. As presently preferred, the SIMM 5 has a 144-bit wide data path with 128 data lines (DATA[127:0]), 16 error correction lines (CBW[15:0]) implementing a known error correction code, a RAS signal, two CAS signals, a WE signal, and a reset line. The routing of all control signals 20, address signals 21, and data signals 25 minimizes conductor path capacitance and loading in accordance with the above-mentioned U.S. patent application entitled "High Speed Electric Signal Interconnect Structure," which is assigned to the assignee of the present invention and is incorporated into this application by reference. In terms of path routing, all control signals 20 are routed from driver 15 to the central DRAM 10 of each DRAM group 10a, 10b, 10c and 10d. The DRAMs surrounding the central DRAM 10 are connected to the control signals 20 via short auxiliary paths (not shown) in order to minimize the total capacitance and improve the signal rise times.

In Fig. 3, which will be briefly referred to, is shown the layer arrangement used to distribute all control, address, data, power and ground signals.

Referring briefly to Fig. 1b, a second, rear side of the SIMM 5 is shown. Two additional DRAM groups 10c and 10d, arranged like the DRAM groups 10a and 10b on the front side, are shown in Fig. 1b. Each DRAM 10 in the DRAM groups 10c and 10d similarly has four input lines, in addition to address and control lines, fed from the driver 15 on the front side through conductive vias to the mirror image rear side of the SIMM 5, thereby doubling the available surface area on which DRAMs 10 can be mounted. Moreover, the currently preferred SIMMs 5 utilize DRAMs 10 having a thin, small-dimension package.

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(TSOP - thin small outline package) to reduce the overall thickness of the SIMM 5. When so constructed, the double-sided SIMM 5 of the present invention is no thicker than prior art single-sided SIMMs (for example, as disclosed by Clayton).

Referring briefly to Fig. 4, there is shown the high pin count and density interconnect 30 used to connect the SIMM 5 to the memory module socket (not shown). The interconnect 30 shown in Fig. 4 has 200 pin ends, thus allowing many signals to be passed to and from the SIMM 5. In the preferred embodiment of the SIMM 5, the SIMM 5 is provided with the exact data path architecture compatible with an integrated data and video memory bus, such as the bus described in the above-mentioned co-pending U.S. patent applications assigned to Sun Microsystems, Inc., Mountain View, California, which are hereby incorporated by reference. In particular, the data path architecture implemented on the SIMM 5 includes 128 data lines, 16 error correction code lines (referred to as CBW[15:0] in Fig. 1-6) and, in addition, a plurality of control signals required to perform DRAM memory access. Such control signals, collectively referred to as control lines 20 in Fig. 1a and 1b, include one RAS signal per SIMM 5, two CAS signals, one WE line and one reset line. Thus, it can be seen that the data path used for data transfer to and from the DRAMs 10 is 144 bits wide, not including the control signals 20 used to control the operation of the DRAMs 10. Without taking into account the error correction code signals, designated as CBW[15:0] in Figures 1-6, the actual data path width of the SIMM 5 for writing and reading data to and from memory is 128 bits or 16 bytes, the same as that of the integrated data and video memory bus. Accordingly, the SIMM 5 of the present invention can be incorporated into the memory bus in full-width memory expansion steps.

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The total memory capacity available in a SIMM 5 can be calculated as follows. Depending on the capacity of each RAM 10 mounted on the SIMM 5, the total memory capacity of each SIMM module 5 can be between four megabytes (MB) up to a maximum of 64 MB distributed over a total of 3 6 DRAMs 10. If commercially available 1-Mbit DRAMs 10 with an organization of 256K x 4 are used, four megabytes of memory can be provided in the SIMM 5. Alternatively, when 16-megabit devices become available, the SIMM 5 can easily accommodate these larger 16-megabit devices and provide a total capacity of 64 megabytes on a SIMM 5 mounted with 3 6 DRAMs, because the addressable address space of the SIMM 5 is very large, greater than two gigabits.

The operation of the SIMM 5 is controlled by control signals 20, as briefly explained below. For a complete explanation of the actual operation of the SIMM 5 in conjunction with the integrated data and video bus, the reader is referred to the above-referenced, co-pending U.S. patent application entitled "A Bus Architecture."

Referring now to Figure 2, the physical arrangement of the DRAMs 10 and driver 15 on the SIMM 5 is illustrated. In addition to the DRAM groups 10a and 10b shown on the front of the SIMM 5, it is noted that the SIMM 5 includes two contact areas 50a and 50b at the bottom edge of the SIMM 5. The contact areas 50a and 50b consist of closely spaced conductive contact pads running longitudinally along the bottom edge of the SIMM 5 from pin 0 to pin 199, the number corresponding to that shown in the interconnect map (shown in Figure 4) and in the pinout summary (shown in Figure 6). A detail of the lower edge of the SIMM 5 of Fig. 2 is shown in Fig. 2a, in which an enlarged view of the contact areas 50a and 50b is shown in perspective. From Fig. 2a it can be seen that the contact areas 50a and 50b consist of many closely spaced contact surfaces 35 on the front side of the SIMM 5 and

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a mirror image but electrically separate set of contact pads 3 6 on the back of the SIMM 5. Unlike prior art SIMMs, the SIMM 5 of the present invention doubles the connection capacity of a SIMM by "breaking" the connection between the front and back of the SIMM 5, thus effectively doubling the edge area that can be provided for electrical functions. For the sake of clarity, it should be noted that unlike prior art SIMM modules, which have contact pads spaced 0.1" apart from each other at centers, the contacts 35 and 3 6 of the SIMM 5 are spaced 0.050" apart from each other at centers, with the contact pads 35 and 3 6 themselves having a lateral extension of 0.040" and thus a gap of 0.010" between the contact pads. However, the exact spacing and dimensions are not indicative of the present invention, and it will be apparent to one skilled in the art that many systems of spacing and pad arrangement are possible using the "dual readout" arrangement as shown in Figure 2a in contact areas 50a and 50b. Thus, by working together, the reduced spacing and dual readout arrangements of contact areas 50a and 50b provide for a very greatly improved pin density available for SIMM modules, more than four times that suggested by Clayton. In particular, because 200 pins are available for use with the SIMM 5, the full 144-bit data path width, plus control signals and power and ground connections, are accommodated by the interconnect member 30 and the interconnect areas 50a and 50b of the SIMM 5.

As previously noted in connection with the memory capacities according to the type of DRAMs 10 mounted on the SIMM 5, it should be noted that the main advantage of the SIMM 5 constructed according to the teachings of the present invention is that memory expansion can be built in increments with full data path width. In contrast to memory expansion using SIMMs according to the prior art,

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By using the SIMM 5 when expanding the memory, in particular the memory relating to the integrated data and video memory of the above-mentioned co-pending application, the memory can be expanded SIMM by SIMM and it is not necessary to insert multiple memory modules to achieve a single memory expansion step. This result is mainly due to the inclusion of a complete data path signal path on the SIMM 5, thus facilitating the easy installation of additional memory.

Finally, the interconnect 30 also provides for the supply voltage and ground to be connected to all DRAMs 10 and driver 15. Notably, all of the voltage and ground lines in the interconnect 30 are symmetrically arranged, as can be seen more clearly in Fig. 6. The voltage lines (VCC) and the ground lines (GND) alternate every 16 connections. If a SIMM is accidentally inserted into a memory module socket in the reverse direction, the symmetrical voltage and ground lines prevent the SIMM 5 from being connected to a voltage of reversed polarity and likely being destroyed.

The above has described the physical architecture of a single in-line memory module compatible with integrated data and video memory. It is to be understood that changes and adaptations to the component parts and arrangement of the elements of the present invention may be made by one of ordinary skill in the art without departing from the spirit and scope of the invention. In particular, it is expected that the SIMM 5 may be used in memory arrangements other than the integrated data and video memory incorporated into this application by reference from the above-mentioned co-pending application. However, the SIMM 5 is particularly advantageously designed for use with integrated video memory and the user would derive maximum benefit from use in such a system.

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Although the invention has been described in connection with the preferred embodiment, it is obvious that many alternative adaptations, modifications and applications will be apparent to those skilled in the art in light of the above description.
will be obvious.

Claims (8)

Expectations 1. Single-row memory module comprising the following components: a printed circuit board having a first side and a second side, the printed circuit board having a connection edge, and the connection edge having a plurality of electrical contacts on the first side and the second side of the printed circuit board; a first set of memory elements disposed on the first side of the printed circuit board, the first memory elements having data lines connected to the electrical contacts on the interconnect edge of the printed circuit board; a second set of memory elements disposed on the second side of the printed circuit board, the second memory elements having data lines connected to the electrical contacts on the mating edge of the printed circuit board, and the second set of memory elements being a mirror image of the first set of memory elements; a driver circuit mounted substantially centrally on the printed circuit board, the driver circuit receiving a plurality of control signals via the electrical contacts and transmitting the control signals to the first set of storage elements and the second set of storage elements. 2. A single-row memory module according to claim 1, wherein: the first set of memory elements arranged on the first side of the printed circuit board includes a first subset arranged to the left of the driver circuit and a second subset arranged to the right of the driver circuit; and lG-78 529 the second set of memory elements arranged on the second side of the printed circuit board includes a third subset that is a mirror image of the first subset and a fourth subset that is a mirror image of the second subset. 3. Single-row memory module according to claim 2, wherein the first, second, third and fourth subsets of storage elements each comprise nine storage elements arranged in a three-by-three matrix. 4. Single-row memory module according to claim 3, in which the driver circuit transmits the control signals directly to a central storage element in the three-by-three matrix of the first or second subset of storage elements. 5. Single-row memory module according to claim 1, in which the control signals comprise a column address strobe signal (CAS), a row address strobe signal (RAS), a write enable signal (WE) and an output enable signal (OE). 6. Single-row memory module according to claim 5, in which the driver circuit also drives address lines. 7. Single-row memory module according to claim 1, in which the electrical contacts have symmetrical power and ground contacts so that the single-row memory module will not be damaged if the single-row memory module is incorrectly inserted. 8. The single-in-line memory module of claim 1, wherein the single-in-line memory module provides data in a first data path that is at least as wide as a second data path used in an associated central processing unit.