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DE9105035U1 - Multilayer PCB - Google Patents

Multilayer PCB

Info

Publication number
DE9105035U1
DE9105035U1 DE9105035U DE9105035U DE9105035U1 DE 9105035 U1 DE9105035 U1 DE 9105035U1 DE 9105035 U DE9105035 U DE 9105035U DE 9105035 U DE9105035 U DE 9105035U DE 9105035 U1 DE9105035 U1 DE 9105035U1
Authority
DE
Germany
Prior art keywords
prepreg
conductor
circuit board
levels
conductor levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE9105035U
Other languages
German (de)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE9105035U priority Critical patent/DE9105035U1/en
Publication of DE9105035U1 publication Critical patent/DE9105035U1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

G 4 4 19G4 4 19

Siemens AktiengesellschaftSiemens AG

Mehrlagen-Leiterplatte
5Multilayer PCB
5

Die Erfindung betrifft eine Mehrlagen-Leiterplatte gemäß dem Oberbegriff des Anspruchs 1.The invention relates to a multilayer printed circuit board according to the preamble of claim 1.

Mehrlagen-Leiterplatten, die z. B. in der DE-OS 36 05 474 und dem Buch "Hochtechnologie-Multilayer" von H. Müller, Eugen-G.-Leuze-Verlag, 1988, Seiten 18 bis 24 beschrieben sind, bestehen aus übereinandergeschichteten Leiterebenen, die durch Zwischenlagen elektrisch gegeneinander isoliert sind. Im allgemeinen sind je zwei Leiterebenen auf den beiden Seiten eines Isolierstoffträgers, z. B. aus Epoxiglas-Laminat, aufgebracht. Die so zweiseitig kaschierten Kerne werden mittels Prepregs verbunden. Dies sind Klebefolien, z. B. aus harzimprägniertem Glasgewebe. Bei erhöhter Temperatur schmilzt das Harz und härtet unter Druck und Temperatur aus. Die elektrischen Verbindungen zwisehen den Leiterebenen werden mittels Durchkontaktierungen hergestellt. Hierzu werden an den Kontaktstellen in den zu verbindenden Leiterebenen Lötaugen vorgesehen, wobei die einzelnen Lötaugen einer Durchkontaktierung übereinanderliegen. Nach dem Aufeinanderschichten und Verkleben der Kerne wird die Mehrlagen-Leiterplatte an den Stellen, an denen sich die Lötaugen befinden, durchbohrt. Die Bohrung wird metallisiert, im allgemeinen verkupfert, so daß die Lötaugen und damit die zugehörigen Leiter über eine Metallhülse elektrisch miteinander verbunden sind. Solche Durchkontaktierungen beanspruchen auch in den Leiterebenen Platz, in denen sich kein Anschluß an die Metallhülse befindet. Man setzt daher zur besseren Ausnutzung der Leiterebenenflächen vor allem für die elektrische Verbindung zwischen innen liegenden Leiterebenen sogenannte partielle oder verborgene Durchkontaktierungen ein, für die jeweils nur ein Kern zwischen zwei Lötaugen durchbohrt und die Bohrung metallisiert wird. Für die elektrische Verbindung von außen liegenden Leitern können Sacklöcher gebohrt und metallisiert werden. Alle durch Bohrungen hergestellten elektrischen Verbindungen habenMultilayer circuit boards, which are described for example in DE-OS 36 05 474 and the book "Hochtechnologie-Multilayer" by H. Müller, Eugen-G.-Leuze-Verlag, 1988, pages 18 to 24, consist of conductor layers that are layered on top of each other and are electrically insulated from each other by intermediate layers. In general, two conductor layers are applied to each side of an insulating material carrier, e.g. made of epoxy glass laminate. The cores, which are laminated on both sides in this way, are connected using prepregs. These are adhesive films, e.g. made of resin-impregnated glass fabric. At elevated temperatures, the resin melts and hardens under pressure and temperature. The electrical connections between the conductor layers are made using through-holes. For this purpose, soldering pads are provided at the contact points in the conductor layers to be connected, with the individual soldering pads of a through-hole lying one above the other. After the cores have been stacked and glued together, the multilayer circuit board is drilled through at the points where the soldering pads are located. The hole is metallized, generally copper-plated, so that the soldering pads and thus the associated conductors are electrically connected to one another via a metal sleeve. Such through-holes also take up space in the conductor levels where there is no connection to the metal sleeve. So-called partial or hidden through-holes are therefore used to make better use of the conductor level surfaces, especially for the electrical connection between internal conductor levels, for which only one core is drilled through between two soldering pads and the hole is metallized. Blind holes can be drilled and metallized for the electrical connection of external conductors. All electrical connections made through holes have

02 0102 01

wegen der notwendigen Lötaugen den Nachteil, daß sie viel Platz in den Leiterebenen beanspruchen. Auch beeinträchtigen die Bohrungen, vor allem, wenn sie durch mehrere Leiterebenen gehen, die elektrischen Eigenschaften der betroffenen Leiter.Because of the necessary soldering pads, they have the disadvantage that they take up a lot of space in the conductor levels. The holes also impair the electrical properties of the conductors concerned, especially if they go through several conductor levels.

Der vorliegenden Erfindung liegt die Aufgabe zugrunde, eine Mehrlagen-Leiterplatte zu schaffen, in der die Anzahl der durch Leiterebenen führenden Bohrungen im Vergleich zu den bekannten Mehrlagen-Leiterplatten verringert ist. 10The present invention is based on the object of creating a multilayer circuit board in which the number of holes leading through conductor levels is reduced compared to the known multilayer circuit boards. 10

Erfindungsgemäß wird diese Aufgabe mit den im kennzeichnenden Teil des Anspruchs 1 angegebenen Maßnahmen gelöst.According to the invention, this object is achieved by the measures specified in the characterizing part of claim 1.

In der neuen Mehrlagen-Leiterplatte erfordern die elektrischen Verbindungen zwischen Leiterebenen, die nur durch ein Prepreg getrennt sind, keine Bohrung. Durch die Aussparungen im Prepreg werden die Leiter unmittelbar kontaktiert. Die Kontaktstelle kann gelötet werden, indem die Aussparung im Prepreg oder ein Leiter an der Kontaktstelle mit Lötpaste bedruckt wird. Auf das Verlöten kann im allgemeinen verzichtet werden, da die Haftwirkung des Prepregs für einen ausreichenden Kontaktdruck sorgt. Zur Erzielung eines einwandfreien Kontaktes können die Kontaktflächen mit einem Flußmittel überzogen werden.In the new multilayer circuit board, the electrical connections between conductor levels that are only separated by a prepreg do not require drilling. The conductors are directly contacted through the recesses in the prepreg. The contact point can be soldered by printing solder paste on the recess in the prepreg or a conductor at the contact point. Soldering is generally not necessary, as the adhesive effect of the prepreg ensures sufficient contact pressure. To achieve perfect contact, the contact surfaces can be coated with a flux.

Anhand der Zeichnung werden im folgenden die Erfindung sowie Ausgestaltungen und Ergänzungen näher beschrieben und erläutert. The invention as well as refinements and additions are described and explained in more detail below with reference to the drawing.

Figur 1 veranschaulicht in einer Schnittdarstellung den Aufbau einer neuen Mehrlagen-Leiterplatte,Figure 1 shows a sectional view of the structure of a new multilayer printed circuit board,

Figur 2 zeigt Aufsichten von Leiterebenen mit zu kontaktierenden Leitern und einem Prepreg als Zwischenlage.Figure 2 shows top views of conductor levels with conductors to be contacted and a prepreg as an intermediate layer.

In Figur 1 sind mit LEI, LE2 ... LE6 Leiterebenen einer Mehrlagen-Leiterplatte bezeichnet, die jeweils aus mehreren aus einem mit Kupfer kaschierten Kern geätzten Leiterbahnen bestehen. Die inneren Leiterebenen LE2, LE3, LEA, LE5 sitzen paarweise auf je einem Isolierstoffträger TRl, TR2 und bildenIn Figure 1, LEI, LE2 ... LE6 designate conductor levels of a multilayer circuit board, each of which consists of several conductor tracks etched from a core clad with copper. The inner conductor levels LE2, LE3, LEA, LE5 are located in pairs on an insulating material carrier TR1, TR2 and form

02 02 02 02

G 44 1 9 ,, #; G 44 1 9 ,, #;

mit diesem jeweils einen beidseitig kaschierten Kern Kl bzw. K2. Die äußeren Leiterebenen LEI, LE6 bilden die Außenseiten der Mehrlagen-Leiterplatte. Die Kerne Kl, K2 sind miteinander mittels eines Prepregs PR2 verklebt, das gleichzeitig die Leiterebenen LE3, LE4 gegeneinander isoliert. Mittels Prepregs PRl, PR3 sind die Leiterebenen LEI, LE6 auf die Kerne Kl, K2 geklebt.with this a core Kl or K2 laminated on both sides. The outer conductor levels LEI, LE6 form the outsides of the multilayer circuit board. The cores Kl, K2 are glued together using a prepreg PR2, which simultaneously insulates the conductor levels LE3, LE4 from each other. The conductor levels LEI, LE6 are glued to the cores Kl, K2 using prepregs PRl, PR3.

Die elektrischen Verbindungen zwischen den Leiterebenen LE2, LE3 auf dem Kern Kl und den Leiterebenen LE4, LE5 des Kernes K2 sind in bekannter Weise mittels metallisierter Bohrung BRl, BR2 als sogenannte partielle oder verborgene Durchkontaktierungen hergestellt. Die elektrischen Verbindungen zwischen den Leiterebenen LE3, LE4 sind durch Druckkontakt hergestellt. Hierzu werden die Leiterebenen LE3, LE4 mit einem fotoempfindlichen Lack beschichtet, an der Kontaktstelle belichtet und freientwickelt. In einem galvanischen Prozeß werden an den freientwickelten Flächen Verstärkungen Vl, V2 aufgebaut, bis deren gesamte Stärke etwa gleich der Dicke des Prepregs PR2 ist. In diesem wird an der Kontaktstelle eine Durchbrechung DR angebracht, deren Form der Form der Verstärkungen Vl, V2 entspricht. Im Falle, daß die Durchbrechung gebohrt wird, ist sie selbstverständlich kreisrund, vorteilhaft wird sie jedoch gestanzt, so daß sie auch rechteckig sein kann.The electrical connections between the conductor levels LE2, LE3 on the core K1 and the conductor levels LE4, LE5 of the core K2 are made in a known manner by means of metallized holes BR1, BR2 as so-called partial or hidden through-holes. The electrical connections between the conductor levels LE3, LE4 are made by pressure contact. For this purpose, the conductor levels LE3, LE4 are coated with a photosensitive lacquer, exposed at the contact point and freely developed. In a galvanic process, reinforcements Vl, V2 are built up on the freely developed surfaces until their total thickness is approximately equal to the thickness of the prepreg PR2. In this, an opening DR is made at the contact point, the shape of which corresponds to the shape of the reinforcements Vl, V2. If the opening is drilled, it is of course circular, but it is advantageous to punch it so that it can also be rectangular.

Figur 2 zeigt eine Aufsicht auf die beiden Leiterebenen LE3, LE4. Die Leiterbahnen sind mit LB, LB1 bezeichnet. Die Verstärkungen Vl, V2 sind nicht breiter als die Leiterbahnen. Damit sich eine ausreichende Kontaktfläche ergibt und die Verstärkungen eine genügende Festigkeit haben, sind sie jedoch rechteckförmig länglich ausgebildet. Die Durchbrechung DR im Prepreg PR2 ist in diesem Falle ein schmaler Schlitz.Figure 2 shows a top view of the two conductor levels LE3, LE4. The conductor tracks are labeled LB, LB 1. The reinforcements Vl, V2 are not wider than the conductor tracks. However, to ensure that there is a sufficient contact area and that the reinforcements have sufficient strength, they are rectangularly elongated. The opening DR in the prepreg PR2 is a narrow slot in this case.

Nach dem Zusammenpressen und Erhitzen der Kerne Kl und K2 sind die Leiterebenen LE3, LE4 miteinander verbunden, und zwar durch einfache Druckkontaktierung ohne Bohrung. Die Haftwirkung des Prepregs sorgt für einen ausreichenden Kontaktdruck. Die Verbindungen durch Isolierstoffträger erfolgen über Boh-After pressing together and heating the cores Kl and K2, the conductor levels LE3, LE4 are connected to each other, namely by simple pressure contact without drilling. The adhesive effect of the prepreg ensures sufficient contact pressure. The connections through insulating material carriers are made via drilling.

02 03 ... .; .,,. ..02 03 ... . ; .,,. ..

G 4 4 19G4 4 19

rungen BRl, BR2. Dadurch ergeben sich zahlreiche Varianten zum Verbinden verschiedener Leiterebenen, und man ist in der Wahl der Leiterbahnen und der Verbindungsstellen sehr flexibel, zumal, wie anhand von Figur 2 gezeigt, die Druckkontaktierung praktisch keinen zusätzlichen Platz beansprucht.BR1, BR2. This results in numerous variants for connecting different conductor levels, and one is very flexible in the choice of conductor tracks and connection points, especially since, as shown in Figure 2, the pressure contact requires practically no additional space.

Selbstverständlich brauchen nicht alle Verbindungen zwischen durch Prepregs getrennte Leiterebenen durch Druckkontaktierung hergestellt zu werden. Beispielsweise sind die Verbindungen der beiden äußeren Leiterebenen LEI, LE2 bzw. LE5, LE6 nach dem Verkleben durch metallisierte Sacklöcher SLl, SL2 hergestellt.Of course, not all connections between conductor levels separated by prepregs need to be made by pressure contact. For example, the connections of the two outer conductor levels LEI, LE2 and LE5, LE6 are made after gluing by means of metalized blind holes SL1, SL2.

Eine sechslagige Leiterplatte gemäß Figur 1 kann in folgenden Verfahrensschritten hergestellt werden. Zunächst werden beide doppeltkaschierten Isolierstoffträger, die späteren Kerne Kl, K2, mit den Bohrungen BRl, BR2 versehen und die Leiterebenen LE2, LE5 hergestellt. Mit den Prepregs PRl, PR3 werden Kupferfolien auf die Leiterebenen LE2, LE5 geklebt. Mit dem Verkleben erhält man zwei dreilagige Teilkerne, auf denen die Leiterebenen LE3, LE4 hergestellt werden können. Die Bohrungen BRl, BR2 werden galvanisch metallisiert; in demselben Arbeitsgang können die Verstärkungen Vl, V2 erzeugt werden. Das Prepreg PR2 wird an der Kontaktstelle mit der Durchbrechung DR versehen, und die beiden Teilkerne werden verpreßt, wobei die Kontaktflächen der Verstärkungen Vl, V2 aufeinandergedrückt und elektrisch verbunden werden. Anschließend werden aus den die Außenseiten bildenden Kupferfolien die Leiterebenen LEI, LE6 geätzt und die Sacklöcher SLl, SL2 metallisiert.A six-layer circuit board according to Figure 1 can be manufactured in the following process steps. First, both double-clad insulating material carriers, the later cores K1, K2, are provided with the holes BRl, BR2 and the conductor levels LE2, LE5 are produced. Using the prepregs PRl, PR3, copper foils are glued to the conductor levels LE2, LE5. By gluing, two three-layer partial cores are obtained, on which the conductor levels LE3, LE4 can be manufactured. The holes BRl, BR2 are galvanically metallized; the reinforcements Vl, V2 can be produced in the same operation. The prepreg PR2 is provided with the opening DR at the contact point and the two partial cores are pressed together, whereby the contact surfaces of the reinforcements Vl, V2 are pressed together and electrically connected. The conductor levels LEI, LE6 are then etched from the copper foils forming the outer sides and the blind holes SLl, SL2 are metallized.

02 0402 04

Claims (4)

G 4 4 19 SchutzansprücheG 4 4 19 Protection claims 1. Mehrlagen-Leiterplatte mit mehreren Leiterebenen, die durch isolierende Zwischenlagen voneinander getrennt sind, von denen mindestens eine ein Prepreg ist und mit senkrecht zu den Leiterebenen, in Bohrungen verlaufenden Durchkontaktierungen zwischen Leiterebenen, dadurch gekennzeichnet, daß zur Kontaktierung von zwei durch das Prepreg (PR) gegeneinander isolierten Leiterbahnen (LB, LB1) mindestens eine von diesen eine Verstärkung (V, V) aufweist, derart, daß die Summe der Verstärkungen etwa gleich der Dicke des Prepregs ist, und daß das Prepreg an der Kontaktstelle mit einer Durchbrechung (DR) versehen ist.1. Multilayer printed circuit board with several conductor levels which are separated from one another by insulating intermediate layers, at least one of which is a prepreg and with through-contacts running perpendicular to the conductor levels in bores between conductor levels, characterized in that for contacting two conductor tracks (LB, LB 1 ) insulated from one another by the prepreg (PR), at least one of these has a reinforcement (V, V) such that the sum of the reinforcements is approximately equal to the thickness of the prepreg, and that the prepreg is provided with an opening (DR) at the contact point. 2. Mehrlagen-Leiterplatte nach Anspruch 1, dadurch gekennzeichnet, daß die beiden Leiterbahnen (LB, LB1) an der Kontaktstelle jeweils eine Stärke von etwa der halben Dicke des Prepregs haben.2. Multilayer printed circuit board according to claim 1, characterized in that the two conductor tracks (LB, LB 1 ) at the contact point each have a thickness of approximately half the thickness of the prepreg. 3. Mehrlagen-Leiterplatte nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Durchbrechung (DR) des Prepregs (PR) gestanzt ist und die Form eines Rechtecks hat, dessen Breite etwa gleich der der Leiterbahnen (LB, LB1) ist.3. Multilayer printed circuit board according to claim 1 or 2, characterized in that the opening (DR) of the prepreg (PR) is punched and has the shape of a rectangle whose width is approximately equal to that of the conductor tracks (LB, LB 1 ). 4. Mehrlagen-Leiterplatte nach Anspruch 1 bis 3, dadurch gekennzeichnet, daß die Leiter durch galvanischen Auftrag von Kupfer verstärkt sind.4. Multilayer printed circuit board according to claims 1 to 3, characterized in that the conductors are reinforced by galvanic application of copper. 03 0103 01
DE9105035U 1991-04-24 1991-04-24 Multilayer PCB Expired - Lifetime DE9105035U1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE9105035U DE9105035U1 (en) 1991-04-24 1991-04-24 Multilayer PCB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE9105035U DE9105035U1 (en) 1991-04-24 1991-04-24 Multilayer PCB

Publications (1)

Publication Number Publication Date
DE9105035U1 true DE9105035U1 (en) 1992-06-17

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ID=6866643

Family Applications (1)

Application Number Title Priority Date Filing Date
DE9105035U Expired - Lifetime DE9105035U1 (en) 1991-04-24 1991-04-24 Multilayer PCB

Country Status (1)

Country Link
DE (1) DE9105035U1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530840A1 (en) * 1991-09-05 1993-03-10 Matsushita Electric Industrial Co., Ltd. Electric circuit board module and method for producing electric circuit board module
DE9403108U1 (en) * 1994-02-24 1994-04-14 Siemens AG, 80333 München Low-inductance high-current busbar for converter modules

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530840A1 (en) * 1991-09-05 1993-03-10 Matsushita Electric Industrial Co., Ltd. Electric circuit board module and method for producing electric circuit board module
US5406459A (en) * 1991-09-05 1995-04-11 Matsushita Electric Industrial Co., Ltd. Surface mounting module for an electric circuit board
DE9403108U1 (en) * 1994-02-24 1994-04-14 Siemens AG, 80333 München Low-inductance high-current busbar for converter modules

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