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DE69941287D1 - Verfahren und apparat für arithmetische operationen - Google Patents

Verfahren und apparat für arithmetische operationen

Info

Publication number
DE69941287D1
DE69941287D1 DE69941287T DE69941287T DE69941287D1 DE 69941287 D1 DE69941287 D1 DE 69941287D1 DE 69941287 T DE69941287 T DE 69941287T DE 69941287 T DE69941287 T DE 69941287T DE 69941287 D1 DE69941287 D1 DE 69941287D1
Authority
DE
Germany
Prior art keywords
arithmetic operations
arithmetic
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69941287T
Other languages
English (en)
Inventor
Tomochika Kanakogi
Masaitsu Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of DE69941287D1 publication Critical patent/DE69941287D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE69941287T 1998-01-21 1999-01-21 Verfahren und apparat für arithmetische operationen Expired - Lifetime DE69941287D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP937198 1998-01-21
PCT/JP1999/000237 WO1999038088A1 (fr) 1998-01-21 1999-01-21 Procede et dispositif pour operation arithmetique

Publications (1)

Publication Number Publication Date
DE69941287D1 true DE69941287D1 (de) 2009-10-01

Family

ID=11718622

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69941287T Expired - Lifetime DE69941287D1 (de) 1998-01-21 1999-01-21 Verfahren und apparat für arithmetische operationen

Country Status (6)

Country Link
US (1) US6609143B1 (de)
EP (1) EP1049025B1 (de)
JP (1) JP3667635B2 (de)
CN (1) CN1109990C (de)
DE (1) DE69941287D1 (de)
WO (1) WO1999038088A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587582B1 (en) * 1998-12-03 2009-09-08 Sun Microsystems, Inc. Method and apparatus for parallel arithmetic operations
JP3338043B2 (ja) * 2000-11-02 2002-10-28 株式会社ソニー・コンピュータエンタテインメント 並列演算装置、エンタテインメント装置、演算処理方法、コンピュータプログラム、半導体デバイス
US7107305B2 (en) * 2001-10-05 2006-09-12 Intel Corporation Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
EP1866741B1 (de) * 2005-03-31 2009-07-15 Nxp B.V. Kanonisch gezeichneter digitaler multiplikator
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8645451B2 (en) * 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9122517B2 (en) 2012-06-11 2015-09-01 International Business Machines Corporation Fused multiply-adder with booth-encoding
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
CN106528046B (zh) * 2016-11-02 2019-06-07 上海集成电路研发中心有限公司 长位宽时序累加乘法器
JP7129857B2 (ja) * 2018-09-07 2022-09-02 ルネサスエレクトロニクス株式会社 積和演算装置、積和演算方法、及びシステム
CN114138233B (zh) * 2021-11-18 2025-03-21 中国科学院自动化研究所 串行移位补码乘加器
CN113805840B (zh) * 2021-11-18 2022-05-03 南京风兴科技有限公司 快速累加器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636155A (en) 1993-04-27 1997-06-03 Matsushita Electric Industrial Co., Ltd. Arithmetic processor and arithmetic method
JPH0744533A (ja) * 1993-07-27 1995-02-14 Kawasaki Steel Corp 演算装置
FR2718866B1 (fr) * 1994-04-19 1996-05-15 Sgs Thomson Microelectronics Dispositif de calcul arithmétique et logique et procédé de commande.
JP3579087B2 (ja) * 1994-07-08 2004-10-20 株式会社日立製作所 演算器およびマイクロプロセッサ
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
CN1107905C (zh) * 1995-08-31 2003-05-07 英特尔公司 在分组数据上执行乘－加运算的装置
US5751622A (en) 1995-10-10 1998-05-12 Chromatic Research, Inc. Structure and method for signed multiplication using large multiplier having two embedded signed multipliers
US5784306A (en) * 1996-06-28 1998-07-21 Cirrus Logic, Inc. Parallel multiply accumulate array circuit
JP3092534B2 (ja) * 1996-12-13 2000-09-25 日本電気株式会社 ブロックｉｉｒプロセッサ
US5941940A (en) * 1997-06-30 1999-08-24 Lucent Technologies Inc. Digital signal processor architecture optimized for performing fast Fourier Transforms
US6078939A (en) * 1997-09-30 2000-06-20 Intel Corporation Apparatus useful in floating point arithmetic
US6085213A (en) * 1997-10-23 2000-07-04 Advanced Micro Devices, Inc. Method and apparatus for simultaneously multiplying two or more independent pairs of operands and summing the products
DE69927075T2 (de) * 1998-02-04 2006-06-14 Texas Instruments Inc Rekonfigurierbarer Koprozessor mit mehreren Multiplizier-Akkumulier-Einheiten

Also Published As

Publication number Publication date
CN1109990C (zh) 2003-05-28
EP1049025A1 (de) 2000-11-02
EP1049025A4 (de) 2005-03-30
EP1049025B1 (de) 2009-08-19
US6609143B1 (en) 2003-08-19
JP3667635B2 (ja) 2005-07-06
WO1999038088A1 (fr) 1999-07-29
CN1288545A (zh) 2001-03-21

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