DE69935559D1 - Bussignalleitungstreiber - Google Patents
BussignalleitungstreiberInfo
- Publication number
- DE69935559D1 DE69935559D1 DE69935559T DE69935559T DE69935559D1 DE 69935559 D1 DE69935559 D1 DE 69935559D1 DE 69935559 T DE69935559 T DE 69935559T DE 69935559 T DE69935559 T DE 69935559T DE 69935559 D1 DE69935559 D1 DE 69935559D1
- Authority
- DE
- Germany
- Prior art keywords
- bussignalleitungstreiber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
- G06F13/4077—Precharging or discharging
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26088498A JP4198792B2 (ja) | 1998-08-31 | 1998-08-31 | 信号線駆動回路 |
JP26088498 | 1998-08-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69935559D1 true DE69935559D1 (de) | 2007-05-03 |
DE69935559T2 DE69935559T2 (de) | 2007-12-06 |
Family
ID=17354098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69935559T Expired - Lifetime DE69935559T2 (de) | 1998-08-31 | 1999-08-26 | Bussignalleitungstreiber |
Country Status (4)
Country | Link |
---|---|
US (1) | US6300799B1 (de) |
EP (1) | EP0984360B1 (de) |
JP (1) | JP4198792B2 (de) |
DE (1) | DE69935559T2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1334593A2 (de) | 2000-11-13 | 2003-08-13 | Primarion, Inc. | VORVERZERRUNG FüR DATENVERMITTLUNG |
US7026847B2 (en) * | 2003-12-31 | 2006-04-11 | Altera Corporation | Programmable current booster for faster edge-rate output in high speed applications |
US20060244478A1 (en) * | 2005-04-29 | 2006-11-02 | Kent Smith | Systems and methods for reducing signal ringing |
KR100881195B1 (ko) * | 2007-05-22 | 2009-02-05 | 삼성전자주식회사 | 고주파 성능을 개선한 odt 회로 |
JP5776418B2 (ja) * | 2011-07-29 | 2015-09-09 | 富士通セミコンダクター株式会社 | 半導体記憶装置及び半導体記憶装置の制御方法 |
US9065544B2 (en) * | 2012-09-28 | 2015-06-23 | Osram Sylvania Inc. | Pulse-based binary communication |
CN112953496B (zh) * | 2021-02-04 | 2022-04-22 | 电子科技大学 | 一种高速动态比较器 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2560410B1 (fr) * | 1984-02-24 | 1986-06-06 | Efcis | Circuit de precharge de bus de transfert de donnees logiques |
US5134316A (en) * | 1990-12-12 | 1992-07-28 | Vlsi Technology, Inc. | Precharged buffer with reduced output voltage swing |
US5214320A (en) * | 1992-06-12 | 1993-05-25 | Smos Systems, Inc. | System and method for reducing ground bounce in integrated circuit output buffers |
KR960006911B1 (ko) * | 1992-12-31 | 1996-05-25 | 현대전자산업주식회사 | 데이타 출력버퍼 |
US5453705A (en) * | 1993-12-21 | 1995-09-26 | International Business Machines Corporation | Reduced power VLSI chip and driver circuit |
KR0146169B1 (ko) * | 1995-06-30 | 1998-12-01 | 김주용 | 포스트 차지 로직에 의한 펄스 전달 장치 |
US5760620A (en) * | 1996-04-22 | 1998-06-02 | Quantum Effect Design, Inc. | CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks |
KR0179930B1 (ko) * | 1996-07-12 | 1999-04-01 | 문정환 | 출력 버퍼 제어 회로 |
US6054874A (en) * | 1997-07-02 | 2000-04-25 | Cypress Semiconductor Corp. | Output driver circuit with switched current source |
US6130556A (en) * | 1998-06-16 | 2000-10-10 | Lsi Logic Corporation | Integrated circuit I/O buffer with 5V well and passive gate voltage |
-
1998
- 1998-08-31 JP JP26088498A patent/JP4198792B2/ja not_active Expired - Fee Related
-
1999
- 1999-08-26 EP EP99202783A patent/EP0984360B1/de not_active Expired - Lifetime
- 1999-08-26 DE DE69935559T patent/DE69935559T2/de not_active Expired - Lifetime
- 1999-08-30 US US09/385,344 patent/US6300799B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0984360B1 (de) | 2007-03-21 |
JP2000076868A (ja) | 2000-03-14 |
EP0984360A2 (de) | 2000-03-08 |
EP0984360A3 (de) | 2004-03-17 |
JP4198792B2 (ja) | 2008-12-17 |
US6300799B1 (en) | 2001-10-09 |
DE69935559T2 (de) | 2007-12-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |