DE69932252D1 - Geteilter rechner - Google Patents

Geteilter rechner

Info

Publication number: DE69932252D1
Authority: DE; Germany
Prior art keywords: input; module; output; interface; external
Prior art date: 1998-10-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69932252T

Other languages

English (en)

Other versions

DE69932252T2 (de

Inventor

G Shatas

R Asprey

L Thomas

Greg O'bryant

Greg Luterman

E Choun

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Avocent Huntsville LLC

Original Assignee

Avocent Huntsville LLC

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1998-10-30

Filing date

1999-10-29

Publication date

2006-08-17

1999-10-29 Application filed by Avocent Huntsville LLC filed Critical Avocent Huntsville LLC

2006-08-17 Application granted granted Critical

2006-08-17 Publication of DE69932252D1 publication Critical patent/DE69932252D1/de

2007-06-06 Publication of DE69932252T2 publication Critical patent/DE69932252T2/de

2019-10-30 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/329—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]

Landscapes

Engineering & Computer Science (AREA)
General Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
General Physics & Mathematics (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Signal Processing (AREA)
Computer Networks & Wireless Communication (AREA)
Saccharide Compounds (AREA)
Small-Scale Networks (AREA)
Bus Control (AREA)
Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
Computer And Data Communications (AREA)
Debugging And Monitoring (AREA)

DE69932252T 1998-10-30 1999-10-29 Geteilter rechner Expired - Lifetime DE69932252T2 (de)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
US10625598P	1998-10-30	1998-10-30
US106255P		1998-10-30
PCT/US1999/025291 WO2000026797A1 (en)	1998-10-30	1999-10-29	Split computer

Publications (2)

Publication Number	Publication Date
DE69932252D1 true DE69932252D1 (de)	2006-08-17
DE69932252T2 DE69932252T2 (de)	2007-06-06

Family

ID=22310393

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69932252T Expired - Lifetime DE69932252T2 (de)	1998-10-30	1999-10-29	Geteilter rechner

Country Status (7)

Country	Link
EP (2)	EP1125210B1 (de)
AT (1)	ATE332531T1 (de)
AU (2)	AU1708800A (de)
DE (1)	DE69932252T2 (de)
ES (1)	ES2267303T3 (de)
HK (2)	HK1041530B (de)
WO (2)	WO2000026796A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20030041129A1 (en) *	2000-07-20	2003-02-27	John Applcby-Allis	Voice-over-internet protocol telephone in reconfigurable logic
AU2001270874A1 (en) *	2000-07-20	2002-02-05	Celoxica Limited	System, method and article of manufacture for controlling the use of resources
CN102929756A (zh) *	2012-10-28	2013-02-13	中国电子科技集团公司第十研究所	通用型高速并、串行总线开发验证平台

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4384327A (en) *	1978-10-31	1983-05-17	Honeywell Information Systems Inc.	Intersystem cycle control logic
ZA883232B (en) *	1987-05-06	1989-07-26	Dowd Research Pty Ltd O	Packet switches,switching methods,protocols and networks
US4959833A (en) *	1989-03-08	1990-09-25	Ics Electronics Corporation	Data transmission method and bus extender
JPH034351A (ja) *	1989-04-26	1991-01-10	Dubner Computer Syst Inc	システム・バス・データ・リンク装置
US5430848A (en) *	1992-08-14	1995-07-04	Loral Fairchild Corporation	Distributed arbitration with programmable priorities
US5812534A (en) *	1993-01-08	1998-09-22	Multi-Tech Systems, Inc.	Voice over data conferencing for a computer-based personal communications system
US5664223A (en) *	1994-04-05	1997-09-02	International Business Machines Corporation	System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5659707A (en) *	1994-10-07	1997-08-19	Industrial Technology Research Institute	Transfer labeling mechanism for multiple outstanding read requests on a split transaction bus
US5799207A (en) *	1995-03-28	1998-08-25	Industrial Technology Research Institute	Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device
US5586121A (en) *	1995-04-21	1996-12-17	Hybrid Networks, Inc.	Asymmetric hybrid access system and method
RU2176814C2 (ru) *	1995-06-07	2001-12-10	Самсунг Электроникс Ко., Лтд.	Схема уменьшения задержки при передаче буферизованных данных между двумя взаимно асинхронными шинами
US5781747A (en) *	1995-11-14	1998-07-14	Mesa Ridge Technologies, Inc.	Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location
US5764479A (en) *	1996-09-23	1998-06-09	International Business Machines Corporation	Split system personal computer having floppy disk drive moveable between accessible and inaccessible positions
EP0844567A1 (de) *	1996-11-21	1998-05-27	Hewlett-Packard Company	PCI-Busbrücke für Fernübertragung

1999
- 1999-10-29 WO PCT/US1999/025290 patent/WO2000026796A1/en not_active Application Discontinuation
- 1999-10-29 DE DE69932252T patent/DE69932252T2/de not_active Expired - Lifetime
- 1999-10-29 AT AT99957481T patent/ATE332531T1/de not_active IP Right Cessation
- 1999-10-29 EP EP99957481A patent/EP1125210B1/de not_active Expired - Lifetime
- 1999-10-29 AU AU17088/00A patent/AU1708800A/en not_active Abandoned
- 1999-10-29 EP EP99960160A patent/EP1133732A4/de not_active Ceased
- 1999-10-29 WO PCT/US1999/025291 patent/WO2000026797A1/en active IP Right Grant
- 1999-10-29 ES ES99957481T patent/ES2267303T3/es not_active Expired - Lifetime
- 1999-10-29 AU AU15178/00A patent/AU1517800A/en not_active Abandoned
2002
- 2002-02-21 HK HK02101293.0A patent/HK1041530B/zh not_active IP Right Cessation
- 2002-03-18 HK HK02102076.1A patent/HK1043409A1/zh unknown

Also Published As

Publication number	Publication date
WO2000026797A9 (en)	2000-10-19
WO2000026797A1 (en)	2000-05-11
DE69932252T2 (de)	2007-06-06
EP1133732A4 (de)	2003-01-22
HK1041530B (zh)	2007-01-19
WO2000026796A9 (en)	2000-11-30
HK1041530A1 (en)	2002-07-12
EP1125210A1 (de)	2001-08-22
AU1708800A (en)	2000-05-22
ATE332531T1 (de)	2006-07-15
EP1133732A1 (de)	2001-09-19
AU1517800A (en)	2000-05-22
HK1043409A1 (zh)	2002-09-13
EP1125210B1 (de)	2006-07-05
EP1125210A4 (de)	2002-08-07
ES2267303T3 (es)	2007-03-01
WO2000026796A1 (en)	2000-05-11

Publication	Publication Date	Title
AU2002217916A1 (en)	2002-07-16	Computer peripheral device that remains operable when central processor operations are suspended
TW327684B (en)	1998-03-01	A method and apparatus for interfacing a device compliant to a first bus protocol to an external bus having a second bus protocol and for providing virtual functions through a multi-function intelligent bridge
WO2003090052A3 (en)	2004-08-12	A computer system including a secure execution mode - capable cpu and a security services processor connected via a secure communication path
EP1030241A4 (de)	2001-11-07	Display
GB2348352B (en)	2002-07-31	Force feedback system including multi-tasking graphical host environment and interface device
ATE475930T1 (de)	2010-08-15	Verzweigungsbefehl für einen mehrfachverarbeitungsprozessor
DE69020569D1 (de)	1995-08-03	Modulares ein-/ausgabesystem für superrechner.
ATE218227T1 (de)	2002-06-15	Eingabevorrichtung für ein rechnersystem
ATE237835T1 (de)	2003-05-15	Leistungssteuerung in einem computersystem
NO20025921D0 (no)	2002-12-10	Fordelermodul for bruk i telekommunikasjons- og datasystemteknologi
WO1999038086A3 (en)	1999-11-18	Bus bridge architecture for a data processing system
TW200634620A (en)	2006-10-01	Mechanism to determine trust of out-of-band management agents
ATE468562T1 (de)	2010-06-15	Virtualisierung von e/a-adapterressourcen
AU2003222411A1 (en)	2003-12-12	Access to a wide memory
DE69932252D1 (de)	2006-08-17	Geteilter rechner
MY114652A (en)	2002-12-31	Personal computer with local bus arbitration.
DE69729664D1 (de)	2004-07-29	System zur Versorgung von Rechnerperipheriegeräten
SE9801674D0 (sv)	1998-05-13	Application specific integrated circuit and transceiver circuit
ATE205316T1 (de)	2001-09-15	Vorrichtung zum hierarchischen verbinden einer mehrzahl von funktionseinheiten in einem prozessor
AU3710601A (en)	2001-09-12	Computer node architecture comprising a dedicated middleware processor
SE9900887L (sv)	2000-09-13	Krypteringsanordning
WO2001046761A3 (en)	2008-02-14	Fabrication process control system emulator
Chen et al.	2000	Transformation methods for communication optimization on CC-NUMA parallel system
RU95103257A (ru)	1996-12-10	Преобразователь код-частота
TW374126B (en)	1999-11-11	An integrated circuit device employed for monitoring computer working environment

Legal Events

Date	Code	Title	Description
2007-07-26	8364	No opposition during term of opposition