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DE69841667D1 - Halbleiteranordnungen mit MOS-Gatter - Google Patents

Halbleiteranordnungen mit MOS-Gatter

Info

Publication number
DE69841667D1
DE69841667D1 DE69841667T DE69841667T DE69841667D1 DE 69841667 D1 DE69841667 D1 DE 69841667D1 DE 69841667 T DE69841667 T DE 69841667T DE 69841667 T DE69841667 T DE 69841667T DE 69841667 D1 DE69841667 D1 DE 69841667D1
Authority
DE
Germany
Prior art keywords
mos
gate
semiconductor arrangements
arrangements
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841667T
Other languages
English (en)
Inventor
John Manning Neilson
Richard Douglas Stokes
Christopher Boguslaw Kocon
Linda Susan Brush
John Lawrence Benjamin
Louis Ellen Skurkey
Christopher Lawrence Rexer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of DE69841667D1 publication Critical patent/DE69841667D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
DE69841667T 1997-03-11 1998-03-10 Halbleiteranordnungen mit MOS-Gatter Expired - Lifetime DE69841667D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/814,842 US5877044A (en) 1997-03-11 1997-03-11 Method of making MOS-gated semiconductor devices

Publications (1)

Publication Number Publication Date
DE69841667D1 true DE69841667D1 (de) 2010-07-01

Family

ID=25216137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841667T Expired - Lifetime DE69841667D1 (de) 1997-03-11 1998-03-10 Halbleiteranordnungen mit MOS-Gatter

Country Status (7)

Country Link
US (1) US5877044A (de)
EP (1) EP0865080B1 (de)
JP (1) JP3971838B2 (de)
KR (1) KR100505271B1 (de)
CN (1) CN1146970C (de)
DE (1) DE69841667D1 (de)
TW (1) TW385496B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080029830A1 (en) * 2006-08-01 2008-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Forming reverse-extension MOS in standard CMOS flow
JP2008140939A (ja) * 2006-11-30 2008-06-19 Toshiba Corp 半導体装置およびその製造方法
US8178930B2 (en) * 2007-03-06 2012-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure to improve MOS transistor on-breakdown voltage
US9040384B2 (en) * 2012-10-19 2015-05-26 Freescale Semiconductor, Inc. High voltage diode
CN103219238B (zh) * 2013-04-27 2016-09-21 中国东方电气集团有限公司 一种全自对准的绝缘栅双极晶体管器件及其制造方法
CN103390641B (zh) * 2013-04-27 2016-02-03 中国东方电气集团有限公司 一种绝缘栅双极型晶体管及其自对准制作方法
CN103219237B (zh) * 2013-04-27 2015-10-28 中国东方电气集团有限公司 一种自对准绝缘栅双极型晶体管的制作方法
CN111933700B (zh) * 2020-09-29 2021-06-11 中芯集成电路制造(绍兴)有限公司 功率半导体器件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0227894A3 (de) * 1985-12-19 1988-07-13 SILICONIX Incorporated Vertikaler DMOS-Transistor von hoher Packungsdichte
JPS62232167A (ja) * 1986-04-02 1987-10-12 Nissan Motor Co Ltd 半導体装置
JPS6419772A (en) * 1987-07-15 1989-01-23 Nec Corp Manufacture of vertical mosfet
JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
JPH01238172A (ja) * 1988-03-18 1989-09-22 Fuji Electric Co Ltd Mos型半導体素子の製造方法
US5182222A (en) * 1991-06-26 1993-01-26 Texas Instruments Incorporated Process for manufacturing a DMOS transistor
US5171705A (en) * 1991-11-22 1992-12-15 Supertex, Inc. Self-aligned structure and process for DMOS transistor
IT1252625B (it) * 1991-12-05 1995-06-19 Cons Ric Microelettronica Processo di fabbricazione di transistors a effetto di campo con gate isolato (igfet) a bassa densita' di corto circuiti tra gate e source e dispositivi con esso ottenuti
DE69432407D1 (de) * 1994-05-19 2003-05-08 Cons Ric Microelettronica Integrierte Leistungsschaltung ("PIC") mit vertikalem IGB und Verfahren zur Herstellung derselben
US5474946A (en) * 1995-02-17 1995-12-12 International Rectifier Corporation Reduced mask process for manufacture of MOS gated devices

Also Published As

Publication number Publication date
EP0865080A3 (de) 1998-10-28
CN1198003A (zh) 1998-11-04
CN1146970C (zh) 2004-04-21
KR100505271B1 (ko) 2005-12-02
US5877044A (en) 1999-03-02
EP0865080B1 (de) 2010-05-19
EP0865080A2 (de) 1998-09-16
JPH10270680A (ja) 1998-10-09
TW385496B (en) 2000-03-21
KR19980080128A (ko) 1998-11-25
JP3971838B2 (ja) 2007-09-05

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FAIRCHILD SEMICONDUCTOR CORP., SOUTH PORTLAND,, US

8364 No opposition during term of opposition