DE69835807D1 - Verfahren und vorrichtung zur taktsignalverteilung an mehreren busknoten in einer busbrücke - Google Patents
Verfahren und vorrichtung zur taktsignalverteilung an mehreren busknoten in einer busbrückeInfo
- Publication number
- DE69835807D1 DE69835807D1 DE69835807T DE69835807T DE69835807D1 DE 69835807 D1 DE69835807 D1 DE 69835807D1 DE 69835807 T DE69835807 T DE 69835807T DE 69835807 T DE69835807 T DE 69835807T DE 69835807 D1 DE69835807 D1 DE 69835807D1
- Authority
- DE
- Germany
- Prior art keywords
- bus
- signal distribution
- clocking signal
- several
- nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40058—Isochronous transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40091—Bus bridging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Small-Scale Networks (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US672 | 1993-01-05 | ||
US09/000,672 US6032261A (en) | 1997-12-30 | 1997-12-30 | Bus bridge with distribution of a common cycle clock to all bridge portals to provide synchronization of local buses, and method of operation thereof |
PCT/IB1998/001577 WO1999035587A1 (en) | 1997-12-30 | 1998-10-08 | Method and apparatus for distributing a cycle clock to a plurality of bus nodes in a bus bridge |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69835807D1 true DE69835807D1 (de) | 2006-10-19 |
DE69835807T2 DE69835807T2 (de) | 2007-04-12 |
Family
ID=21692544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69835807T Expired - Fee Related DE69835807T2 (de) | 1997-12-30 | 1998-10-08 | Verfahren und vorrichtung zur taktsignalverteilung an mehreren busknoten in einer busbrücke |
Country Status (8)
Country | Link |
---|---|
US (1) | US6032261A (de) |
EP (1) | EP0961977B1 (de) |
JP (1) | JP2001515682A (de) |
KR (1) | KR100646122B1 (de) |
CN (1) | CN1143221C (de) |
DE (1) | DE69835807T2 (de) |
TW (1) | TW417050B (de) |
WO (1) | WO1999035587A1 (de) |
Families Citing this family (83)
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JPH10254827A (ja) * | 1997-03-06 | 1998-09-25 | Canon Inc | 拡張カードおよび拡張カードのアクセス制御方法およびコンピュータが読み出し可能なプログラムを格納した記憶媒体 |
JP3397124B2 (ja) * | 1998-03-12 | 2003-04-14 | ソニー株式会社 | 同期方法及びブリッジ |
US6252886B1 (en) * | 1998-07-06 | 2001-06-26 | Sony Corporation | Bandwidth reservation |
JP3815063B2 (ja) * | 1998-07-14 | 2006-08-30 | ソニー株式会社 | バスネットワークの同期通信設定の解除方法およびそれを利用するバスネットワーク、並びに情報提供媒体 |
JP2000032030A (ja) * | 1998-07-14 | 2000-01-28 | Sony Corp | バスネットワークの同期通信設定方法およびそれを利用するバスネットワーク、並びに情報提供媒体 |
EP0986248A1 (de) * | 1998-09-07 | 2000-03-15 | Deutsche Thomson-Brandt Gmbh | Verfahren und Vorrichtung zur Zeitmarkierung eines aufzuzeichnenden Bitstroms |
JP2000124914A (ja) * | 1998-10-19 | 2000-04-28 | Sony Corp | 情報処理装置および方法、並びに提供媒体 |
US6418494B1 (en) * | 1998-10-30 | 2002-07-09 | Cybex Computer Products Corporation | Split computer architecture to separate user and processor while retaining original user interface |
JP3175826B2 (ja) * | 1998-11-24 | 2001-06-11 | 日本電気株式会社 | ネットワーク構成方法およびネットワーク管理ノード |
US6510150B1 (en) * | 1998-12-21 | 2003-01-21 | Koninklijke Philips Electronics N.V. | Method of MAC synchronization in TDMA-based wireless networks |
JP2000216800A (ja) * | 1999-01-27 | 2000-08-04 | Sony Corp | デ―タ中継装置および方法、並びに提供媒体 |
US6598084B1 (en) * | 1999-02-16 | 2003-07-22 | Sony Corporation | Methods and apparatus for processing, transmitting, and receiving data from a modular electronic medical device |
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US6389547B1 (en) * | 1999-03-19 | 2002-05-14 | Sony Corporation | Method and apparatus to synchronize a bus bridge to a master clock |
JP3353824B2 (ja) | 1999-04-22 | 2002-12-03 | 日本電気株式会社 | ネットワーク同期システム及びネットワーク同期方法 |
US6445711B1 (en) | 1999-04-23 | 2002-09-03 | Sony Corporation | Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE STD 1394 serial buses |
US6366805B1 (en) * | 1999-05-26 | 2002-04-02 | Viasys Healthcare Inc. | Time frame synchronization of medical monitoring signals |
US6628607B1 (en) | 1999-07-09 | 2003-09-30 | Apple Computer, Inc. | Method and apparatus for loop breaking on a serial bus |
US6633943B1 (en) * | 1999-09-21 | 2003-10-14 | Sony Corporation | Method and system for the simplification of leaf-limited bridges |
JP2003524947A (ja) * | 1999-09-23 | 2003-08-19 | デジタル ハーモニー テクノロジーズ インコーポレイテッド | 分散同期信号のための方法および装置 |
JP3424620B2 (ja) * | 1999-09-24 | 2003-07-07 | 日本電気株式会社 | アイソクロナスパケット転送方法,該転送用制御プログラムの記録媒体,ブリッジ及びパケット転送制御lsi |
JP3843667B2 (ja) * | 1999-10-15 | 2006-11-08 | セイコーエプソン株式会社 | データ転送制御装置及び電子機器 |
US6691096B1 (en) | 1999-10-28 | 2004-02-10 | Apple Computer, Inc. | General purpose data container method and apparatus for implementing AV/C descriptors |
US6671768B1 (en) | 1999-11-01 | 2003-12-30 | Apple Computer, Inc. | System and method for providing dynamic configuration ROM using double image buffers for use with serial bus devices |
US6618750B1 (en) | 1999-11-02 | 2003-09-09 | Apple Computer, Inc. | Method and apparatus for determining communication paths |
US6813663B1 (en) | 1999-11-02 | 2004-11-02 | Apple Computer, Inc. | Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images |
US6636914B1 (en) | 1999-11-05 | 2003-10-21 | Apple Computer, Inc. | Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases |
US6587904B1 (en) | 1999-11-05 | 2003-07-01 | Apple Computer, Inc. | Method and apparatus for preventing loops in a full-duplex bus |
US6457086B1 (en) * | 1999-11-16 | 2002-09-24 | Apple Computers, Inc. | Method and apparatus for accelerating detection of serial bus device speed signals |
US6751697B1 (en) * | 1999-11-29 | 2004-06-15 | Sony Corporation | Method and system for a multi-phase net refresh on a bus bridge interconnect |
GB9930849D0 (en) * | 1999-12-24 | 2000-02-16 | Koninkl Philips Electronics Nv | Data communications |
JP3454217B2 (ja) * | 1999-12-28 | 2003-10-06 | 日本電気株式会社 | 通信経路制御方法、機器制御装置、及びブリッジ |
EP1113626B1 (de) * | 1999-12-30 | 2009-04-22 | Sony Deutschland GmbH | Schnittstellenverbindungsschicht- Einrichtung zum Aufbau eines verteilten Netzwerks |
US7266617B1 (en) | 2000-01-18 | 2007-09-04 | Apple Inc. | Method and apparatus for border node behavior on a full-duplex bus |
US6639918B1 (en) * | 2000-01-18 | 2003-10-28 | Apple Computer, Inc. | Method and apparatus for border node behavior on a full-duplex bus |
JP2001230821A (ja) * | 2000-02-16 | 2001-08-24 | Sony Corp | データ中継装置および方法、並びに提供媒体 |
US7050453B1 (en) | 2000-02-17 | 2006-05-23 | Apple Computer, Inc. | Method and apparatus for ensuring compatibility on a high performance serial bus |
US6772267B2 (en) * | 2000-02-18 | 2004-08-03 | Bridgeco Ag | Multi-portal bridge for providing network connectivity |
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US6618785B1 (en) | 2000-04-21 | 2003-09-09 | Apple Computer, Inc. | Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus |
US6718497B1 (en) | 2000-04-21 | 2004-04-06 | Apple Computer, Inc. | Method and apparatus for generating jitter test patterns on a high performance serial bus |
JP2001313646A (ja) * | 2000-04-27 | 2001-11-09 | Sony Corp | 電子機器およびその物理層回路のステート制御方法 |
WO2001086886A2 (en) * | 2000-05-11 | 2001-11-15 | Firemedia Communications (Israel) Ltd. | Three-dimensional switch providing packet routing between multiple multimedia buses |
AU2001260560A1 (en) * | 2000-05-18 | 2001-11-26 | Firemedia Communications (Israel) Ltd. | Bandwidth and path allocation method for a switched fabric connecting multiple multimedia buses |
US6822946B1 (en) * | 2000-08-24 | 2004-11-23 | Motorola, Inc | Wireless bridge for a broadband network |
EP1198085B1 (de) | 2000-10-10 | 2011-06-08 | Sony Deutschland GmbH | Zyklussynchronisierung zwischen miteinander verbundenen Teilnetzwerken |
DE60131765T2 (de) | 2000-10-19 | 2008-11-20 | Thomson Licensing | Verfahren zur verbindung mehrerer kommunikationsbusse mit drahtlosen verbindungen |
EP1199840A1 (de) * | 2000-10-19 | 2002-04-24 | THOMSON multimedia | Verfahren zum drahtlosen Anschluss einer entfernten IEEE1394-Vorrichtung zu einer Gruppe von IEEE1394-Vorrichtungen |
EP1199839A1 (de) * | 2000-10-19 | 2002-04-24 | THOMSON multimedia | Kommunikationsverfahren zwischen Brücke-bewussten Knoten über Hiperlan 2 Brücken |
JP4097891B2 (ja) * | 2000-11-27 | 2008-06-11 | 三菱電機株式会社 | Ieee1394を用いた同期システム |
WO2002075562A1 (de) * | 2001-03-15 | 2002-09-26 | Robert Bosch Gmbh | Verfahren und vorrichtung zur synchronisation der globalen zeit von mehreren ttcan-bussen sowie entsprechendes bussystem |
US6975653B2 (en) * | 2001-06-12 | 2005-12-13 | Agilent Technologies, Inc. | Synchronizing clocks across sub-nets |
US7269137B2 (en) * | 2001-08-24 | 2007-09-11 | Canon Kabushiki Kaisha | Method for setting up an isochronous data stream connection, with the application of a predetermined, total isochronous delay on one or more routing paths |
US6880025B2 (en) * | 2001-12-27 | 2005-04-12 | Koninklijke Philips Electronics N.V. | Efficient timeout message management in IEEE 1394 bridged serial bus network |
US6898658B2 (en) * | 2001-12-27 | 2005-05-24 | Koninklijke Philips Electronics N.V. | Method to prevent net update oscillation |
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KR100597436B1 (ko) * | 2004-12-15 | 2006-07-10 | 한국전자통신연구원 | 무선 1394 시스템의 사이클 타임 동기화 장치 및 그 방법 |
US20080214153A1 (en) * | 2005-09-14 | 2008-09-04 | Jorey Ramer | Mobile User Profile Creation based on User Browse Behaviors |
KR100652013B1 (ko) * | 2005-11-17 | 2006-12-01 | 한국전자통신연구원 | 무선 ieee1394 프로토콜을 사용하는 이종 네트워크환경에서의 시간 동기화 방법 |
US7783820B2 (en) * | 2005-12-30 | 2010-08-24 | Avocent Corporation | Packet-switched split computer having disassociated peripheral controller and plural data buses |
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WO2007127452A2 (en) * | 2006-04-28 | 2007-11-08 | Avocent Corporation | Dvc delta commands |
JP2019175309A (ja) * | 2018-03-29 | 2019-10-10 | セイコーエプソン株式会社 | 回路装置、電子機器及びケーブルハーネス |
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US5799207A (en) * | 1995-03-28 | 1998-08-25 | Industrial Technology Research Institute | Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device |
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JP3719789B2 (ja) * | 1996-10-04 | 2005-11-24 | 株式会社東芝 | 通信端末装置及び中継装置 |
JPH10178438A (ja) * | 1996-12-18 | 1998-06-30 | Sony Corp | データ通信システム、データ通信装置および方法 |
US5940608A (en) * | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5831805A (en) * | 1997-02-13 | 1998-11-03 | Sony Corporation | Local power failure detection and clock disabling circuit |
US5909559A (en) * | 1997-04-04 | 1999-06-01 | Texas Instruments Incorporated | Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width |
-
1997
- 1997-12-30 US US09/000,672 patent/US6032261A/en not_active Expired - Fee Related
-
1998
- 1998-10-08 KR KR1019997007890A patent/KR100646122B1/ko not_active Expired - Fee Related
- 1998-10-08 JP JP53585899A patent/JP2001515682A/ja not_active Ceased
- 1998-10-08 CN CNB988046520A patent/CN1143221C/zh not_active Expired - Fee Related
- 1998-10-08 DE DE69835807T patent/DE69835807T2/de not_active Expired - Fee Related
- 1998-10-08 EP EP98945471A patent/EP0961977B1/de not_active Expired - Lifetime
- 1998-10-08 WO PCT/IB1998/001577 patent/WO1999035587A1/en active IP Right Grant
- 1998-11-06 TW TW087118508A patent/TW417050B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6032261A (en) | 2000-02-29 |
CN1254426A (zh) | 2000-05-24 |
DE69835807T2 (de) | 2007-04-12 |
KR20000075817A (ko) | 2000-12-26 |
WO1999035587A1 (en) | 1999-07-15 |
TW417050B (en) | 2001-01-01 |
KR100646122B1 (ko) | 2006-11-17 |
CN1143221C (zh) | 2004-03-24 |
EP0961977B1 (de) | 2006-09-06 |
JP2001515682A (ja) | 2001-09-18 |
EP0961977A1 (de) | 1999-12-08 |
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