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DE69724192D1 - Verfahren zum Ätzen von Polyzidstrukturen - Google Patents

Verfahren zum Ätzen von Polyzidstrukturen

Info

Publication number
DE69724192D1
DE69724192D1 DE69724192T DE69724192T DE69724192D1 DE 69724192 D1 DE69724192 D1 DE 69724192D1 DE 69724192 T DE69724192 T DE 69724192T DE 69724192 T DE69724192 T DE 69724192T DE 69724192 D1 DE69724192 D1 DE 69724192D1
Authority
DE
Germany
Prior art keywords
polycide structures
etching
etching polycide
structures
polycide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69724192T
Other languages
English (en)
Other versions
DE69724192T2 (de
Inventor
Shaoher Pan
Songlin Xu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of DE69724192D1 publication Critical patent/DE69724192D1/de
Application granted granted Critical
Publication of DE69724192T2 publication Critical patent/DE69724192T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32091Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/321Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • H01J2237/3343Problems associated with etching
    • H01J2237/3345Problems associated with etching anisotropy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • H01J2237/3343Problems associated with etching
    • H01J2237/3346Selectivity

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Analytical Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69724192T 1996-06-17 1997-06-17 Verfahren zum Ätzen von Polyzidstrukturen Expired - Fee Related DE69724192T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US665657 1996-06-17
US08/665,657 US6008139A (en) 1996-06-17 1996-06-17 Method of etching polycide structures

Publications (2)

Publication Number Publication Date
DE69724192D1 true DE69724192D1 (de) 2003-09-25
DE69724192T2 DE69724192T2 (de) 2004-06-17

Family

ID=24671017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724192T Expired - Fee Related DE69724192T2 (de) 1996-06-17 1997-06-17 Verfahren zum Ätzen von Polyzidstrukturen

Country Status (6)

Country Link
US (1) US6008139A (de)
EP (1) EP0814500B1 (de)
JP (1) JPH10116823A (de)
KR (1) KR980005800A (de)
DE (1) DE69724192T2 (de)
TW (1) TW345682B (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6231776B1 (en) 1995-12-04 2001-05-15 Daniel L. Flamm Multi-temperature processing
KR100440418B1 (ko) 1995-12-12 2004-10-20 텍사스 인스트루먼츠 인코포레이티드 저압,저온의반도체갭충전처리방법
WO1999067817A1 (en) 1998-06-22 1999-12-29 Applied Materials, Inc. Silicon trench etching using silicon-containing precursors to reduce or avoid mask erosion
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6306732B1 (en) * 1998-10-09 2001-10-23 Advanced Micro Devices, Inc. Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier
US6255221B1 (en) * 1998-12-17 2001-07-03 Lam Research Corporation Methods for running a high density plasma etcher to achieve reduced transistor device damage
US6299788B1 (en) * 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
US6379574B1 (en) * 1999-05-03 2002-04-30 Applied Materials, Inc. Integrated post-etch treatment for a dielectric etch process
KR100292412B1 (ko) * 1999-07-14 2001-06-01 윤종용 폴리실리콘막에 대한 금속 실리사이드막의 식각선택비를 증가시키는 방법 및 이를 이용한 폴리실리콘막과 금속 실리사이드막의 적층막 식각방법
JP2001035808A (ja) * 1999-07-22 2001-02-09 Semiconductor Energy Lab Co Ltd 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法
US6242362B1 (en) * 1999-08-04 2001-06-05 Taiwan Semiconductor Manufacturing Company Etch process for fabricating a vertical hard mask/conductive pattern profile to improve T-shaped profile for a silicon oxynitride hard mask
US6548414B2 (en) * 1999-09-14 2003-04-15 Infineon Technologies Ag Method of plasma etching thin films of difficult to dry etch materials
US6486069B1 (en) 1999-12-03 2002-11-26 Tegal Corporation Cobalt silicide etch process and apparatus
WO2001050511A1 (en) * 1999-12-30 2001-07-12 Koninklijke Philips Electronics N.V. Semiconductor manufacture using helium-assisted etch
US6300251B1 (en) * 2000-02-10 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon
US6507155B1 (en) 2000-04-06 2003-01-14 Applied Materials Inc. Inductively coupled plasma source with controllable power deposition
KR100390040B1 (ko) * 2001-04-06 2003-07-04 주식회사 하이닉스반도체 반도체소자의 듀얼게이트 제조방법
TW586335B (en) * 2001-10-31 2004-05-01 Applied Materials Inc Plasma etch reactor with dual sources for enhancing both etch selectivity and etch rate
US6590344B2 (en) * 2001-11-20 2003-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Selectively controllable gas feed zones for a plasma reactor
WO2003056617A1 (fr) * 2001-12-27 2003-07-10 Tokyo Electron Limited Procede de gravure et dispositif de gravure au plasma
US7109122B2 (en) * 2002-11-29 2006-09-19 Tokyo Electron Limited Method and apparatus for reducing substrate charging damage
KR100638983B1 (ko) * 2004-12-15 2006-10-26 동부일렉트로닉스 주식회사 금속-절연체-금속 커패시터의 제조 방법
KR100643570B1 (ko) * 2005-06-28 2006-11-10 주식회사 하이닉스반도체 반도체 소자 제조 방법
US7758763B2 (en) * 2006-10-31 2010-07-20 Applied Materials, Inc. Plasma for resist removal and facet control of underlying features
CN103832965B (zh) * 2012-11-23 2017-02-08 北京北方微电子基地设备工艺研究中心有限责任公司 基片刻蚀方法
JP2015079793A (ja) * 2013-10-15 2015-04-23 東京エレクトロン株式会社 プラズマ処理方法
US10643858B2 (en) 2017-10-11 2020-05-05 Samsung Electronics Co., Ltd. Method of etching substrate
CN118969612B (zh) * 2024-10-17 2025-03-25 浙江广芯微电子有限公司 一种沟槽肖特基结构的二极管柔性加工管控方法及平台

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4411734A (en) * 1982-12-09 1983-10-25 Rca Corporation Etching of tantalum silicide/doped polysilicon structures
US4460435A (en) * 1983-12-19 1984-07-17 Rca Corporation Patterning of submicrometer metal silicide structures
US4490209B2 (en) * 1983-12-27 2000-12-19 Texas Instruments Inc Plasma etching using hydrogen bromide addition
US4918031A (en) * 1988-12-28 1990-04-17 American Telephone And Telegraph Company,At&T Bell Laboratories Processes depending on plasma generation using a helical resonator
JP2926864B2 (ja) * 1990-04-12 1999-07-28 ソニー株式会社 銅系金属膜のエッチング方法
JP3004699B2 (ja) * 1990-09-07 2000-01-31 東京エレクトロン株式会社 プラズマ処理方法
US5094712A (en) * 1990-10-09 1992-03-10 Micron Technology, Inc. One chamber in-situ etch process for oxide and conductive material
US5211804A (en) * 1990-10-16 1993-05-18 Oki Electric Industry, Co., Ltd. Method for dry etching
US5167762A (en) * 1991-01-02 1992-12-01 Micron Technology, Inc. Anisotropic etch method
US5431772A (en) * 1991-05-09 1995-07-11 International Business Machines Corporation Selective silicon nitride plasma etching process
JP3210359B2 (ja) * 1991-05-29 2001-09-17 株式会社東芝 ドライエッチング方法
US5192702A (en) * 1991-12-23 1993-03-09 Industrial Technology Research Institute Self-aligned cylindrical stacked capacitor DRAM cell
KR0164618B1 (ko) * 1992-02-13 1999-02-01 이노우에 쥰이치 플라즈마 처리방법
US5256245A (en) * 1992-08-11 1993-10-26 Micron Semiconductor, Inc. Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers
JP3326644B2 (ja) * 1993-11-16 2002-09-24 ソニー株式会社 シリコン系材料層の加工方法
JP2907314B2 (ja) * 1993-12-30 1999-06-21 日本電気株式会社 半導体装置の製造方法
JP3365067B2 (ja) * 1994-02-10 2003-01-08 ソニー株式会社 プラズマ装置およびこれを用いたプラズマ処理方法
US5437765A (en) * 1994-04-29 1995-08-01 Texas Instruments Incorporated Semiconductor processing
DE69506619T2 (de) * 1994-06-02 1999-07-15 Applied Materials, Inc., Santa Clara, Calif. Induktiv gekoppelter Plasmareaktor mit einer Elektrode zur Erleichterung der Plasmazündung
US5783101A (en) * 1994-09-16 1998-07-21 Applied Materials, Inc. High etch rate residue free metal etch process with low frequency high power inductive coupled plasma
US5779926A (en) * 1994-09-16 1998-07-14 Applied Materials, Inc. Plasma process for etching multicomponent alloys
US5607542A (en) * 1994-11-01 1997-03-04 Applied Materials Inc. Inductively enhanced reactive ion etching
US5591301A (en) * 1994-12-22 1997-01-07 Siemens Aktiengesellschaft Plasma etching method
US5880033A (en) * 1996-06-17 1999-03-09 Applied Materials, Inc. Method for etching metal silicide with high selectivity to polysilicon
US5866483A (en) * 1997-04-04 1999-02-02 Applied Materials, Inc. Method for anisotropically etching tungsten using SF6, CHF3, and N2

Also Published As

Publication number Publication date
JPH10116823A (ja) 1998-05-06
TW345682B (en) 1998-11-21
KR980005800A (ko) 1998-03-30
US6008139A (en) 1999-12-28
EP0814500B1 (de) 2003-08-20
DE69724192T2 (de) 2004-06-17
EP0814500A3 (de) 1998-09-09
EP0814500A2 (de) 1997-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee