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DE69718278D1 - Method and system for single-cycle execution of successive iterations of an instruction loop - Google Patents

Method and system for single-cycle execution of successive iterations of an instruction loop

Info

Publication number
DE69718278D1
DE69718278D1 DE69718278T DE69718278T DE69718278D1 DE 69718278 D1 DE69718278 D1 DE 69718278D1 DE 69718278 T DE69718278 T DE 69718278T DE 69718278 T DE69718278 T DE 69718278T DE 69718278 D1 DE69718278 D1 DE 69718278D1
Authority
DE
Germany
Prior art keywords
successive iterations
instruction loop
cycle execution
execution
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69718278T
Other languages
German (de)
Other versions
DE69718278T2 (en
Inventor
Timothy D Anderson
Jonathan H Shiell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69718278D1 publication Critical patent/DE69718278D1/en
Publication of DE69718278T2 publication Critical patent/DE69718278T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69718278T 1996-10-31 1997-10-31 Method and system for single-cycle execution of successive iterations of an instruction loop Expired - Lifetime DE69718278T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2923096P 1996-10-31 1996-10-31

Publications (2)

Publication Number Publication Date
DE69718278D1 true DE69718278D1 (en) 2003-02-13
DE69718278T2 DE69718278T2 (en) 2003-08-21

Family

ID=21847948

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69718278T Expired - Lifetime DE69718278T2 (en) 1996-10-31 1997-10-31 Method and system for single-cycle execution of successive iterations of an instruction loop

Country Status (4)

Country Link
US (1) US5951679A (en)
EP (1) EP0840208B1 (en)
JP (1) JPH10177482A (en)
DE (1) DE69718278T2 (en)

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US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7139901B2 (en) 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7032226B1 (en) * 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7649901B2 (en) 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
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US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7155516B2 (en) 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7058064B2 (en) 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US6567895B2 (en) * 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US6829702B1 (en) * 2000-07-26 2004-12-07 International Business Machines Corporation Branch target cache and method for efficiently obtaining target path instructions for tight program loops
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7020871B2 (en) 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
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US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
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US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
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US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7249248B2 (en) * 2002-11-25 2007-07-24 Intel Corporation Method, apparatus, and system for variable increment multi-index looping operations
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
JP4610218B2 (en) * 2004-03-30 2011-01-12 ルネサスエレクトロニクス株式会社 Information processing device
US7475231B2 (en) * 2005-11-14 2009-01-06 Texas Instruments Incorporated Loop detection and capture in the instruction queue
US20070294519A1 (en) * 2006-06-19 2007-12-20 Miller Laura F Localized Control Caching Resulting In Power Efficient Control Logic
US20080229074A1 (en) * 2006-06-19 2008-09-18 International Business Machines Corporation Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic
US20090217017A1 (en) * 2008-02-26 2009-08-27 International Business Machines Corporation Method, system and computer program product for minimizing branch prediction latency
US9110683B2 (en) * 2008-08-15 2015-08-18 Apple Inc. Predicting branches for vector partitioning loops when processing vector instructions
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US11294681B2 (en) 2019-05-31 2022-04-05 Texas Instruments Incorporated Processing device with a microbranch target buffer for branch prediction using loop iteration count
US20230195517A1 (en) * 2021-12-22 2023-06-22 Advanced Micro Devices, Inc. Multi-Cycle Scheduler with Speculative Picking of Micro-Operations
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Also Published As

Publication number Publication date
DE69718278T2 (en) 2003-08-21
EP0840208B1 (en) 2003-01-08
EP0840208A2 (en) 1998-05-06
US5951679A (en) 1999-09-14
EP0840208A3 (en) 1999-04-21
JPH10177482A (en) 1998-06-30

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