[go: up one dir, main page]

DE69517629D1 - Verfahren zur selektiven Herstellung von Halbleitergebieten - Google Patents

Verfahren zur selektiven Herstellung von Halbleitergebieten

Info

Publication number
DE69517629D1
DE69517629D1 DE69517629T DE69517629T DE69517629D1 DE 69517629 D1 DE69517629 D1 DE 69517629D1 DE 69517629 T DE69517629 T DE 69517629T DE 69517629 T DE69517629 T DE 69517629T DE 69517629 D1 DE69517629 D1 DE 69517629D1
Authority
DE
Germany
Prior art keywords
selective production
semiconductor areas
semiconductor
areas
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69517629T
Other languages
English (en)
Other versions
DE69517629T2 (de
Inventor
John W Steele
Fresart Edouard De
David N Theodore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69517629D1 publication Critical patent/DE69517629D1/de
Publication of DE69517629T2 publication Critical patent/DE69517629T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H01L21/205—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
DE69517629T 1994-05-02 1995-04-18 Verfahren zur selektiven Herstellung von Halbleitergebieten Expired - Fee Related DE69517629T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/236,054 US5498578A (en) 1994-05-02 1994-05-02 Method for selectively forming semiconductor regions

Publications (2)

Publication Number Publication Date
DE69517629D1 true DE69517629D1 (de) 2000-08-03
DE69517629T2 DE69517629T2 (de) 2001-03-01

Family

ID=22887947

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69517629T Expired - Fee Related DE69517629T2 (de) 1994-05-02 1995-04-18 Verfahren zur selektiven Herstellung von Halbleitergebieten

Country Status (6)

Country Link
US (1) US5498578A (de)
EP (1) EP0681315B1 (de)
JP (1) JPH07302760A (de)
KR (1) KR950034506A (de)
CN (1) CN1055565C (de)
DE (1) DE69517629T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996015550A1 (en) * 1994-11-10 1996-05-23 Lawrence Semiconductor Research Laboratory, Inc. Silicon-germanium-carbon compositions and processes thereof
US5614249A (en) * 1995-08-28 1997-03-25 Lsi Logic Corporation Leak detection system for a gas manifold of a chemical vapor deposition apparatus
US7232728B1 (en) 1996-01-30 2007-06-19 Micron Technology, Inc. High quality oxide on an epitaxial layer
KR100417646B1 (ko) * 1996-12-28 2004-04-13 주식회사 하이닉스반도체 반도체 소자의 층간 절연막 세정방법
US5937308A (en) * 1997-03-26 1999-08-10 Advanced Micro Devices, Inc. Semiconductor trench isolation structure formed substantially within a single chamber
US5904542A (en) * 1997-03-26 1999-05-18 Advanced Micro Devices, Inc. Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric
US5891793A (en) * 1997-04-04 1999-04-06 Advanced Micro Devices, Inc. Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
US5989948A (en) * 1997-09-22 1999-11-23 Vlsi Technology, Inc. Methods of forming pairs of transistors, and methods of forming pairs of transistors having different voltage tolerances
US6271070B2 (en) * 1997-12-25 2001-08-07 Matsushita Electronics Corporation Method of manufacturing semiconductor device
DE19824142A1 (de) * 1998-05-29 1999-12-09 Siemens Ag Verfahren zum Ätzen von flourwasserstofflöslichen Schichten
WO2000012785A1 (en) * 1998-08-26 2000-03-09 Semitool, Inc. Low-temperature process for forming an epitaxial layer on a semiconductor substrate
DE19845792A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Verfahren zur Erzeugung einer amorphen oder polykristallinen Schicht auf einem Isolatorgebiet
US6404007B1 (en) * 1999-04-05 2002-06-11 Fairchild Semiconductor Corporation Trench transistor with superior gate dielectric
JP4655321B2 (ja) * 1999-08-27 2011-03-23 東京エレクトロン株式会社 熱処理方法
KR20030035152A (ko) * 2001-10-30 2003-05-09 주식회사 하이닉스반도체 반도체웨이퍼 제조방법
JP2003234402A (ja) * 2002-02-12 2003-08-22 Tokyo Electron Ltd 半導体製造方法及び半導体製造装置
US20040026255A1 (en) * 2002-08-06 2004-02-12 Applied Materials, Inc Insoluble anode loop in copper electrodeposition cell for interconnect formation
US20050082172A1 (en) * 2003-10-21 2005-04-21 Applied Materials, Inc. Copper replenishment for copper plating with insoluble anode
US7226842B2 (en) * 2004-02-17 2007-06-05 Intel Corporation Fabricating strained channel epitaxial source/drain transistors
WO2007009000A2 (en) * 2005-07-13 2007-01-18 Fujifilm Dimatix, Inc. Fluid deposition cluster tool
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US10249493B2 (en) * 2015-12-30 2019-04-02 Siltronic Ag Method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553415A (en) * 1978-10-16 1980-04-18 Mitsubishi Electric Corp Selective epitaxial growing
WO1991003834A1 (en) * 1989-09-05 1991-03-21 Mcnc Method for selectively depositing material on substrates
US5190792A (en) * 1989-09-27 1993-03-02 International Business Machines Corporation High-throughput, low-temperature process for depositing oxides
US5214002A (en) * 1989-10-25 1993-05-25 Agency Of Industrial Science And Technology Process for depositing a thermal CVD film of Si or Ge using a hydrogen post-treatment step and an optional hydrogen pre-treatment step
US5242530A (en) * 1991-08-05 1993-09-07 International Business Machines Corporation Pulsed gas plasma-enhanced chemical vapor deposition of silicon
US5227330A (en) * 1991-10-31 1993-07-13 International Business Machines Corporation Comprehensive process for low temperature SI epit axial growth

Also Published As

Publication number Publication date
KR950034506A (ko) 1995-12-28
DE69517629T2 (de) 2001-03-01
EP0681315A1 (de) 1995-11-08
JPH07302760A (ja) 1995-11-14
EP0681315B1 (de) 2000-06-28
CN1055565C (zh) 2000-08-16
US5498578A (en) 1996-03-12
CN1113033A (zh) 1995-12-06

Similar Documents

Publication Publication Date Title
DE69723338D1 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE69704964D1 (de) Verfahren zur Herstellung von Acryloxypropylsilane
DE59900390D1 (de) Verfahren zur Herstellung von Olefinen
DE69600826D1 (de) Integriertes Verfahren zur Herstellung von Buten-1
DE69611658D1 (de) Verfahren zur Herstellung von Ethylenglykol
DE69434536D1 (de) Verfahren zur Herstellung von halbleitenden Wafern
DE69713022D1 (de) Verfahren zur Herstellung von Unterkleidung
DE69517629D1 (de) Verfahren zur selektiven Herstellung von Halbleitergebieten
DE69508310D1 (de) Verfahren zur Herstellung von Mikrolinsen
DE69527818D1 (de) Verfahren zur Herstellung von Polycarbonaten
DE69618022D1 (de) Verfahren zur Herstellung von Schleifmitteln
DE59707913D1 (de) Kontinuierliches Verfahren zur Herstellung von gamma- Aminopropyltrialkoxysilanen
DE69510596D1 (de) Verfahren zur Herstellung von Organooxysilane
DE69502384D1 (de) Prozess zur herstellung von polyarylenetherketonen
DE59504792D1 (de) Verfahren zur Herstellung von Serienventilen
DE69708508D1 (de) Verfahren zur Herstellung von geschweissten Strukturen
DE69725675D1 (de) Verfahren zur Herstellung von Metallocenen
DE69809828D1 (de) Verfahren zur Herstellung von Nudeln
DE59500930D1 (de) Verfahren zur Herstellung von Ethanolaminen
DE69735433D1 (de) Verfahren zur herstellung von substituierten pyridinen
DE69700509D1 (de) Verfahren zur Herstellung von Allylsilanen
DE69712157D1 (de) Verfahren zur Herstellung von Acrylnitril
DE69819948D1 (de) Verfahren zur Herstellung von Monosilanen
DE59501267D1 (de) Verfahren zur Herstellung von Dinitrotoluol
DE69703600D1 (de) Verfahren zur Herstellung von Halbleiterscheiben

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee