DE69512125D1 - Herstellung von Löchern in polymerischen Materialien - Google Patents
Herstellung von Löchern in polymerischen MaterialienInfo
- Publication number
- DE69512125D1 DE69512125D1 DE69512125T DE69512125T DE69512125D1 DE 69512125 D1 DE69512125 D1 DE 69512125D1 DE 69512125 T DE69512125 T DE 69512125T DE 69512125 T DE69512125 T DE 69512125T DE 69512125 D1 DE69512125 D1 DE 69512125D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- holes
- polymeric materials
- polymeric
- materials
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US23409994A | 1994-04-28 | 1994-04-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69512125D1 true DE69512125D1 (de) | 1999-10-21 |
DE69512125T2 DE69512125T2 (de) | 2000-04-20 |
Family
ID=22879928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69512125T Expired - Fee Related DE69512125T2 (de) | 1994-04-28 | 1995-04-28 | Herstellung von Löchern in polymerischen Materialien |
Country Status (6)
Country | Link |
---|---|
US (1) | US6188125B1 (de) |
EP (1) | EP0680085B1 (de) |
JP (1) | JPH08139194A (de) |
KR (1) | KR950034610A (de) |
DE (1) | DE69512125T2 (de) |
TW (1) | TW271005B (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09129727A (ja) * | 1995-10-30 | 1997-05-16 | Nec Corp | 半導体装置及びその製造方法 |
DE69737542T2 (de) * | 1996-03-22 | 2007-12-13 | Texas Instruments Inc., Dallas | Halbleiterschaltung mit dielektrischer Schicht zwischen zwei Metallebenen und Verfahren zur Herstellung |
FR2747511B1 (fr) | 1996-04-10 | 1998-09-04 | Sgs Thomson Microelectronics | Interconnexions multicouches a faible capacite parasite laterale |
JPH10223624A (ja) * | 1997-02-06 | 1998-08-21 | Nec Yamagata Ltd | 半導体装置の製造方法 |
JPH10335458A (ja) | 1997-05-30 | 1998-12-18 | Nec Corp | 半導体装置及びその製造方法 |
US6294455B1 (en) | 1997-08-20 | 2001-09-25 | Micron Technology, Inc. | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry |
JP3199006B2 (ja) * | 1997-11-18 | 2001-08-13 | 日本電気株式会社 | 層間絶縁膜の形成方法および絶縁膜形成装置 |
US6197696B1 (en) | 1998-03-26 | 2001-03-06 | Matsushita Electric Industrial Co., Ltd. | Method for forming interconnection structure |
FR2777697B1 (fr) * | 1998-04-16 | 2000-06-09 | St Microelectronics Sa | Circuit integre avec couche d'arret et procede de fabrication associe |
US20010029091A1 (en) * | 1998-04-17 | 2001-10-11 | U.S. Philips Corporation | Method for manufacturing an electronic device comprising an organic- containing material |
JP3102409B2 (ja) * | 1998-04-30 | 2000-10-23 | 日本電気株式会社 | 配線の形成方法及びプラズマアッシング装置 |
US6127263A (en) * | 1998-07-10 | 2000-10-03 | Applied Materials, Inc. | Misalignment tolerant techniques for dual damascene fabrication |
US6391771B1 (en) | 1998-07-23 | 2002-05-21 | Applied Materials, Inc. | Integrated circuit interconnect lines having sidewall layers |
TW437040B (en) | 1998-08-12 | 2001-05-28 | Applied Materials Inc | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US6225207B1 (en) * | 1998-10-01 | 2001-05-01 | Applied Materials, Inc. | Techniques for triple and quadruple damascene fabrication |
US6309801B1 (en) | 1998-11-18 | 2001-10-30 | U.S. Philips Corporation | Method of manufacturing an electronic device comprising two layers of organic-containing material |
US6258732B1 (en) * | 1999-02-04 | 2001-07-10 | International Business Machines Corporation | Method of forming a patterned organic dielectric layer on a substrate |
US6770975B2 (en) | 1999-06-09 | 2004-08-03 | Alliedsignal Inc. | Integrated circuits with multiple low dielectric-constant inter-metal dielectrics |
EP1077475A3 (de) | 1999-08-11 | 2003-04-02 | Applied Materials, Inc. | Verfahren zur Mikrobearbeitung einer Körperhölung mit mehrfachem Profil |
DE19961103C2 (de) * | 1999-12-17 | 2002-03-14 | Infineon Technologies Ag | Dielektrische Füllung von elektrischen Verdrahtungsebenen und Verfahren zur Herstellung einer elektrischen Verdrahtung |
US6720249B1 (en) | 2000-04-17 | 2004-04-13 | International Business Machines Corporation | Protective hardmask for producing interconnect structures |
DE10127934A1 (de) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | Leiterbahnanordnung und Verfahren zum Herstellen einer gekapselten Leiterbahnkopplung |
DE10146146B4 (de) * | 2001-09-19 | 2004-02-05 | Infineon Technologies Ag | Verfahren zur elektrischen Isolation nebeneinander liegender metallischer Leiterbahnen und Halbleiterbauelement mit voneinander isolierten metallischen Leiterbahnen |
JP3667303B2 (ja) | 2002-06-04 | 2005-07-06 | 沖電気工業株式会社 | 多層配線構造部の製造方法 |
US6878620B2 (en) * | 2002-11-12 | 2005-04-12 | Applied Materials, Inc. | Side wall passivation films for damascene cu/low k electronic devices |
DE10301243B4 (de) * | 2003-01-15 | 2009-04-16 | Infineon Technologies Ag | Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung |
US7608538B2 (en) * | 2007-01-05 | 2009-10-27 | International Business Machines Corporation | Formation of vertical devices by electroplating |
US9505609B2 (en) * | 2015-04-29 | 2016-11-29 | Invensense, Inc. | CMOS-MEMS integrated device with selective bond pad protection |
DE102019131408A1 (de) | 2019-06-28 | 2020-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Margenverbesserung für durchkontaktierung am hinteren ende der leitung zu einer metallleitung |
CN112151497B (zh) | 2019-06-28 | 2023-08-22 | 台湾积体电路制造股份有限公司 | 半导体结构以及形成半导体结构的方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4523372A (en) * | 1984-05-07 | 1985-06-18 | Motorola, Inc. | Process for fabricating semiconductor device |
JPS6185844A (ja) * | 1984-09-28 | 1986-05-01 | シーメンス、アクチエンゲゼルヤフト | 集積回路とその製法 |
JPH01235254A (ja) | 1988-03-15 | 1989-09-20 | Nec Corp | 半導体装置及びその製造方法 |
JP2782801B2 (ja) * | 1989-06-23 | 1998-08-06 | 日本電気株式会社 | 半導体装置の配線構造 |
JPH04174541A (ja) | 1990-03-28 | 1992-06-22 | Nec Corp | 半導体集積回路及びその製造方法 |
JPH04233732A (ja) * | 1990-08-16 | 1992-08-21 | Motorola Inc | 半導体の製造工程で使用するスピン・オン誘電体 |
US5284801A (en) * | 1992-07-22 | 1994-02-08 | Vlsi Technology, Inc. | Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric |
JPH0697299A (ja) * | 1992-09-11 | 1994-04-08 | Nec Yamagata Ltd | 半導体装置 |
-
1995
- 1995-04-26 JP JP7102527A patent/JPH08139194A/ja active Pending
- 1995-04-27 KR KR1019950010066A patent/KR950034610A/ko active IP Right Grant
- 1995-04-28 EP EP95106399A patent/EP0680085B1/de not_active Expired - Lifetime
- 1995-04-28 DE DE69512125T patent/DE69512125T2/de not_active Expired - Fee Related
- 1995-06-07 US US08/476,293 patent/US6188125B1/en not_active Expired - Lifetime
- 1995-06-08 TW TW084105791A patent/TW271005B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950034610A (ko) | 1995-12-28 |
DE69512125T2 (de) | 2000-04-20 |
US6188125B1 (en) | 2001-02-13 |
TW271005B (de) | 1996-02-21 |
JPH08139194A (ja) | 1996-05-31 |
EP0680085A1 (de) | 1995-11-02 |
EP0680085B1 (de) | 1999-09-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |