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DE69434695D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
DE69434695D1
DE69434695D1 DE69434695T DE69434695T DE69434695D1 DE 69434695 D1 DE69434695 D1 DE 69434695D1 DE 69434695 T DE69434695 T DE 69434695T DE 69434695 T DE69434695 T DE 69434695T DE 69434695 D1 DE69434695 D1 DE 69434695D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69434695T
Other languages
English (en)
Other versions
DE69434695T2 (de
Inventor
Shouichi Kawamura
Nobuaki Takashina
Yasushi Kasa
Kiyoshi Itano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69434695D1 publication Critical patent/DE69434695D1/de
Application granted granted Critical
Publication of DE69434695T2 publication Critical patent/DE69434695T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE69434695T 1993-03-17 1994-01-25 Verfahren zur Herstellung einer Halbleiteranordnung Expired - Lifetime DE69434695T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5738093 1993-03-17
JP5738093A JP3342730B2 (ja) 1993-03-17 1993-03-17 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69434695D1 true DE69434695D1 (de) 2006-05-18
DE69434695T2 DE69434695T2 (de) 2006-10-05

Family

ID=13054004

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69434550T Expired - Lifetime DE69434550T2 (de) 1993-03-17 1994-01-25 Nichtflüchtiges Halbleiterspeicherbauelement, welches die Anforderungen an dessen Spannungsfestigkeit verringert
DE69434695T Expired - Lifetime DE69434695T2 (de) 1993-03-17 1994-01-25 Verfahren zur Herstellung einer Halbleiteranordnung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69434550T Expired - Lifetime DE69434550T2 (de) 1993-03-17 1994-01-25 Nichtflüchtiges Halbleiterspeicherbauelement, welches die Anforderungen an dessen Spannungsfestigkeit verringert

Country Status (5)

Country Link
US (2) US5406524A (de)
EP (3) EP1223619B1 (de)
JP (1) JP3342730B2 (de)
KR (1) KR970003808B1 (de)
DE (2) DE69434550T2 (de)

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JP3004043B2 (ja) * 1990-10-23 2000-01-31 株式会社東芝 不揮発性半導体メモリ装置
EP0961290B1 (de) * 1991-12-09 2001-11-14 Fujitsu Limited Flash-Speicher mit besserer Löschbarkeit und dessen Schaltung
JP3406077B2 (ja) * 1994-08-26 2003-05-12 三菱電機株式会社 不揮発性半導体記憶装置
DE19526012C2 (de) * 1995-07-17 1997-09-11 Siemens Ag Elektrisch lösch- und programmierbare nicht-flüchtige Speicherzelle
US5818758A (en) * 1996-12-31 1998-10-06 Intel Corporation Zero voltage drop negative switch for dual well processes
JP3191861B2 (ja) * 1997-01-30 2001-07-23 日本電気株式会社 不揮発性半導体メモリ装置及びその消去方法
JPH10261946A (ja) * 1997-03-19 1998-09-29 Mitsubishi Electric Corp 半導体集積回路
US6026026A (en) * 1997-12-05 2000-02-15 Hyundai Electronics America, Inc. Self-convergence of post-erase threshold voltages in a flash memory cell using transient response
US6229732B1 (en) 1998-09-03 2001-05-08 Macronix International Co., Ltd. Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices
US6055186A (en) * 1998-10-23 2000-04-25 Macronix International Co., Ltd. Regulated negative voltage supply circuit for floating gate memory devices
JP3540211B2 (ja) 1999-08-30 2004-07-07 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置及びそのプログラム方法
US6456554B1 (en) * 1999-10-19 2002-09-24 Texas Instruments Incorporated Chip identifier and method of fabrication
US6639835B2 (en) * 2000-02-29 2003-10-28 Micron Technology, Inc. Static NVRAM with ultra thin tunnel oxides
JP3633853B2 (ja) 2000-06-09 2005-03-30 Ｎｅｃエレクトロニクス株式会社 フラッシュメモリの消去動作制御方法およびフラッシュメモリの消去動作制御装置
JP3918442B2 (ja) * 2001-02-19 2007-05-23 ソニー株式会社 半導体装置及びその製造方法
US6703670B1 (en) * 2001-04-03 2004-03-09 National Semiconductor Corporation Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
JP4809545B2 (ja) * 2001-05-31 2011-11-09 株式会社半導体エネルギー研究所 半導体不揮発性メモリ及び電子機器
US20060170053A1 (en) * 2003-05-09 2006-08-03 Yee-Chia Yeo Accumulation mode multiple gate transistor
US7095653B2 (en) * 2003-10-08 2006-08-22 Micron Technology, Inc. Common wordline flash array architecture
US7149132B2 (en) * 2004-09-24 2006-12-12 Ovonyx, Inc. Biasing circuit for use in a non-volatile memory device
JP2007013197A (ja) * 2006-08-24 2007-01-18 Renesas Technology Corp 不揮発性半導体記憶装置
JP5369413B2 (ja) * 2007-09-14 2013-12-18 富士電機株式会社 半導体装置
JP2012146033A (ja) * 2011-01-07 2012-08-02 Toshiba Corp メモリ装置
US11145368B2 (en) * 2020-01-06 2021-10-12 Microchip Technology Incorporated Method and system for reliable and secure memory erase

Family Cites Families (19)

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Publication number Priority date Publication date Assignee Title
US3660819A (en) * 1970-06-15 1972-05-02 Intel Corp Floating gate transistor and method for charging and discharging same
US4072868A (en) * 1976-09-16 1978-02-07 International Business Machines Corporation FET inverter with isolated substrate load
US4559694A (en) * 1978-09-13 1985-12-24 Hitachi, Ltd. Method of manufacturing a reference voltage generator device
JPS56108258A (en) * 1980-02-01 1981-08-27 Seiko Instr & Electronics Ltd Semiconductor device
US4490629A (en) * 1982-05-10 1984-12-25 American Microsystems, Inc. High voltage circuits in low voltage CMOS process
US4573144A (en) * 1982-09-30 1986-02-25 Motorola, Inc. Common floating gate programmable link
EP0160720B1 (de) * 1984-05-07 1988-01-07 Deutsche ITT Industries GmbH Halbleiterspeicherzelle mit einem potentialmässig schwebenden Speichergate
FR2576133B1 (fr) * 1985-01-15 1991-04-26 Eurotechnique Sa Memoire en circuit integre a haute fiabilite
US4675557A (en) * 1986-03-20 1987-06-23 Motorola Inc. CMOS voltage translator
JPS63153799A (ja) * 1986-08-08 1988-06-27 Nec Corp 半導体メモリ
JPS647557A (en) * 1987-06-29 1989-01-11 Nec Corp Vertically stacked read-only memory
US4885719A (en) * 1987-08-19 1989-12-05 Ict International Cmos Technology, Inc. Improved logic cell array using CMOS E2 PROM cells
JPH0695545B2 (ja) * 1988-01-07 1994-11-24 株式会社東芝 半導体集積回路
US4866307A (en) * 1988-04-20 1989-09-12 Texas Instruments Incorporated Integrated programmable bit circuit using single-level poly construction
US5016217A (en) * 1988-05-17 1991-05-14 Ict International Cmos Technology, Inc. Logic cell array using CMOS EPROM cells having reduced chip surface area
US4951114A (en) * 1988-12-05 1990-08-21 Raytheon Company Complementary metal electrode semiconductor device
JP2888898B2 (ja) * 1990-02-23 1999-05-10 株式会社日立製作所 半導体集積回路
US5272368A (en) * 1991-05-10 1993-12-21 Altera Corporation Complementary low power non-volatile reconfigurable EEcell
US5452248A (en) * 1991-06-27 1995-09-19 Kabushiki Kaisha Toshiba Method of operating a nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
EP1223619A1 (de) 2002-07-17
DE69434550T2 (de) 2006-03-30
US5406524A (en) 1995-04-11
KR970003808B1 (ko) 1997-03-22
EP0616368A2 (de) 1994-09-21
DE69434550D1 (de) 2005-12-29
KR940022564A (ko) 1994-10-21
DE69434695T2 (de) 2006-10-05
US5581107A (en) 1996-12-03
EP0616368B1 (de) 2005-11-23
JP3342730B2 (ja) 2002-11-11
JPH06275842A (ja) 1994-09-30
EP1217626A1 (de) 2002-06-26
EP1223619B1 (de) 2006-04-05
EP0616368A3 (de) 1998-01-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE