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DE69434249D1 - Digitaler Signalprozessor mit Coprozessor zur Viterbi Decodierung - Google Patents

Digitaler Signalprozessor mit Coprozessor zur Viterbi Decodierung

Info

Publication number
DE69434249D1
DE69434249D1 DE69434249T DE69434249T DE69434249D1 DE 69434249 D1 DE69434249 D1 DE 69434249D1 DE 69434249 T DE69434249 T DE 69434249T DE 69434249 T DE69434249 T DE 69434249T DE 69434249 D1 DE69434249 D1 DE 69434249D1
Authority
DE
Germany
Prior art keywords
coprocessor
digital signal
signal processor
viterbi decoding
viterbi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69434249T
Other languages
English (en)
Other versions
DE69434249T2 (de
Inventor
David Mark Blaker
Muhammad Shafiul Mobin
Gregory Stephen Ellard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69434249D1 publication Critical patent/DE69434249D1/de
Publication of DE69434249T2 publication Critical patent/DE69434249T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
DE69434249T 1993-11-16 1994-11-09 Digitaler Signalprozessor mit Coprozessor zur Viterbi Decodierung Expired - Lifetime DE69434249T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US153391 1988-02-08
US15339193A 1993-11-16 1993-11-16

Publications (2)

Publication Number Publication Date
DE69434249D1 true DE69434249D1 (de) 2005-03-03
DE69434249T2 DE69434249T2 (de) 2005-12-22

Family

ID=22547025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69434249T Expired - Lifetime DE69434249T2 (de) 1993-11-16 1994-11-09 Digitaler Signalprozessor mit Coprozessor zur Viterbi Decodierung

Country Status (6)

Country Link
US (1) US5748650A (de)
EP (2) EP1111798B1 (de)
JP (1) JPH07202726A (de)
KR (1) KR100336246B1 (de)
DE (1) DE69434249T2 (de)
TW (1) TW243568B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2724273B1 (fr) * 1994-09-05 1997-01-03 Sgs Thomson Microelectronics Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi
US8489860B1 (en) * 1997-12-22 2013-07-16 Texas Instruments Incorporated Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device
EP0945788B1 (de) * 1998-02-04 2004-08-04 Texas Instruments Inc. Datenverarbeitungssytem mit einem digitalen Signalprozessor und einem Koprozessor und Datenverarbeitungsverfahren
US20020110206A1 (en) * 1998-11-12 2002-08-15 Neal Becker Combined interference cancellation with FEC decoding for high spectral efficiency satellite communications
WO2001069376A2 (en) * 2000-03-15 2001-09-20 Arc International Plc Method and apparatus for processor code optimization using code compression
WO2002021699A2 (en) * 2000-09-08 2002-03-14 Avaz Networks Programmable and multiplierless viterbi accelerator
US6944206B1 (en) * 2000-11-20 2005-09-13 Ericsson Inc. Rate one coding and decoding methods and systems
EP1410513A4 (de) * 2000-12-29 2005-06-29 Infineon Technologies Ag Kanal-codec-prozessor, der für mehrere drahtlose kommunikationsstandards konfigurierbar ist
JP2007299279A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 演算装置、プロセッサシステム、及び映像処理装置
US8694878B2 (en) * 2011-06-15 2014-04-08 Texas Instruments Incorporated Processor instructions to accelerate Viterbi decoding
DE102014107297A1 (de) 2014-05-23 2015-11-26 Karl Storz Gmbh & Co. Kg Positionsgeregelter elektrodynamischer Linearantrieb
TWI742322B (zh) * 2017-12-01 2021-10-11 英屬開曼群島商睿能創意公司 輪轂裝置、充電系統及車輪

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2564805B2 (ja) * 1985-08-08 1996-12-18 日本電気株式会社 情報処理装置
US4748626A (en) * 1987-01-28 1988-05-31 Racal Data Communications Inc. Viterbi decoder with reduced number of data move operations
US5151904A (en) * 1990-09-27 1992-09-29 The Titan Corporation Reconfigurable, multi-user viterbi decoder
FR2669445B1 (fr) * 1990-11-15 1993-01-08 Alcatel Radiotelephone Dispositif prevu pour le traitement de l'algorithme de viterbi comprenant un processeur et un operateur specialise.
US5220570A (en) * 1990-11-30 1993-06-15 The Board Of Trustees Of The Leland Stanford Junior University Programmable viterbi signal processor
BE1004814A3 (nl) * 1991-05-08 1993-02-02 Bell Telephone Mfg Decodeerinrichting.
KR100304222B1 (ko) * 1992-03-23 2001-11-22 미셀 달사세 프로세서를 구비하여 비터비 알고리즘을 처리하는 장치
US5432804A (en) * 1993-11-16 1995-07-11 At&T Corp. Digital processor and viterbi decoder having shared memory

Also Published As

Publication number Publication date
EP0653848A3 (de) 1997-02-05
DE69434249T2 (de) 2005-12-22
EP1111798A1 (de) 2001-06-27
KR100336246B1 (ko) 2002-11-23
EP0653848A2 (de) 1995-05-17
KR950015072A (ko) 1995-06-16
US5748650A (en) 1998-05-05
JPH07202726A (ja) 1995-08-04
TW243568B (en) 1995-03-21
EP1111798B1 (de) 2005-01-26

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Legal Events

Date Code Title Description
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