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DE69431740D1 - Mehrlagige Verdrahtungsplatine und ihre Herstellung - Google Patents

Mehrlagige Verdrahtungsplatine und ihre Herstellung

Info

Publication number
DE69431740D1
DE69431740D1 DE69431740T DE69431740T DE69431740D1 DE 69431740 D1 DE69431740 D1 DE 69431740D1 DE 69431740 T DE69431740 T DE 69431740T DE 69431740 T DE69431740 T DE 69431740T DE 69431740 D1 DE69431740 D1 DE 69431740D1
Authority
DE
Germany
Prior art keywords
manufacture
wiring board
layer wiring
layer
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69431740T
Other languages
English (en)
Other versions
DE69431740T2 (de
Inventor
Hisashi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69431740D1 publication Critical patent/DE69431740D1/de
Application granted granted Critical
Publication of DE69431740T2 publication Critical patent/DE69431740T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE69431740T 1993-04-21 1994-04-20 Mehrlagige Verdrahtungsplatine und ihre Herstellung Expired - Fee Related DE69431740T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5117954A JPH0828580B2 (ja) 1993-04-21 1993-04-21 配線基板構造及びその製造方法

Publications (2)

Publication Number Publication Date
DE69431740D1 true DE69431740D1 (de) 2003-01-02
DE69431740T2 DE69431740T2 (de) 2003-04-24

Family

ID=14724359

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69431740T Expired - Fee Related DE69431740T2 (de) 1993-04-21 1994-04-20 Mehrlagige Verdrahtungsplatine und ihre Herstellung

Country Status (5)

Country Link
US (2) US5534666A (de)
EP (1) EP0624904B1 (de)
JP (1) JPH0828580B2 (de)
CA (1) CA2121712C (de)
DE (1) DE69431740T2 (de)

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US6294743B1 (en) * 1995-04-28 2001-09-25 Victor Company Of Japan, Ltd. Multilayer print circuit board and the production method of the multilayer print circuit board
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JP2001251056A (ja) * 2000-03-03 2001-09-14 Sony Corp プリント配線基板の製造方法
JP2001320171A (ja) * 2000-05-08 2001-11-16 Shinko Electric Ind Co Ltd 多層配線基板及び半導体装置
JP3418615B2 (ja) * 2001-06-12 2003-06-23 沖電気工業株式会社 半導体素子およびその製造方法
JP3807312B2 (ja) * 2002-01-18 2006-08-09 富士通株式会社 プリント基板とその製造方法
US6826830B2 (en) * 2002-02-05 2004-12-07 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
JP4148201B2 (ja) * 2004-08-11 2008-09-10 ソニー株式会社 電子回路装置
JP2006216711A (ja) * 2005-02-02 2006-08-17 Ibiden Co Ltd 多層プリント配線板
US20070202655A1 (en) * 2005-12-08 2007-08-30 Intel Corporation Method of providing a via opening in a dielectric film of a thin film capacitor
TWI337059B (en) * 2007-06-22 2011-02-01 Princo Corp Multi-layer substrate and manufacture method thereof
US20090321119A1 (en) * 2008-06-30 2009-12-31 Yasuhiro Kohara Device mounting board, semiconductor module, mobile device, and manufacturing method of device mounting board
KR20110113980A (ko) * 2010-04-12 2011-10-19 삼성전자주식회사 필름을 포함한 다층 인쇄회로기판 및 그 제조 방법
TWI381780B (zh) * 2010-04-28 2013-01-01 Wus Printed Circuit Co Ltd 可辨識印刷電路板之製造方法
CN106455369A (zh) * 2010-06-03 2017-02-22 Ddi环球有限公司 利用盲过孔和内部微过孔以耦联子组件来制造印刷电路板的系统和方法
TWI422485B (zh) * 2010-12-31 2014-01-11 Tong Hsing Electronic Ind Ltd 一種具有反射膜之陶瓷基板及其製造方法
DE102012101237A1 (de) * 2012-02-16 2013-08-22 Ev Group E. Thallner Gmbh Verfahren zum temporären Verbinden eines Produktsubstrats mit einem Trägersubstrat
JP2013187255A (ja) * 2012-03-06 2013-09-19 Ngk Spark Plug Co Ltd 配線基板の製造方法
US9159670B2 (en) * 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
DE102014210895A1 (de) * 2014-06-06 2015-12-17 Continental Automotive Gmbh Mehrlagige Leiterplatte und Verfahren zu dessen Herstellung
RU2600514C1 (ru) * 2015-06-01 2016-10-20 Открытое акционерное общество "Институт точной технологии и проектирования" Способ изготовления вертикальных контактных структур на полупроводниковых пластинах или печатных платах
DE102016219733A1 (de) 2016-10-11 2018-04-12 Continental Automotive Gmbh Verfahren zur Herstellung einer mehrlagigen Leiterplatte
JP7100980B2 (ja) 2018-01-22 2022-07-14 ローム株式会社 Ｌｅｄパッケージ

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Also Published As

Publication number Publication date
JPH06310870A (ja) 1994-11-04
CA2121712A1 (en) 1994-10-22
EP0624904A2 (de) 1994-11-17
CA2121712C (en) 1998-08-25
US5534666A (en) 1996-07-09
EP0624904A3 (de) 1995-04-19
EP0624904B1 (de) 2002-11-20
US5590461A (en) 1997-01-07
JPH0828580B2 (ja) 1996-03-21
DE69431740T2 (de) 2003-04-24

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee