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DE69419663D1 - Multitasking-Prozessorarchitektur - Google Patents

Multitasking-Prozessorarchitektur

Info

Publication number
DE69419663D1
DE69419663D1 DE69419663T DE69419663T DE69419663D1 DE 69419663 D1 DE69419663 D1 DE 69419663D1 DE 69419663 T DE69419663 T DE 69419663T DE 69419663 T DE69419663 T DE 69419663T DE 69419663 D1 DE69419663 D1 DE 69419663D1
Authority
DE
Germany
Prior art keywords
processor architecture
multitasking processor
multitasking
architecture
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69419663T
Other languages
English (en)
Other versions
DE69419663T2 (de
Inventor
Alain Artieri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of DE69419663D1 publication Critical patent/DE69419663D1/de
Application granted granted Critical
Publication of DE69419663T2 publication Critical patent/DE69419663T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
DE69419663T 1993-05-27 1994-05-20 Multitasking-Prozessorarchitektur Expired - Fee Related DE69419663T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9306612A FR2705804B1 (fr) 1993-05-27 1993-05-27 Architecture de processeur multi-tâches.

Publications (2)

Publication Number Publication Date
DE69419663D1 true DE69419663D1 (de) 1999-09-02
DE69419663T2 DE69419663T2 (de) 2000-01-27

Family

ID=9447691

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419663T Expired - Fee Related DE69419663T2 (de) 1993-05-27 1994-05-20 Multitasking-Prozessorarchitektur

Country Status (5)

Country Link
US (1) US5600837A (de)
EP (1) EP0626642B1 (de)
JP (1) JP3713723B2 (de)
DE (1) DE69419663T2 (de)
FR (1) FR2705804B1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19500957A1 (de) * 1994-07-19 1996-01-25 Bosch Gmbh Robert Verfahren zur Steuerung von technischen Vorgängen oder Prozessen
FR2724243B1 (fr) * 1994-09-06 1997-08-14 Sgs Thomson Microelectronics Systeme de traitement multitaches
US5986709A (en) * 1996-11-18 1999-11-16 Samsung Electronics Co., Ltd. Adaptive lossy IDCT for multitasking environment
US5852451A (en) * 1997-01-09 1998-12-22 S3 Incorporation Pixel reordering for improved texture mapping
EP0863462B8 (de) * 1997-03-04 2010-07-28 Panasonic Corporation Zur effizienten Ausführung vieler asynchronen Ereignisaufgaben geeigneter Prozessor
US6658447B2 (en) * 1997-07-08 2003-12-02 Intel Corporation Priority based simultaneous multi-threading
JP3990011B2 (ja) 1997-10-31 2007-10-10 沖電気工業株式会社 復号画像変換回路および復号画像変換装置
US6862635B1 (en) * 1998-11-13 2005-03-01 Cray Inc. Synchronization techniques in a multithreaded environment
US7020879B1 (en) * 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US6477562B2 (en) 1998-12-16 2002-11-05 Clearwater Networks, Inc. Prioritized instruction scheduling for multi-streaming processors
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US6275749B1 (en) * 1998-12-22 2001-08-14 Philips Electronics North America Corporation Interrupt-controlled thread processing
US7668189B1 (en) * 1999-07-08 2010-02-23 Thomson Licensing Adaptive transport protocol
US7318090B1 (en) * 1999-10-20 2008-01-08 Sony Corporation Method for utilizing concurrent context switching to support isochronous processes
JP2004518183A (ja) 2000-07-14 2004-06-17 クリアウオーター・ネツトワークス・インコーポレイテツド マルチスレッド・システムにおける命令のフェッチとディスパッチ
US7173627B2 (en) * 2001-06-29 2007-02-06 Intel Corporation Apparatus, method and system with a graphics-rendering engine having a graphics context manager
US6885374B2 (en) * 2001-06-29 2005-04-26 Intel Corporation Apparatus, method and system with a graphics-rendering engine having a time allocator
US20080059672A1 (en) * 2006-08-30 2008-03-06 Irish John D Methods and Apparatus for Scheduling Prioritized Commands on a Bus
US9218211B2 (en) * 2009-01-02 2015-12-22 International Business Machines Corporation Priority promotion for service requests
US8583700B2 (en) * 2009-01-02 2013-11-12 International Business Machines Corporation Creation of date window for record selection
JP5848153B2 (ja) * 2012-02-17 2016-01-27 ルネサスエレクトロニクス株式会社 信号処理装置及び半導体装置
US11556274B1 (en) 2021-09-01 2023-01-17 Western Digital Technologies, Inc. Endurance groups ECC allocation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4462074A (en) * 1981-11-19 1984-07-24 Codex Corporation Do loop circuit
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
EP0221741A3 (de) * 1985-11-01 1991-01-16 Advanced Micro Devices, Inc. Mikroprogrammierte Rechnerablaufsteuerungen
GB2187577B (en) * 1986-03-07 1989-11-15 Stc Plc Digital computer systems
US5016162A (en) * 1988-03-30 1991-05-14 Data General Corp. Contention revolution in a digital computer system

Also Published As

Publication number Publication date
EP0626642B1 (de) 1999-07-28
JPH0756751A (ja) 1995-03-03
EP0626642A1 (de) 1994-11-30
JP3713723B2 (ja) 2005-11-09
DE69419663T2 (de) 2000-01-27
US5600837A (en) 1997-02-04
FR2705804B1 (fr) 1995-08-11
FR2705804A1 (fr) 1994-12-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee