DE69320870T2 - Display device - Google Patents

Abstract

A display apparatus includes a matrix of a group of scanning lines and a group of data signal lines intersecting the scanning lines, pixels each formed at an intersection of the scanning lines and data signal lines, and a driver for supplying drive signals to the matrix so as to effect a display at the pixels. The scanning lines are divided into at least three blocks each comprising a plurality of adjacent scanning lines. The driver includes scanning means for sequentially selecting the at least three blocks so as not to select neighboring blocks consecutively and for consecutively selecting adjacent scanning lines in a selected block. As a result, flicker in a repetitive image is prevented while maintaining good observability of a motion picture. <IMAGE>

Description

FIELD OF THE INVENTION AND RELATED ART

The present invention relates to a display device for use in a television receiver, a computer terminal, an image data processing device such as a video camera viewfinder, etc., particularly to a planar or flat display device having scanning lines and data (signal) lines.

Flat panel display devices include, for example, a type having electron discharge elements at respective pixels and a type having a liquid crystal for forming the pixels. Liquid crystal display devices having a liquid crystal are widely used among others and continue to require attention.

To facilitate understanding, an exemplary display device having a liquid crystal device is described below.

In known liquid crystal display devices, a liquid crystal material is interposed between scanning lines (scanning electrodes) and data lines (data electrodes) which form an electrode matrix for forming a large number of pixels for displaying image data. The display device is driven in a multiplexed manner so that an address or scanning signal is sequentially applied to the scanning electrodes, and prescribed data signals are applied to the data electrodes in parallel in synchronism with the address signal.

The sequential application of the address signal is carried out according to various schemes, including the non-interlaced scanning scheme, in which the address signal for selecting the scanning electrodes is applied sequentially without skipping from one side of the scanning electrodes to the other, the two-interlaced scanning scheme, in which an address signal is applied sequentially to every other scanning electrode, and the N-interlaced scanning scheme (N = 3, 4, 5, ...) in which an address signal is applied sequentially skipping two or more skipped scanning electrodes, i.e., to every N-th scanning electrode, as disclosed by Mihara et al. in European Patent Specification EP-A 316774. Particularly, in a display device requiring a substantial selection time for a scanning electrode, a 2n-interlace scanning scheme for selecting every 2n-th scanning electrode (n = 1, 2, 3, ...) is often used in order to suppress flicker due to the low-frequency scanning control and in view of the advantageous configuration of the scanning system.

The time-dependent change in the voltage applied between the electrodes (ie, to a pixel) (ie, the voltage waveform) differs depending on whether the data signal applied to them is for writing "black" or "white", so that a different optical response of the pixel results. More specifically, a pixel is switched to a black or white state when the pixel in question is located on a selected scanning electrode. On the other hand, when the pixel in question is located on a non-selected scanning electrode, the pixel causes a change in brightness level depending on the data waveform, while maintaining black or white. If a black signal and a white signal are alternately applied to a particular data electrode, the pixels on the data electrode cause a change in brightness level during the period of non-selection of the pixels. a change in the brightness level in a cycle of alternation of the black and white signals. If the alternation cycle is less than a certain constant, which is determined depending on the brightness difference corresponding to the application of the black and white signals.

In a display device, a repeated image with 2n each (n = an integer of 1, 2, 3, ...) is often used to advantageously design a graphics system. If the control is carried out according to the aforementioned 2n interlace scheme, flickering can occur in some cases due to the periodic repetition of the white signal.

If a higher interlace rate is used to increase the raster frequency in order to suppress flickering, this can in some cases lead to a reduced recognizability of a moving image (moving image).

U.S. Patent No. 5,172,105, entitled "DISPLAY APPARATUS" and assigned to Katakura et al., describes a display apparatus having a driving scheme for sequentially selecting the scanning electrodes while skipping a prescribed number of skipped scanning electrodes to suppress the occurrence of flicker and improve the perceptibility of a moving image.

On the other hand, there may be cases where scanning electrodes must be selected one after the other without skipping in order to display a complex image with good image quality or to prevent the deterioration of image quality accompanying a temperature change. In such a case, it is problematic to use the driving scheme disclosed in the above-mentioned US patent as such.

Furthermore, DE-C-36 13 446 discloses a liquid crystal light modulating device with a pixel matrix. The pixel matrix consists of a group of scanning electrodes and a group of signal electrodes which are separated from each other by a gap. A ferroelectric liquid crystal material is filled into the gap between them. In addition, a scanning line drive circuit and a common display signal generator are connected to the scanning electrodes and the signal electrodes, respectively, in order to drive one of a plurality of selectable blocks, i.e. four blocks. The scanning line drive circuit comprises a plurality of separate logic units for selecting one of the plurality of blocks. In order to write a selected block, a selection signal is sequentially applied to the signal lines in order to supply the information signals to the signal lines in sequence. Consequently, a block is selected to select a part of all the scan lines (i.e., a partial overwrite), and the scan lines of the selected block are subjected to the non-interlaced scanning operation.

Furthermore, EP-A-0 434 042 describes a display device in which a ferroelectric liquid crystal is arranged between a group of scanning electrodes and a group of data electrodes forming an electrode matrix. A driving device formed by a graphic controller applies a scanning signal to the scanning electrodes and data signals to the data electrodes in synchronism with the scanning signal. Thereby, the scanning electrodes are divided into a plurality of blocks, the scanning electrodes are selected while at least one scanning electrode is omitted. That is, all the scanning lines of each block are subjected to an interlaced scanning operation, the blocks being selected sequentially from the top to the bottom without skipping, i.e. in a non-skipping manner.

It is an object of the present invention to provide a display device and a display method by means of which images can be displayed with improved image quality.

According to the invention, the object is achieved by a display device according to patent claim 1 and by a display method according to patent claim 10.

In the drive scheme used in the present invention, no selection signal is applied to the scanning lines, a predetermined number of scanning lines are skipped from the beginning to the end of a vertical scan, as in the known drive scheme, but the blocks are selected at an interval of at least one block, i.e., in a manner that can be called a "block skip scanning" scheme. As a result, the black data signal and the white data signal continuously alternate until the line sequential scanning is completed within a block even when displaying a repeated image in which "white" and "black" are alternately applied in a data line direction, so that the reduction in the frequency of the alternation of the black and white data signals is suppressed, thereby preventing flickering. Furthermore, non-interlaced scanning is performed within each block, so that the recognizability of a moving image is maintained.

These and other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a circuit diagram to illustrate a basic structure of an embodiment of the display device according to the invention.

Fig. 2 shows a timing diagram of a group of scanning signals used in the display device according to Fig. 1.

Fig. 3 shows a block diagram of a display device or a display system according to the present invention.

Fig. 4 is a schematic partial plan view of a liquid crystal display unit (image area) used in the present invention, and Fig. 5 is a schematic sectional view thereof.

Figs. 6 and 10 show schematic views of the scan line blocks, respectively.

Figures 7, 9, 11 and 12 each show a basic view of the memories used in the invention.

Fig. 8 shows a block diagram of an algorithm used in the invention.

Fig. 13 shows a group of drive waveforms used in the drive system according to the present invention.

Fig. 14 shows a timing diagram with the time correlation between the signal transfer and the control.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to a preferred embodiment of the present invention, a display device is provided with a a plurality of scanning lines, wherein a display screen or a console formed by the scanning lines is divided into at least three areas (blocks), the blocks being selected one after the other such that adjacent blocks are not selected consecutively, ie the blocks are selected with a spacing of at least one block, adjacent scanning lines within each block being selected consecutively in a non-interlaced scanning mode.

The following is a description of a basic structure of the display device according to the invention with reference to Fig. 1.

Fig. 1 shows a circuit diagram for illustrating a display device. In detail, Fig. 1 shows a display unit DPU with a total of 14 scanning lines (C11 ... C14, C21 ... C24, ..., C41 ... C44), which are divided into four blocks (BK1, BK2, ..., BK4) with four adjacent scanning lines each.

CEL indicates a pixel and CELi,j generally indicates a pixel formed at the intersection of an i-th scanning line and a j-th data signal line. Each pixel represents certain display data (optical data) based on a combination of two signals applied to the pixel, i.e., a signal applied to an associated scanning line from a scanning line application circuit 102 and a signal applied to an associated one of the data signal lines (S1...Sm).

In the operation of the display device thus constructed, according to a timing chart shown in Fig. 2, a block BK1 is first selected and scanning lines C11 to C14 are scanned one after another. Then, instead of a block BK2, a block BK3 is selected and scanning lines C31 to C34 are scanned one after another. Then, the block BK2 is selected. and scanning lines C21 to C24 are scanned one after another. Thereafter, a block BK4 is selected and scanning lines C41 to C44 are scanned one after another. Thus, the blocks are scanned in a regular or irregular skip manner, with the scanning lines within each block being scanned in a non-interlaced manner. By repeating the above scanning pattern, a moving picture or a still picture is displayed on the display unit DPU.

For the sake of simplicity, the scanning signal in Fig. 2 is shown as a simple rectangular waveform. In fact, however, another suitable waveform of the scanning signal may be used depending on the structure of the pixel, etc. Of course, such a scanning signal may include a reset signal component (or clear signal component) for resetting the display state of a pixel once. The scanning signal may also include an auxiliary signal component for stabilizing the electrical or physical characteristics of a pixel without changing the display state of the pixel.

The timing of the scanning signals applied to adjacent scanning lines within a block may be selected so that the falling of a preceding signal and the rising of a subsequent signal occur simultaneously or are spaced apart by a prescribed interval. Alternatively, the two consecutively applied scanning signals may overlap. More specifically, a subsequent scanning line in such a case may receive a reset signal component while a scanning line receives a signal component for display, thus resulting in a high-speed display.

The number of scan lines simultaneously selected within a block does not have to be one, but a plurality of adjacent scanning lines can be selected simultaneously, and such selection can be continued successively for further groups of adjacent scanning lines.

As a more detailed description with reference to the arrangement shown in Fig. 1, two adjacent scanning lines C11 and C12 are first simultaneously selected, i.e., supplied with a scanning signal. Thereafter, scanning lines C13 and C14 are simultaneously selected. Thereafter, a subsequent block BK3 is selected skipping block BK2, and C31 and C32 are simultaneously selected, followed by simultaneous selection of C33 and C34. Such an operation is continued to achieve display of a raster.

In case of simultaneous selection of a plurality of scanning lines as described above, a display can be achieved such that two pixels CELi,j and CELi+1,j on a data signal line form a combined pixel unit. In this case, one pixel, e.g. CELi,j, can be set as a standard pixel and another pixel CELi+1,j as a compensation pixel for effecting display compensation for a possible difference between the display state at the standard pixel and the time display state due to, for example, a change in the ambient temperature. Such a method is suitably applied to a gray-scale display by forming a transparent region and an opaque region within a pixel unit and changing the ratio of the regions.

The pixels used in the present invention may preferably comprise a liquid crystal cell constructed, for example, as a simple matrix display panel, an electroluminescent cell with an electron discharge element, or a liquid crystal cell with a switching element such as a thin-film transistor or an MIM element at each pixel.

A liquid crystal cell is particularly preferred because of its economical manufacturing process, and suitable examples of the liquid crystal may include a twisted nematic liquid crystal and a ferroelectric liquid crystal as described below.

If the display unit (console) is of the transmission type, a light source may be arranged on one of its sides as an illumination device to improve the contrast and brightness.

Furthermore, it is possible to arrange a recording device for recording a display image. The recording can be made on a recording medium such as a magnetic medium, an optical medium, semiconductor memories, paper and plastic sheets, and the recording device required for this may include, for example, a magnetic head, an optical head, a thermal head and an ink jet head.

The display device according to the invention can be preferably used in a display method using a ferroelectric liquid crystal having excellent response and a wide viewing angle, particularly in a gradation (grayscale) display method using a ferroelectric liquid crystal (hereinafter sometimes abbreviated as "FLC").

Graded display methods using the FLC have been disclosed, for example, in U.S. Patent No. 4,712,877 to Okada et al.; U.S. Patent No. 4,747,671 to Takahashi et al., and U.S. Patent No. 4,763,994 to Kaneko et al.

Specifically, such gradated display methods can be representatively classified into (1) a method of dividing a pixel into independently controlled subpixels (dither method), (2) a method of forming a potential gradient within a pixel to divide the pixel into display areas (potential gradient method), (3) a method of applying a unidirectional electric field to a liquid crystal in a monostable state to control the deviation of the liquid crystal molecule long axis depending on the strength of the electric field, and (4) a method of changing the liquid crystal layer thickness within a pixel to change the electric field strength applied to the liquid crystal layer within the pixel, thereby achieving a gradated display.

In such a gradation display system using an FLC, there is a problem that it causes a substantial change in the threshold value according to a temperature change, so that it is difficult to maintain a constant gradation level regardless of a temperature change. To solve the problem, we have proposed a driving scheme which may be called a pixel shift method (two-pulse method) in U.S. Patent Application No. 984,694 filed on December 2, 1992, entitled "Liquid Crystal Display Device". In principle, the driving scheme comprises: (1) line sequential writing starting from a first line to an n-th line, while (2) simultaneously selecting two consecutive scanning lines (L-th and L-th+1) at a selection instant and, at a subsequent selection instant, simultaneously selecting two consecutive scanning lines (L-th+1 and L-th+2) deviating by one line, where L is an integer of 1 ≤ L ≤ n. Of the consecutive L-th and L-th+1 scanning lines, the L-th scanning line represents a scanning line for the temperature temperature compensation of the L-th+1 scanning line. More specifically, when the liquid crystal cell is at a standard temperature, only the L-th+1 scanning line is written, and if the temperature deviates, the L-th line is written. In other words, the display data to be displayed on the L-th+1 scanning line is shifted to the L-th scanning line in accordance with a temperature change. Thus, an undesirable display state of a pixel on one of at least two adjacent scanning lines is compensated by a display state of a pixel on the other scanning line. That is, a synthetic display state of adjacent pixels on a data line and at least two scanning lines is used as a unit for the gradated display. By this measure, an undesirable display state of a pixel in the unit can be compensated by a display state of the remaining pixel in the unit, whereby a normal display can be achieved as a whole.

In order to realize the writing operation described above, the following conditions can be set. (3) The simultaneously selected (at least) two scanning lines are supplied with two scanning signals that are different from each other and are determined to provide continuous threshold values at two pixels formed at the intersections of a data line with two scanning lines. The provision of a "continuous threshold value" is a condition for realizing a uniform data shift between two scanning lines successively written by a line-sequential scan. (4) A pixel having a threshold distribution in terms of transmittance is required.

However, with such a control method, the image data changes its position according to a temperature change, so that it is difficult to completely adjust the image of a frame to Specifically, the pixels on the first scanning line have no scanning line to which the image data is shifted, and the pixels on the n-th scanning line are not subjected to any operation after the image data shift according to a temperature change.

Second, cell-skip scanning cannot be performed since the scanning lines are selected row-sequentially starting from the first row to the n-th row.

The present invention can be preferably used to suppress the flicker possible in the aforementioned stepped driving scheme.

In the following, the invention is explained in more detail based on preferred embodiments.

[First embodiment]

Fig. 3 shows a block diagram of a liquid crystal display device according to a first embodiment of the present invention. Referring to Fig. 3, the display device comprises a liquid crystal display unit (console) 101, a scanning signal application circuit 102, a data signal application circuit 103, a scanning signal control circuit 104, a drive control circuit 105, a data signal control circuit 106, and a graphics controller 107.

Data supplied from the graphics controller 107 via the drive control circuit 105 are input to the scanning signal control circuit 104 and the data signal control circuit 106, where they are converted into address data and display data, respectively. The scanning signal application circuit 102 generates scanning signals in accordance with the address data, which are supplied to the scanning electrodes in the liquid crystal display unit 101. Furthermore, the data signal application circuit 103 generates data signals corresponding to corresponding to the display data supplied to the data electrodes in the liquid crystal display unit 101.

Fig. 4 shows an enlarged partial view of the liquid crystal display unit 101 with scanning electrodes C1 to C6 ... and data electrodes S1 to S6 ... arranged so as to form an electrode matrix and pixels each forming a display unit, for example with a pixel P22 formed at the intersection of a scanning electrode C2 and a data electrode S2. Fig. 5 shows a partial sectional view of the display unit taken along line A-A in Fig. 4. Referring to Fig. 5, the liquid crystal display unit 101 includes glass substrates 302 and 304 and a ferroelectric liquid crystal 303 arranged between the substrates 302 and 304 and in a cell structure forming a cell gap defined by a spacer 306. Furthermore, an analyzer 301 and a polarizer 305 are arranged as crossed nicols so that the cell structure is located therebetween.

In detail, the cell structure shown in Figs. 4 and 5 comprises a pair of substrates 302 and 304 made of glass plates or plastic plates which are kept at a predetermined distance by spacers 306 and sealed with an adhesive to form a cell structure filled with a liquid crystal. On the substrate 304, there is further formed an electrode group (e.g. an electrode group for applying scanning voltages of a matrix electrode structure) having a plurality of transparent electrodes C1 to C6 ... in a predetermined pattern, e.g. a stripe pattern. On the substrate 302, there is formed another electrode group (e.g. an electrode group for applying data voltages of the matrix electrode structure) having a plurality of transparent electrodes S1 to S6 ... crossing the transparent electrodes C1 to C6.

In the device, the alignment control layers (not shown) may be formed directly above the transparent electrodes C1 to C6 and S1 to S6 on the substrates 304 and 302, respectively. In another embodiment, short-circuit prevention insulating films (not shown) and alignment control layers (not shown) may be disposed on the substrates 304 and 302, respectively.

Examples of the material constituting the alignment control layers include inorganic insulating materials such as silicon monoxide, silicon dioxide, alumina, zirconia, magnesium fluoride, cerium oxide, cerium fluoride, silicon nitride, silicon carbide and boron nitride; and organic insulating materials such as polyvinyl alcohol, polyimide, polyamideimide, polyesterimide, polyparaxylylene, polyester, polycarbonate, polyvinyl acetal, polyvinyl chloride, polyamide, polystyrene, cellulose resin, melamine resin, urea resin and acrylic resin. The aforementioned alignment (control) layer made of an insulating material can also be used as an insulating film for short-circuit prevention.

The alignment control layers made of inorganic insulating material or organic insulating material may have a uniaxial alignment axis by rubbing the surface of the layer after its formation in one direction with velvet, cloth or paper to form the uniaxial alignment axis.

Furthermore, the insulating films for short-circuit prevention may be formed with a thickness of 20 nm (200 Å) or more, preferably 50 nm (500 Å) or more, of an inorganic insulating material such as SiO₂, TiO₂, Al₂O₃, Si₃N₄ and BaTiO₃. The film formation may be carried out, for example, by sputtering, ion beam evaporation or calcining of an organic titanium component, an organic silane component or an organic aluminum component. The or For example, the organic titanium component may be an alkyl (methyl, ethyl, propyl, butyl, etc.) titanate component, and the organic silane component may be an ordinary silane coupling agent. If the thickness of the short-circuit prevention insulating film is less than 20 nm (200 Å), effective short-circuit prevention cannot be achieved. On the other hand, if the thickness is greater than 500 nm (5000 Å), the effective voltage applied to the liquid crystal layer is significantly reduced, so that the thickness can be set to 500 nm (5000 Å) or less, preferably 200 nm (2000 Å) or less.

The liquid crystal material suitable for the present invention is a chiral smectic liquid crystal exhibiting ferroelectricity. Specifically, liquid crystals in a chiral smectic C phase (SmC*), a chiral smectic G phase (SmG*), a chiral smectic F phase (SmF*), a chiral smectic I phase (SmI*) or a chiral smectic H phase (SmH*) can be used.

Details of ferroelectric liquid crystals are disclosed, for example, in LE JOURNAL DE PHYSIQUE LETTERS, 36 (L-69) 1975, "Ferroelectric Liquid Crystals"; Applied Physics Letters 36 11, 1980, "Submicro Second Bi-stable Electrooptic Switching in Liquid Crystals"; Kotai Butsuri (Solid-State Physics) 16 (141) 1981, "Ekisho (Liquid Crystals)"; U.S. Patent Nos. 4,561,726; 4,589,996; 4,592,858; 4,596,667; 4,613,209; 4,614,609; 4,622,165, etc. The chiral smectic liquid crystals disclosed in these references can be used in the present invention.

Other specific examples of the ferroelectric liquid crystal may include decyloxybenzylidene-p'-amino-2-methylbutylcinnamate (DOBAMBC), hexyloxybenzylidene-p'-amino-2- chloropropyl cinnamate (HOBACPC), and 4-O-(2-methyl)butylresorcylidene-4'-octylaniline (MBRA 8).

[First embodiment]

With respect to the embodiment of the liquid crystal display device shown in Figs. 3 to 5, a frame frequency of 1/(512 x 96 µs) = 20.3 Hz is obtained when the selection time for a scanning electrode is 96 µs. In this display device, the flicker caused by the scanning drive is suppressed at a raster frequency of 40 Hz or more, so that an image is designed to be formed by a double vertical scan.

According to Fig. 6, the entire area consisting of 512 lines (scanning electrodes) is divided into 16 blocks B1 to B16. In a first field, the blocks B1, B3, B5, B7, B9, B11, B13 and B15 are selected and in a second field, the blocks B2, B4, B6, B8, B10, B12, B14 and B16. In each block, a non-interlaced scan is carried out. As an entire scanning sequence, the 1st, 2nd, 3rd, ..., 31st, 32nd, 65th, 66th ..., 96th, 129th, 130th, ..., 160th, ..., 449th, 450th, ..., and 480th scanning electrodes are sequentially selected to complete the first vertical scan, and thereafter, the 33rd, 34th, 35th, ..., 63rd, 64th, 97th, 98th, ..., 128th, 161st, 162nd, ..., 192nd, ..., 481st, 482nd, ..., and 512th scanning electrodes are sequentially selected to complete the second vertical scan, thereby writing an entire image.

To implement the above method, a memory 500 as shown in Fig. 7 is provided in the scanning signal control circuit 104. Referring to Fig. 7, the memory 500 includes a scanning address memory M1, an address increment memory M2, a line number counter memory M3, a block number counter memory, and address table memories MT (1) to MT (16). As fixed values, the number 1 is set in the address increment memory M2, and the 16 numbers 1, 65, 129, 193, 257, 321, 385, 449, 33, 97, 161, 225, 289, 353, 417 and 481 are set in the address table memories MT(1) to MT(16) as the respective initial scanning address (position ranks of the initial scanning electrodes) among all the scanning electrodes of the first vertical scan and the second vertical scan in this order. Here, the content of the scanning address memory means the scanning address. The content of the address increment memory M2 means the scanning electrodes covered by one scanning operation ("1" means that each line is scanned in a non-interlaced manner). The content of the line number counter memory has the meaning of the scanning repetitions carried out at that time in each block. The content of the block number counter memory M4 has the meaning of the ordinal number of the block for which the scanning is carried out at that time during the entire first vertical scan and second vertical scan. The contents of the address table memories MT(1) to MT(16) have the meaning of the scanning addresses from which the scanning is started for the respective blocks.

Fig. 8 shows a flow chart of an algorithm for determining the scanning addresses. In step 1, the number "1" is set in the block number counter memory M4 for initialization. In step 2, the number in the block number counter memory M4 is checked to see if it exceeds 16 (M4 > 16) to judge whether all the blocks have been written. In step 3, the line number counter memory is initialized for scanning in each block. First, a number "1" for the first scan in the block is set in the line number counter memory M3. Thereafter, the number of the block is checked according to the content of the block number counter memory to determine the initial scanning address in the block concerned, and the initial scanning address in the block is according to the content of the corresponding address table memory MT to set the initial scanning address in the scanning address memory M1. In step 4, a number "1" is added to the block number counter memory M4. In step 5, it is checked whether the content of the line number counter memory M3 exceeds 32 (M3 > 32) to check whether the writing to the block is completed. In step 6, the scanning address is transferred. In step 7, the content of the address increment memory M2 is added to the content of the scanning address memory M1, and a number "1" is added to the line number counter memory M3.

Thus, according to the algorithm shown in Fig. 8, the content of the address table memory MT is set in the scanning address memory M1 based on the content of the block number counter memory M4, and this operation is repeated 16 times, each time the steps of sending the scanning address to the scanning signal application circuit and incrementing the content of the scanning line address memory by "1" (the content of the address increment memory M2) are repeated 32 times. After the scanning address is transferred 16 x 32 times, the operation is returned to the beginning. Before the first transfer of the scanning address, a number "1" is set in the scanning address memory M1, the line number counter memory M3, and the block number counter memory M4.

If, for example, an image according to Fig. 4 is now viewed, where the pixels of the odd-numbered scanning electrodes, i.e., 1st, 3rd, 5th, ... to 511th line, are black, and the pixels of the even-numbered scanning electrodes, i.e., 2nd, 4th, 6th, ... to 512th line, are alternately black, white, black, white, ..., a pixel P22 receives a black signal and a white signal for each line. The repetition frequency is 1/(1 · 2 · 96 us) = 5208 Hz (> 40 Hz), so that no flickering occurs.

On the other hand, when a similar image is displayed according to the known 2-line scanning scheme, the 1st, 3rd, 5th, ... to 511th lines are selected sequentially to complete the first vertical scan, and then the 2nd, 4th, ... to 512th lines are selected to complete the second vertical scan, thereby writing an entire image. In this case, the pixel P22 continuously receives the black signal for 256 repetitions and then continuously receives the white signal for 256 repetitions, resulting in a signal repetition frequency of 1/(256 · 2 · 96 us) = 20.3 Hz (< 40 Hz), whereby flickering is noticeable.

If the 8-interlace scanning scheme is also used to avoid flicker, whereby the flicker is removed due to an increased frequency, the recognizability of a moving image is noticeably affected, since an image is formed by scanning every 8th line in comparison to the non-interlaced scanning.

[Second embodiment]

In order not to lower the raster frequency below 40 Hz, it is also possible to select the blocks arbitrarily to write an entire image. The device used in the first embodiment can, for example, be controlled by selecting the blocks in the order B1, B10, B3, B8, B13, B2, B15, B12, B5, B14, B7, B16, B9, B6, B11 and B4 to achieve a similar effect.

In this case, the 16 numbers 1, 289, 65, 225, 385, 33, 449, 353, 129, 417, 193, 481, 257, 161, 321 and 97 are set in the corresponding address table memories MT(1) to MT(16) as shown in Fig. 9.

[Third embodiment]

In this embodiment, a liquid crystal display device consists of 1024 scanning electrodes and 1280 data electrodes arranged to form an electrode matrix.

If the selection time for a scanning electrode is 96 us, the frame frequency is 1/(1024 · 96 us) = 10.2 Hz. To provide a raster frequency of 40 Hz or higher, an overall image is designed to be formed by four vertical scanning operations.

As shown in Fig. 10, the 1024 scanning lines constituting an entire display area are divided into 32 blocks B1 to B32 each having 32 lines. In a first grid, the blocks B1, B5, B9, B13, B17, B21, B25 and B29 are selected in that order. Further, the blocks B3, B7, B11, B15, B19, B23, B27 and B31 are selected in a second grid; the blocks B2, B6, B10, B14, B18, B22, B26 and B30 in a third grid; and the blocks B4, B8, B12, B16, B20, B24, B28 and B30 in a fourth grid. And within each grid, the scanning lines are subjected to non-interlaced scanning.

As a total sequence, the 1st, 2nd, 3rd, ..., 31st, 32nd, 129th, 130th, ..., 160th, 257th, 258th, ... 288th, ..., 897th, 898th, ..., and 928th scanning lines are selected to terminate the first vertical scan; the 65th, 66th, 67th, 95th, 96th, 193rd, 194th, ..., 224th, 321st, 322nd, ..., 352nd, 961st, 962nd, ..., and 992nd scanning lines are selected to terminate the second vertical scan; the 33rd, 34th, 35th, 63rd, 64th, 161st, 162nd, ..., 192nd, 289th, 290th, ..., 320th, ..., 929th, 930th, ..., and 960th scanning lines to terminate the third vertical scan; and thereafter the 97th, 98th, 99th, ..., 127th, 128th, 225th, 226th, ..., 256th, 353rd, 354th, ..., 384th, 993rd, 994th, ..., and 1024th scanning lines to complete the fourth vertical scan, thereby writing an entire image.

To implement the above-mentioned method, a memory 800 according to Fig. 11 is provided in the scanning signal control circuit. As fixed values, a number 1 is set in the address increment memory M2, and 32 numbers 1, 129, 257, 385, 513, 641, 769, 897, 65, 193, 321, 449, 577, 705, 833, 961, 33, 161, 289, 417, 545, 673, 801, 929, 97, 225, 353, 481, 609, 737, 865 and 993 are set in the address table memories MT(1) to MT(32) respectively as the initial scanning addresses from all the scanning lines for the first, second, third and fourth vertical scanning.

The sampling address is formed according to the same algorithm as shown in Fig. 8, except that the number of blocks for judging the completion of writing to all blocks in step 2 in Fig. 8 is changed to M4 > 32.

For example, if an image shown in Fig. 4 is used, where the pixels on the odd-numbered scanning electrodes, i.e. the 1st, 3rd, 5th, ... to 1023rd line, are black, and the pixels on the even-numbered scanning electrodes, i.e. the 2nd, 4th, 6th, ..., 1024th line, are white, a pixel P22 receives alternately a black signal and a white signal for one line at a time. The repetition frequency is 1/(1 · 2 · 96 us) = 5208 Hz (> 40 Hz).

On the other hand, when a similar image is displayed according to a known 4-interlace scanning scheme, the 1st, 5th, 9th, ..., and 1021st scanning lines are selected to terminate the first vertical scan; the 2nd, 6th, 10th, ..., and 1022nd scanning lines to terminate the second vertical scan; the 3rd, 7th, 11th, ..., and 1023rd scanning lines to terminate the third vertical scan; and thereafter the 4th, 8th, 12th, ... and 1024th scanning lines to complete the fourth vertical scan, thereby writing an entire image. In this case, the pixel P22 continuously receives the black signal for 256 repetitions, then the white signal for 256 repetitions, then the black signal for 256 repetitions, and then the black signal for 256 repetitions, so that a repetition frequency of 1/(256 · 2 · 96 us) = 20.3 Hz (< 40 Hz) is obtained, whereby flickering is noticeable.

Furthermore, if a 16-interlace scanning scheme is used to avoid flicker, whereby flicker is removed due to an increased frequency, the recognizability of a moving picture is noticeably impaired because an image is formed by scanning every 16th line compared to the non-interlace scanning.

[Fourth embodiment]

In order not to lower the raster frequency below 40 Hz, it is possible to select the blocks arbitrarily to thereby write an entire image. The device of the third embodiment can, for example, be controlled to select the blocks in the order B1, B18, B27, B12, B5, B22, B31, B8, B17, B2, B23, B20, B29, B14, B11, B32, B13, B26, B3, B16, B9, B30, B19, B4, B25, B10, B7, B28, B21, B6, B15 and B24 to achieve a similar effect. In this case, the 32 addresses 1, 545, 833, 353, 129, 673, 961, 225, 513, 33, 705, 609, 897, 417, 321, 993, 385, 801, 65, 481, 257, 929, 577, 97, 769, 289, 193, 865, 641, 161, 449 and 737 are set in the address table memories MT(1) to MT(32) respectively, as shown in Fig. 12.

The results of the actual operation of the display device according to the above-mentioned first and second embodiments are shown in Table 1 below. with those of the 2-interlace scanning scheme and the 8-interlace scanning scheme also described above. Table 1

Similarly, the results of the actual operation of the display device according to the aforementioned third and fourth embodiments are summarized in Table 2 below together with those of the 4-interlace scanning scheme and the 16-interlace scanning scheme also described above. Table 2

Fig. 13 shows a group of drive signal waveforms used to evaluate the above embodiments, and Fig. 14 is a timing diagram of the correlation between signal transmission and drive for driving a device according to Fig. 3.

In each of the above embodiments, each block is designed to have 32 scanning electrodes. This is because a character, an icon and a mouse mark have a height of 32 dots or less and no flicker caused by the scanning drive is caused by 32 lines. If the number of scanning electrodes in a block is increased, the probability of occurrence of a block boundary in a display pattern such as a character is reduced, thereby providing good recognizability, but the tendency to flicker due to the scanning drive increases inversely. If the number of scanning electrodes in a block is reduced, the probability of occurrence of Occurrence of a block boundary in a display pattern such as a character. Particularly, in the case of a number of scanning electrodes in a block being less than the number of dots in the height direction of a display pattern such as a character, a block boundary always appears in a character display and scanning is skipped thereat, so that perceptibility is significantly impaired.

For the above reason, it is preferable that the number of scanning electrodes in one block (i) is not so large as to cause flickering due to scanning drive and (ii) is sufficiently large as to be greater than or equal to the number of dots in the height direction of a display pattern such as a character, an icon or a mouse mark. As long as the above conditions (i) and (ii) are satisfied, a larger number results in better perceptibility.

As described above, in the present invention, the scanning lines are divided into a plurality of blocks each having a plurality of adjacent scanning lines, the blocks being sequentially selected with a distance of at least one block between sequentially selected blocks, while the adjacent scanning lines within each block are sequentially selected. As a result, a decrease in the frequency of alternating black display and white display data signals for displaying a repeated image is prevented to prevent flickering while maintaining good recognizability of a moving image. Thus, a display device with improved image quality is provided.

Claims (10)

1. Display device, with: a matrix of a group of scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) and a group of data signal lines (S1 ... Sm) which cross the scanning lines (C11, ... C14, C21 ... C24, C41 ... C44), pixels (CEL) each formed at an intersection of the scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) and the data signal lines (S1 ... Sm), and a drive device (104 to 106) for supplying drive signals to the matrix to effect a display at the pixels (CEL), wherein the scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) are divided into at least four blocks (BK1, BK2, ..., BK4) each having a plurality of adjacent scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44), characterized in that the control device (104 to 106) includes a scanning device (104) for sequentially selecting the at least four blocks (BK1, BK2, ..., BK4) with scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44), so that the blocks (BK1, BK2, ..., BK4) are selected sequentially with a distance of at least one block between successively selected blocks and the adjacent scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) within each selected block are selected successively. 2. Device according to claim 1, wherein the pixels (CEL) comprise a liquid crystal. 3. Device according to claim 1, wherein the pixels (CEL) comprise a ferroelectric liquid crystal. 4. Device according to claim 1, wherein the pixels (CEL) have a liquid crystal and are each equipped with a switching element. 5. The device according to claim 1, wherein each of the at least four blocks (BK1, BK2, ..., BK4) contains the same number of scan lines (C11, ... C14, C21 ... C24, ..., C41 ... C44). 6. Device according to claim 1, wherein the at least four blocks (BK1, BK2, ..., BK4) are selected in an irregular sequence. 7. Device according to claim 1, further comprising an illumination device for illuminating the pixels (CEL). 8. The apparatus of claim 1, further comprising a graphics controller (107) for controlling a display image. 9. The apparatus of claim 1, further comprising a recording device for recording a display image. 10. Notification procedure, with: Providing a display device comprising a matrix of a group of scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) and a group of data signal lines (S1 ... Sm) crossing the scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44), pixels (CEL) each formed at an intersection of the scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) and the data signal line (S1 ... Sm), and a drive device (104 to 106) for supplying drive signals to the matrix to effect a display at the pixels (CEL); Dividing the scanning lines ((C11, ... C14, C21 ... C24, ..., C41 ... C44) into at least four blocks (BK1, BK2, ..., BK4) each having a plurality of adjacent scanning lines (C11, ... C14, C21 ... C24, ..., C41 ... C44); characterized by further comprising the step of sequentially selecting the at least four blocks (BK1, BK2, ..., BK4) of scan lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) such that the blocks (BK1, BK2, ..., BK4) are selected sequentially with a spacing of at least one block between successively selected blocks, and the adjacent scan lines (C11, ... C14, C21 ... C24, ..., C41 ... C44) within each selected block are selected sequentially.