US6336180B1
(en)
|
1997-04-30 |
2002-01-01 |
Canon Kabushiki Kaisha |
Method, apparatus and system for managing virtual memory with virtual-physical mapping
|
US5640534A
(en)
*
|
1994-10-05 |
1997-06-17 |
International Business Machines Corporation |
Method and system for concurrent access in a data cache array utilizing multiple match line selection paths
|
US6223260B1
(en)
*
|
1996-01-25 |
2001-04-24 |
Unisys Corporation |
Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
|
US5822758A
(en)
*
|
1996-09-09 |
1998-10-13 |
International Business Machines Corporation |
Method and system for high performance dynamic and user programmable cache arbitration
|
US5893142A
(en)
*
|
1996-11-14 |
1999-04-06 |
Motorola Inc. |
Data processing system having a cache and method therefor
|
AUPO648397A0
(en)
|
1997-04-30 |
1997-05-22 |
Canon Information Systems Research Australia Pty Ltd |
Improvements in multiprocessor architecture operation
|
AUPO647997A0
(en)
|
1997-04-30 |
1997-05-22 |
Canon Information Systems Research Australia Pty Ltd |
Memory controller architecture
|
US6707463B1
(en)
|
1997-04-30 |
2004-03-16 |
Canon Kabushiki Kaisha |
Data normalization technique
|
US6674536B2
(en)
|
1997-04-30 |
2004-01-06 |
Canon Kabushiki Kaisha |
Multi-instruction stream processor
|
US6289138B1
(en)
|
1997-04-30 |
2001-09-11 |
Canon Kabushiki Kaisha |
General image processor
|
US6414687B1
(en)
|
1997-04-30 |
2002-07-02 |
Canon Kabushiki Kaisha |
Register setting-micro programming system
|
US6272257B1
(en)
|
1997-04-30 |
2001-08-07 |
Canon Kabushiki Kaisha |
Decoder of variable length codes
|
KR100255510B1
(ko)
*
|
1997-05-09 |
2000-05-01 |
김영환 |
원포트램셀구조로이루어진캐시데이터램
|
US6065077A
(en)
|
1997-12-07 |
2000-05-16 |
Hotrail, Inc. |
Apparatus and method for a cache coherent shared memory multiprocessing system
|
US6633945B1
(en)
|
1997-12-07 |
2003-10-14 |
Conexant Systems, Inc. |
Fully connected cache coherent multiprocessing systems
|
US6418537B1
(en)
|
1997-12-07 |
2002-07-09 |
Conexant Systems, Inc. |
Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL
|
US6516442B1
(en)
|
1997-12-07 |
2003-02-04 |
Conexant Systems, Inc. |
Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
|
US6292705B1
(en)
|
1998-09-29 |
2001-09-18 |
Conexant Systems, Inc. |
Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
|
US6341337B1
(en)
|
1998-01-30 |
2002-01-22 |
Sun Microsystems, Inc. |
Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic
|
US7035981B1
(en)
*
|
1998-12-22 |
2006-04-25 |
Hewlett-Packard Development Company, L.P. |
Asynchronous input/output cache having reduced latency
|
US6469988B1
(en)
|
1999-07-08 |
2002-10-22 |
Conexant Systems, Inc. |
Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals
|
GB2417111B
(en)
*
|
2002-04-22 |
2006-08-16 |
Micron Technology Inc |
Providing a register file memory with local addressing in a SIMD parallel processor
|
KR100522431B1
(ko)
*
|
2003-04-30 |
2005-10-20 |
주식회사 하이닉스반도체 |
리프레쉬 동작이 향상된 고속 데이터 억세스를 위한반도체 메모리 장치
|
KR100543932B1
(ko)
*
|
2003-04-30 |
2006-01-23 |
주식회사 하이닉스반도체 |
초기화 동작시간이 감소된 태그블럭을 구비하는 반도체 메모리 장치 및 그의 구동방법
|
WO2006056900A1
(en)
*
|
2004-11-24 |
2006-06-01 |
Koninklijke Philips Electronics N.V. |
Coherent caching of local memory data
|
CN103646009B
(zh)
|
2006-04-12 |
2016-08-17 |
索夫特机械公司 |
对载明并行和依赖运算的指令矩阵进行处理的装置和方法
|
CN107368285B
(zh)
|
2006-11-14 |
2020-10-09 |
英特尔公司 |
多线程架构
|
US8208418B1
(en)
*
|
2009-01-16 |
2012-06-26 |
Extreme Networks, Inc. |
Methods, systems, and computer readable media for conserving multicast port list resources in an internet protocol (IP) packet forwarding device
|
US8856448B2
(en)
*
|
2009-02-19 |
2014-10-07 |
Qualcomm Incorporated |
Methods and apparatus for low intrusion snoop invalidation
|
US10228949B2
(en)
|
2010-09-17 |
2019-03-12 |
Intel Corporation |
Single cycle multi-branch prediction including shadow cache for early far branch prediction
|
US9008091B1
(en)
|
2010-11-19 |
2015-04-14 |
Extreme Networks, Inc. |
Methods, systems, and computer readable media for improved multicast scaling through policy based redirection
|
EP2689326B1
(de)
|
2011-03-25 |
2022-11-16 |
Intel Corporation |
Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
|
KR101620676B1
(ko)
|
2011-03-25 |
2016-05-23 |
소프트 머신즈, 인크. |
분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
|
WO2012135031A2
(en)
|
2011-03-25 |
2012-10-04 |
Soft Machines, Inc. |
Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
|
EP2710480B1
(de)
|
2011-05-20 |
2018-06-20 |
Intel Corporation |
Verbindungsstruktur zur unterstützung der ausführung von instruktionssequenzen durch mehrere maschinen
|
US9940134B2
(en)
|
2011-05-20 |
2018-04-10 |
Intel Corporation |
Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
|
KR101703401B1
(ko)
|
2011-11-22 |
2017-02-06 |
소프트 머신즈, 인크. |
다중 엔진 마이크로프로세서용 가속 코드 최적화기
|
KR101703400B1
(ko)
|
2011-11-22 |
2017-02-06 |
소프트 머신즈, 인크. |
마이크로프로세서 가속 코드 최적화기
|
US8930674B2
(en)
|
2012-03-07 |
2015-01-06 |
Soft Machines, Inc. |
Systems and methods for accessing a unified translation lookaside buffer
|
US9916253B2
(en)
|
2012-07-30 |
2018-03-13 |
Intel Corporation |
Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
|
US9710399B2
(en)
|
2012-07-30 |
2017-07-18 |
Intel Corporation |
Systems and methods for flushing a cache with modified data
|
WO2014022115A1
(en)
*
|
2012-07-30 |
2014-02-06 |
Soft Machines, Inc. |
Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
|
US9740612B2
(en)
|
2012-07-30 |
2017-08-22 |
Intel Corporation |
Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
|
US9430410B2
(en)
|
2012-07-30 |
2016-08-30 |
Soft Machines, Inc. |
Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
|
US9229873B2
(en)
|
2012-07-30 |
2016-01-05 |
Soft Machines, Inc. |
Systems and methods for supporting a plurality of load and store accesses of a cache
|
US9678882B2
(en)
|
2012-10-11 |
2017-06-13 |
Intel Corporation |
Systems and methods for non-blocking implementation of cache flush instructions
|
KR102083390B1
(ko)
|
2013-03-15 |
2020-03-02 |
인텔 코포레이션 |
네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
|
WO2014150991A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for implementing a reduced size register view data structure in a microprocessor
|
KR102063656B1
(ko)
|
2013-03-15 |
2020-01-09 |
소프트 머신즈, 인크. |
블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
|
US9904625B2
(en)
|
2013-03-15 |
2018-02-27 |
Intel Corporation |
Methods, systems and apparatus for predicting the way of a set associative cache
|
US9886279B2
(en)
|
2013-03-15 |
2018-02-06 |
Intel Corporation |
Method for populating and instruction view data structure by using register template snapshots
|
WO2014150971A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for dependency broadcasting through a block organized source view data structure
|
US9891924B2
(en)
|
2013-03-15 |
2018-02-13 |
Intel Corporation |
Method for implementing a reduced size register view data structure in a microprocessor
|
US10140138B2
(en)
|
2013-03-15 |
2018-11-27 |
Intel Corporation |
Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
|
US10275255B2
(en)
|
2013-03-15 |
2019-04-30 |
Intel Corporation |
Method for dependency broadcasting through a source organized source view data structure
|
US9811342B2
(en)
|
2013-03-15 |
2017-11-07 |
Intel Corporation |
Method for performing dual dispatch of blocks and half blocks
|
WO2014150806A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for populating register view data structure by using register template snapshots
|
US9569216B2
(en)
|
2013-03-15 |
2017-02-14 |
Soft Machines, Inc. |
Method for populating a source view data structure by using register template snapshots
|
US9454482B2
(en)
*
|
2013-06-27 |
2016-09-27 |
Apple Inc. |
Duplicate tag structure employing single-port tag RAM and dual-port state RAM
|
US20150067246A1
(en)
*
|
2013-08-29 |
2015-03-05 |
Apple Inc |
Coherence processing employing black box duplicate tags
|
US10565121B2
(en)
*
|
2016-12-16 |
2020-02-18 |
Alibaba Group Holding Limited |
Method and apparatus for reducing read/write contention to a cache
|