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DE69224571D1 - Mehrprozessorrechnersystem - Google Patents

Mehrprozessorrechnersystem

Info

Publication number
DE69224571D1
DE69224571D1 DE69224571T DE69224571T DE69224571D1 DE 69224571 D1 DE69224571 D1 DE 69224571D1 DE 69224571 T DE69224571 T DE 69224571T DE 69224571 T DE69224571 T DE 69224571T DE 69224571 D1 DE69224571 D1 DE 69224571D1
Authority
DE
Germany
Prior art keywords
computer system
multiprocessor computer
multiprocessor
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69224571T
Other languages
English (en)
Other versions
DE69224571T2 (de
Inventor
Thomas F Heil
Craig A Walrath
Jimmy D Pike
Edward A Mcdonald
Arthur F Cochcroft
P Chris Raeuber
Daniel C Robbins
Gene F Young
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Publication of DE69224571D1 publication Critical patent/DE69224571D1/de
Application granted granted Critical
Publication of DE69224571T2 publication Critical patent/DE69224571T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
DE69224571T 1991-09-16 1992-09-15 Mehrprozessorrechnersystem Expired - Lifetime DE69224571T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/760,786 US5359715A (en) 1991-09-16 1991-09-16 Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces

Publications (2)

Publication Number Publication Date
DE69224571D1 true DE69224571D1 (de) 1998-04-09
DE69224571T2 DE69224571T2 (de) 1998-10-01

Family

ID=25060194

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224571T Expired - Lifetime DE69224571T2 (de) 1991-09-16 1992-09-15 Mehrprozessorrechnersystem

Country Status (4)

Country Link
US (1) US5359715A (de)
EP (1) EP0533430B1 (de)
JP (1) JP3765586B2 (de)
DE (1) DE69224571T2 (de)

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US5506964A (en) * 1992-04-16 1996-04-09 International Business Machines Corporation System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system
JP2531903B2 (ja) * 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
US5509127A (en) * 1992-12-04 1996-04-16 Unisys Corporation Transmission logic apparatus for dual bus network
CA2109043A1 (en) * 1993-01-29 1994-07-30 Charles R. Moore System and method for transferring data between multiple buses
US5493655A (en) * 1993-02-20 1996-02-20 Acer Incorporated Method and apparatus for upgrading a data processing system from a single processor system to a multiprocessor system
US5682551A (en) * 1993-03-02 1997-10-28 Digital Equipment Corporation System for checking the acceptance of I/O request to an interface using software visible instruction which provides a status signal and performs operations in response thereto
US5542055A (en) * 1993-05-28 1996-07-30 International Business Machines Corp. System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
US5799161A (en) * 1993-06-25 1998-08-25 Intel Corporation Method and apparatus for concurrent data routing
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US5555430A (en) * 1994-05-31 1996-09-10 Advanced Micro Devices Interrupt control architecture for symmetrical multiprocessing system
CN1104688C (zh) * 1994-06-28 2003-04-02 英特尔公司 Pci到isa中断协议转换器及选择机制
US5781774A (en) * 1994-06-29 1998-07-14 Intel Corporation Processor having operating modes for an upgradeable multiprocessor computer system
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US5619728A (en) * 1994-10-20 1997-04-08 Dell Usa, L.P. Decoupled DMA transfer list storage technique for a peripheral resource controller
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5621902A (en) * 1994-11-30 1997-04-15 International Business Machines Corporation Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller
US5594873A (en) * 1994-12-08 1997-01-14 Dell Usa, L.P. System and method for identifying expansion devices in a computer system
KR100255551B1 (ko) * 1994-12-08 2000-05-01 피터 엔. 데트킨 프로세서가전용버스또는공유버스를통해외부구성요소를액세스할수있도록해주는방법및장치
US5835733A (en) * 1994-12-22 1998-11-10 Texas Instruments Incorporated Method and apparatus for implementing a single DMA controller to perform DMA operations for devices on multiple buses in docking stations, notebook and desktop computer system
US5640520A (en) * 1995-05-01 1997-06-17 Intel Corporation Mechanism for supporting out-of-order service of bus requests with in-order only requesters devices
US5793996A (en) * 1995-05-03 1998-08-11 Apple Computer, Inc. Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US5784614A (en) * 1995-07-27 1998-07-21 Ncr Corporation Cache affinity scheduling method for multi-processor nodes in a split transaction bus architecture
US5812800A (en) * 1995-09-11 1998-09-22 Advanced Micro Devices, Inc. Computer system which includes a local expansion bus and a dedicated real-time bus and including a multimedia memory for increased multi-media performance
US5850555A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices, Inc. System and method for validating interrupts before presentation to a CPU
US5894578A (en) * 1995-12-19 1999-04-13 Advanced Micro Devices, Inc. System and method for using random access memory in a programmable interrupt controller
US5850558A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices System and method for referencing interrupt request information in a programmable interrupt controller
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
KR100243100B1 (ko) * 1997-08-12 2000-02-01 정선종 다수의 주프로세서 및 보조 프로세서를 갖는 프로세서의구조 및 보조 프로세서 공유 방법
US6199131B1 (en) * 1997-12-22 2001-03-06 Compaq Computer Corporation Computer system employing optimized delayed transaction arbitration technique
US6070218A (en) * 1998-01-16 2000-05-30 Lsi Logic Corporation Interrupt capture and hold mechanism
US6338090B1 (en) * 1998-03-27 2002-01-08 International Business Machines Corporation Method and apparatus for selectively using input/output buffers as a retransmit vehicle in an information handling system
US6098117A (en) * 1998-04-20 2000-08-01 National Instruments Corporation System and method for controlling access to memory configured within an I/O module in a distributed I/O system
US6272618B1 (en) 1999-03-25 2001-08-07 Dell Usa, L.P. System and method for handling interrupts in a multi-processor computer
US6609169B1 (en) 1999-06-14 2003-08-19 Jay Powell Solid-state audio-video playback system
US6874044B1 (en) * 2003-09-10 2005-03-29 Supertalent Electronics, Inc. Flash drive/reader with serial-port controller and flash-memory controller mastering a second RAM-buffer bus parallel to a CPU bus
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US6922746B2 (en) * 2002-03-04 2005-07-26 Intel Corporation Data processing system preventing configuration cycles to permit control procedure selection for access to attached devices
US8290924B2 (en) * 2008-08-29 2012-10-16 Empire Technology Development Llc Providing answer to keyword based query from natural owner of information

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US4263649A (en) * 1979-01-05 1981-04-21 Mohawk Data Sciences Corp. Computer system with two busses
WO1983001135A1 (en) * 1981-09-18 1983-03-31 Rovsing As Christian Multiprocessor computer system
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
JPS60157655A (ja) * 1984-01-28 1985-08-17 Fanuc Ltd 補助記憶装置
US4652993A (en) * 1984-04-02 1987-03-24 Sperry Corporation Multiple output port memory storage module
US4868742A (en) * 1984-06-20 1989-09-19 Convex Computer Corporation Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a computer and peripherals is resumed
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
US4797815A (en) * 1985-11-22 1989-01-10 Paradyne Corporation Interleaved synchronous bus access protocol for a shared memory multi-processor system
JP2530829B2 (ja) * 1987-01-16 1996-09-04 株式会社日立製作所 直接メモリアクセス制御装置とマルチマイクロコンピュ―タシステム内におけるデ―タ転送方法
EP0290172A3 (de) * 1987-04-30 1991-01-16 Advanced Micro Devices, Inc. Zweirichtungsfifo mit variabler Byte-Begrenzung und Datenpfadbreitenänderung
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
JP2834122B2 (ja) * 1987-07-08 1998-12-09 株式会社日立製作所 制御装置
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US4920486A (en) * 1987-11-23 1990-04-24 Digital Equipment Corporation Distributed arbitration apparatus and method for shared bus
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US5001625A (en) * 1988-03-24 1991-03-19 Gould Inc. Bus structure for overlapped data transfer
US5081576A (en) * 1988-03-24 1992-01-14 Encore Computer U.S., Inc. Advance polling bus arbiter for use in multiple bus system
US5138703A (en) * 1988-03-31 1992-08-11 Kabushiki Kaisha Toshiba Method of and apparatus for expanding system bus
US4961140A (en) * 1988-06-29 1990-10-02 International Business Machines Corporation Apparatus and method for extending a parallel synchronous data and message bus
US4912630A (en) * 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control
JPH02109153A (ja) * 1988-10-18 1990-04-20 Fujitsu Ltd プロセッサ間データ伝送方式
US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
US4912633A (en) * 1988-10-24 1990-03-27 Ncr Corporation Hierarchical multiple bus computer architecture
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage

Also Published As

Publication number Publication date
US5359715A (en) 1994-10-25
EP0533430A2 (de) 1993-03-24
JPH05210641A (ja) 1993-08-20
EP0533430A3 (en) 1994-05-11
JP3765586B2 (ja) 2006-04-12
DE69224571T2 (de) 1998-10-01
EP0533430B1 (de) 1998-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: INTEL CORP., SANTA CLARA, CALIF., US