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DE69217663D1 - Vorrichtung mit paralleler prozessor matrix - Google Patents

Vorrichtung mit paralleler prozessor matrix

Info

Publication number
DE69217663D1
DE69217663D1 DE69217663T DE69217663T DE69217663D1 DE 69217663 D1 DE69217663 D1 DE 69217663D1 DE 69217663 T DE69217663 T DE 69217663T DE 69217663 T DE69217663 T DE 69217663T DE 69217663 D1 DE69217663 D1 DE 69217663D1
Authority
DE
Germany
Prior art keywords
parallel processor
processor matrix
matrix
parallel
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69217663T
Other languages
English (en)
Other versions
DE69217663T2 (de
Inventor
Thierry Collette
Josef Kaiser
Renaud Schmit
Hassane Es-Safi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of DE69217663D1 publication Critical patent/DE69217663D1/de
Application granted granted Critical
Publication of DE69217663T2 publication Critical patent/DE69217663T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
DE69217663T 1991-07-30 1992-07-30 Vorrichtung mit paralleler prozessor matrix Expired - Lifetime DE69217663T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9109649A FR2680026B1 (fr) 1991-07-30 1991-07-30 Architecture de systeme en tableau de processeurs a structure parallele.
PCT/FR1992/000751 WO1993003441A1 (fr) 1991-07-30 1992-07-30 Architecture de systeme en tableau de processeurs a structure parallele

Publications (2)

Publication Number Publication Date
DE69217663D1 true DE69217663D1 (de) 1997-04-03
DE69217663T2 DE69217663T2 (de) 1997-09-04

Family

ID=9415701

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69217663T Expired - Lifetime DE69217663T2 (de) 1991-07-30 1992-07-30 Vorrichtung mit paralleler prozessor matrix

Country Status (7)

Country Link
US (1) US5504918A (de)
EP (1) EP0597028B1 (de)
JP (1) JPH06509671A (de)
CA (1) CA2113435C (de)
DE (1) DE69217663T2 (de)
FR (1) FR2680026B1 (de)
WO (1) WO1993003441A1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2710993B1 (fr) * 1993-10-04 1995-11-24 Commissariat Energie Atomique Procédé et système d'interconnexion pour la gestion de messages dans un réseau de processeurs à structure parallèle.
FR2742560B1 (fr) * 1995-12-19 1998-01-16 Commissariat Energie Atomique Architecture de systeme en tableau de processeurs a structures paralleles multiples
US5903771A (en) * 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
JPH10232788A (ja) * 1996-12-17 1998-09-02 Fujitsu Ltd 信号処理装置及びソフトウェア
US5907691A (en) * 1997-05-01 1999-05-25 Hewlett-Packard Co. Dual pipelined interconnect
DE19816153B4 (de) * 1997-05-01 2005-06-23 Hewlett-Packard Development Co., L.P., Houston Busverbindungssystem
US5911056A (en) * 1997-05-01 1999-06-08 Hewlett-Packard Co. High speed interconnect bus
GB2367732B (en) * 1997-05-01 2002-09-04 Hewlett Packard Co High speed interconnect bus
US5909562A (en) * 1997-05-01 1999-06-01 Hewlett-Packard Co. Backup FIFO in-line storage
ES2129004B1 (es) * 1997-09-12 2000-01-01 Consejo Superior Investigacion Sistema de ensayos no destructivos de arquitectura segmentada (sendas).
US6513108B1 (en) 1998-06-29 2003-01-28 Cisco Technology, Inc. Programmable processing engine for efficiently processing transient data
JP4718012B2 (ja) * 1998-12-21 2011-07-06 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持
KR100959470B1 (ko) * 2002-03-22 2010-05-25 마이클 에프. 디어링 확장가능한 고성능 3ｄ 그래픽
US7447872B2 (en) * 2002-05-30 2008-11-04 Cisco Technology, Inc. Inter-chip processor control plane communication
WO2004038526A2 (en) 2002-10-22 2004-05-06 Isys Technologies Non-peripherals processing control module having improved heat dissipating properties
WO2004038555A2 (en) * 2002-10-22 2004-05-06 Isys Technologies Robust customizable computer processing system
WO2004038527A2 (en) * 2002-10-22 2004-05-06 Isys Technologies Systems and methods for providing a dynamically modular processing unit
US7515156B2 (en) * 2003-01-08 2009-04-07 Hrl Laboratories, Llc Method and apparatus for parallel speculative rendering of synthetic images
US20050138324A1 (en) * 2003-12-19 2005-06-23 International Business Machines Corporation Processing unit having a dual channel bus architecture
US7007128B2 (en) * 2004-01-07 2006-02-28 International Business Machines Corporation Multiprocessor data processing system having a data routing mechanism regulated through control communication
US7308558B2 (en) * 2004-01-07 2007-12-11 International Business Machines Corporation Multiprocessor data processing system having scalable data interconnect and data routing mechanism
US20060041715A1 (en) * 2004-05-28 2006-02-23 Chrysos George Z Multiprocessor chip having bidirectional ring interconnect
US20060026214A1 (en) * 2004-07-29 2006-02-02 International Business Machines Corporation Switching from synchronous to asynchronous processing
WO2006116044A2 (en) * 2005-04-22 2006-11-02 Altrix Logic, Inc. Array of data processing elements with variable precision interconnect
EP2000922A4 (de) 2006-03-03 2010-09-29 Nec Corp Prozessorarraysystem mit funktion zur datenneuzuweisung zwischen hochgeschwindigkeits-pe
US7990724B2 (en) 2006-12-19 2011-08-02 Juhasz Paul R Mobile motherboard
JP5460156B2 (ja) * 2009-07-14 2014-04-02 キヤノン株式会社 データ処理装置
JP5835942B2 (ja) * 2010-06-25 2015-12-24 キヤノン株式会社 画像処理装置、その制御方法及びプログラム
CN116561047A (zh) 2022-01-28 2023-08-08 阿里巴巴（中国）有限公司 用于芯片间通信的处理系统及通信方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719622A (en) * 1985-03-15 1988-01-12 Wang Laboratories, Inc. System bus means for inter-processor communication
JP2781550B2 (ja) * 1985-05-10 1998-07-30 株式会社日立製作所 並列処理計算機
EP0367182A3 (de) * 1988-10-31 1992-07-22 Bts Broadcast Television Systems Gmbh Digitales Hochgeschwindigkeits-Rechersystem
US5218709A (en) * 1989-12-28 1993-06-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Special purpose parallel computer architecture for real-time control and simulation in robotic applications
US5208900A (en) * 1990-10-22 1993-05-04 Motorola, Inc. Digital neural network computation ring

Also Published As

Publication number Publication date
CA2113435C (fr) 2003-01-14
CA2113435A1 (fr) 1993-02-18
EP0597028B1 (de) 1997-02-26
US5504918A (en) 1996-04-02
EP0597028A1 (de) 1994-05-18
WO1993003441A1 (fr) 1993-02-18
FR2680026B1 (fr) 1996-12-20
JPH06509671A (ja) 1994-10-27
FR2680026A1 (fr) 1993-02-05
DE69217663T2 (de) 1997-09-04

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