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DE69028676D1 - System und Verfahren zur Bestimmung des Verdrahtungsmusters - Google Patents

System und Verfahren zur Bestimmung des Verdrahtungsmusters

Info

Publication number
DE69028676D1
DE69028676D1 DE69028676T DE69028676T DE69028676D1 DE 69028676 D1 DE69028676 D1 DE 69028676D1 DE 69028676 T DE69028676 T DE 69028676T DE 69028676 T DE69028676 T DE 69028676T DE 69028676 D1 DE69028676 D1 DE 69028676D1
Authority
DE
Germany
Prior art keywords
determining
wiring pattern
wiring
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69028676T
Other languages
English (en)
Other versions
DE69028676T2 (de
Inventor
Tatsuya Shindo
Kaoru Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69028676D1 publication Critical patent/DE69028676D1/de
Publication of DE69028676T2 publication Critical patent/DE69028676T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Image Analysis (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69028676T 1989-10-24 1990-10-24 System und Verfahren zur Bestimmung des Verdrahtungsmusters Expired - Fee Related DE69028676T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1276379A JPH03138961A (ja) 1989-10-24 1989-10-24 配線パターン決定方式

Publications (2)

Publication Number Publication Date
DE69028676D1 true DE69028676D1 (de) 1996-10-31
DE69028676T2 DE69028676T2 (de) 1997-04-30

Family

ID=17568606

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69028676T Expired - Fee Related DE69028676T2 (de) 1989-10-24 1990-10-24 System und Verfahren zur Bestimmung des Verdrahtungsmusters

Country Status (4)

Country Link
US (1) US5198987A (de)
EP (1) EP0424908B1 (de)
JP (1) JPH03138961A (de)
DE (1) DE69028676T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04130968A (ja) * 1990-09-21 1992-05-01 Toshiba Corp ニューラルネットワークを用いた配線方式
US5634093A (en) * 1991-01-30 1997-05-27 Kabushiki Kaisha Toshiba Method and CAD system for designing wiring patterns using predetermined rules
US5297053A (en) * 1991-06-04 1994-03-22 Computervision Corporation Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board
US5636129A (en) * 1994-04-20 1997-06-03 Her; One-Hsiow A. Electrical routing through fixed sized module and variable sized channel grids
US6223328B1 (en) * 1996-12-03 2001-04-24 Fujitsu, Limited Wire processing method, wire processing equipment, and recording medium for wire processing program used in designing a large scale integrated circuit
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US6266802B1 (en) 1997-10-27 2001-07-24 International Business Machines Corporation Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm
JP4562625B2 (ja) 2005-09-12 2010-10-13 新光電気工業株式会社 自動配線決定方法、およびこの自動配線決定処理をコンピュータに実行させるためのコンピュータプログラム
EP2032856B1 (de) * 2006-05-24 2018-09-12 Multitrode Pty Ltd. Konfigurationstechniken für pumpstation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199166A (ja) * 1985-03-01 1986-09-03 Nec Corp 配線経路探索装置
US4777606A (en) * 1986-06-05 1988-10-11 Northern Telecom Limited Method for deriving an interconnection route between elements in an interconnection medium
JPS63225869A (ja) * 1986-10-09 1988-09-20 Nec Corp 配線経路探索方式
US5032991A (en) * 1988-12-14 1991-07-16 At&T Ball Laboratories Method for routing conductive paths

Also Published As

Publication number Publication date
EP0424908A2 (de) 1991-05-02
DE69028676T2 (de) 1997-04-30
EP0424908B1 (de) 1996-09-25
EP0424908A3 (en) 1991-10-23
US5198987A (en) 1993-03-30
JPH03138961A (ja) 1991-06-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee