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DE69023976D1 - Verfahren zur Herstellung eines Halbleiterbauelementes mit einem T-Gate. - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelementes mit einem T-Gate.

Info

Publication number
DE69023976D1
DE69023976D1 DE69023976T DE69023976T DE69023976D1 DE 69023976 D1 DE69023976 D1 DE 69023976D1 DE 69023976 T DE69023976 T DE 69023976T DE 69023976 T DE69023976 T DE 69023976T DE 69023976 D1 DE69023976 D1 DE 69023976D1
Authority
DE
Germany
Prior art keywords
gate
producing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023976T
Other languages
English (en)
Other versions
DE69023976T2 (de
Inventor
Junichiro Kobayashi
Shigeru Hiramatsu
Hidemi Takakuwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69023976D1 publication Critical patent/DE69023976D1/de
Application granted granted Critical
Publication of DE69023976T2 publication Critical patent/DE69023976T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/10—Lift-off masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electron Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE69023976T 1989-07-25 1990-07-24 Verfahren zur Herstellung eines Halbleiterbauelementes mit einem T-Gate. Expired - Fee Related DE69023976T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1192854A JPH0355852A (ja) 1989-07-25 1989-07-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69023976D1 true DE69023976D1 (de) 1996-01-18
DE69023976T2 DE69023976T2 (de) 1996-07-18

Family

ID=16298077

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023976T Expired - Fee Related DE69023976T2 (de) 1989-07-25 1990-07-24 Verfahren zur Herstellung eines Halbleiterbauelementes mit einem T-Gate.

Country Status (5)

Country Link
US (1) US5006478A (de)
EP (1) EP0410385B1 (de)
JP (1) JPH0355852A (de)
KR (1) KR910003752A (de)
DE (1) DE69023976T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03248439A (ja) * 1990-02-26 1991-11-06 Rohm Co Ltd 化合物半導体装置の製造方法
FR2663155B1 (fr) * 1990-06-12 1997-01-24 Thomson Composants Microondes Procede de realisation d'une grille de transistor.
JPH04130619A (ja) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp 半導体装置の製造方法
JPH04155835A (ja) * 1990-10-18 1992-05-28 Mitsubishi Electric Corp 集積回路装置の製造方法
US5185278A (en) * 1990-10-22 1993-02-09 Motorola, Inc. Method of making self-aligned gate providing improved breakdown voltage
JPH0575139A (ja) * 1991-09-12 1993-03-26 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5328868A (en) * 1992-01-14 1994-07-12 International Business Machines Corporation Method of forming metal connections
US5304511A (en) * 1992-09-29 1994-04-19 Mitsubishi Denki Kabushiki Kaisha Production method of T-shaped gate electrode in semiconductor device
US5288660A (en) * 1993-02-01 1994-02-22 Avantek, Inc. Method for forming self-aligned t-shaped transistor electrode
DE69433738T2 (de) * 1993-09-07 2005-03-17 Murata Mfg. Co., Ltd., Nagaokakyo Halbleiterelement und Verfahren zur Herstellung desselben
JP2565119B2 (ja) * 1993-11-30 1996-12-18 日本電気株式会社 パターン形成方法
JP2725592B2 (ja) * 1994-03-30 1998-03-11 日本電気株式会社 電界効果トランジスタの製造方法
US5824575A (en) * 1994-08-22 1998-10-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US5486483A (en) * 1994-09-27 1996-01-23 Trw Inc. Method of forming closely spaced metal electrodes in a semiconductor device
JPH08111424A (ja) * 1994-10-11 1996-04-30 Mitsubishi Electric Corp 半導体装置の製造方法
US5693548A (en) * 1994-12-19 1997-12-02 Electronics And Telecommunications Research Institute Method for making T-gate of field effect transistor
JP3336487B2 (ja) * 1995-01-30 2002-10-21 本田技研工業株式会社 高周波トランジスタのゲート電極形成方法
US5733827A (en) * 1995-11-13 1998-03-31 Motorola, Inc. Method of fabricating semiconductor devices with a passivated surface
JP3332851B2 (ja) * 1998-04-22 2002-10-07 松下電器産業株式会社 半導体装置の製造方法
US7008832B1 (en) 2000-07-20 2006-03-07 Advanced Micro Devices, Inc. Damascene process for a T-shaped gate electrode
US6270929B1 (en) * 2000-07-20 2001-08-07 Advanced Micro Devices, Inc. Damascene T-gate using a relacs flow
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
JP4093395B2 (ja) * 2001-08-03 2008-06-04 富士通株式会社 半導体装置とその製造方法
US7892710B2 (en) * 2004-05-27 2011-02-22 University Of Delaware Method for making three-dimensional structures on a substrate having micron dimensions, and an article of manufacture three-dimensional objects on a substrate with micron dimensions
US8981876B2 (en) 2004-11-15 2015-03-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Piezoelectric resonator structures and electrical filters having frame elements
US20080305442A1 (en) * 2007-06-05 2008-12-11 Tdk Corporation Patterned material layer, method of forming the same, microdevice, and method of manufacturing the same
US8796904B2 (en) 2011-10-31 2014-08-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Bulk acoustic resonator comprising piezoelectric layer and inverse piezoelectric layer
US9243316B2 (en) 2010-01-22 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Method of fabricating piezoelectric material with selected c-axis orientation
US8283221B2 (en) * 2010-01-25 2012-10-09 Ishiang Shih Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits
US8962443B2 (en) 2011-01-31 2015-02-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor device having an airbridge and method of fabricating the same
US9490418B2 (en) 2011-03-29 2016-11-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator comprising collar and acoustic reflector with temperature compensating layer
US9490771B2 (en) 2012-10-29 2016-11-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator comprising collar and frame
US9401692B2 (en) 2012-10-29 2016-07-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator having collar structure
US9385684B2 (en) 2012-10-23 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator having guard ring
US9728444B2 (en) * 2015-12-31 2017-08-08 International Business Machines Corporation Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3874916A (en) * 1972-06-23 1975-04-01 Radiant Energy Systems Mask alignment system for electron beam pattern generator
US3994758A (en) * 1973-03-19 1976-11-30 Nippon Electric Company, Ltd. Method of manufacturing a semiconductor device having closely spaced electrodes by perpendicular projection
US4283483A (en) * 1979-07-19 1981-08-11 Hughes Aircraft Company Process for forming semiconductor devices using electron-sensitive resist patterns with controlled line profiles
JPS5811512B2 (ja) * 1979-07-25 1983-03-03 超エル・エス・アイ技術研究組合 パタ−ン形成方法
JPS56133876A (en) * 1980-03-24 1981-10-20 Nippon Telegr & Teleph Corp <Ntt> Manufacture of junction type field effect semiconductor device
US4440804A (en) * 1982-08-02 1984-04-03 Fairchild Camera & Instrument Corporation Lift-off process for fabricating self-aligned contacts
JPS59141222A (ja) * 1983-01-31 1984-08-13 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS59232423A (ja) * 1983-06-15 1984-12-27 Matsushita Electric Ind Co Ltd パタ−ン形成方法
GB2156579B (en) * 1984-03-15 1987-05-07 Standard Telephones Cables Ltd Field effect transistors
JPS60231331A (ja) * 1984-04-27 1985-11-16 Fujitsu Ltd リフトオフ・パタ−ンの形成方法
US4618510A (en) * 1984-09-05 1986-10-21 Hewlett Packard Company Pre-passivated sub-micrometer gate electrodes for MESFET devices
IT1184723B (it) * 1985-01-28 1987-10-28 Telettra Lab Telefon Transistore mesfet con strato d'aria tra le connessioni dell'elettrodo di gate al supporto e relativo procedimento difabbricazione
US4599790A (en) * 1985-01-30 1986-07-15 Texas Instruments Incorporated Process for forming a T-shaped gate structure
IT1190294B (it) * 1986-02-13 1988-02-16 Selenia Ind Elettroniche Una struttura di fotopolimero a multistrati (mlr) per la fabbricazione di dispositivi mesfet con gate submicrometrico e con canale incassato (recesse) di lunghezza variabile
JPH02501250A (ja) * 1987-09-14 1990-04-26 ヒユーズ・エアクラフト・カンパニー Ｔゲートおよびトランジスタの処理方法およびそれにより形成されたｔゲートおよびトランジスタ

Also Published As

Publication number Publication date
US5006478A (en) 1991-04-09
JPH0355852A (ja) 1991-03-11
KR910003752A (ko) 1991-02-28
EP0410385B1 (de) 1995-12-06
DE69023976T2 (de) 1996-07-18
EP0410385A2 (de) 1991-01-30
EP0410385A3 (en) 1991-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN

8339 Ceased/non-payment of the annual fee