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DE69021617D1 - Speicher, der verteiltes Laden von Datenleitungen verwendet. - Google Patents

Speicher, der verteiltes Laden von Datenleitungen verwendet.

Info

Publication number
DE69021617D1
DE69021617D1 DE69021617T DE69021617T DE69021617D1 DE 69021617 D1 DE69021617 D1 DE 69021617D1 DE 69021617 T DE69021617 T DE 69021617T DE 69021617 T DE69021617 T DE 69021617T DE 69021617 D1 DE69021617 D1 DE 69021617D1
Authority
DE
Germany
Prior art keywords
memory
data line
distributed data
line loading
uses distributed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021617T
Other languages
English (en)
Other versions
DE69021617T2 (de
Inventor
George Scott Nogle
Perry H Pelley Iii
Stephen T Flannagan
Bruce E Engles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69021617D1 publication Critical patent/DE69021617D1/de
Publication of DE69021617T2 publication Critical patent/DE69021617T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69021617T 1989-04-21 1990-03-12 Speicher, der verteiltes Laden von Datenleitungen verwendet. Expired - Fee Related DE69021617T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/342,160 US4928268A (en) 1989-04-21 1989-04-21 Memory using distributed data line loading

Publications (2)

Publication Number Publication Date
DE69021617D1 true DE69021617D1 (de) 1995-09-21
DE69021617T2 DE69021617T2 (de) 1996-04-04

Family

ID=23340622

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021617T Expired - Fee Related DE69021617T2 (de) 1989-04-21 1990-03-12 Speicher, der verteiltes Laden von Datenleitungen verwendet.

Country Status (5)

Country Link
US (1) US4928268A (de)
EP (1) EP0394652B1 (de)
JP (2) JP2651948B2 (de)
KR (1) KR960002815B1 (de)
DE (1) DE69021617T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910002034B1 (ko) * 1988-07-21 1991-03-30 삼성전자 주식회사 다분할형 메모리 어레이의 충전등화회로
US5229967A (en) * 1990-09-04 1993-07-20 Nogle Scott G BICMOS sense circuit for sensing data during a read cycle of a memory
US5475635A (en) * 1990-10-01 1995-12-12 Motorola, Inc. Memory with a combined global data line load and multiplexer
JP3100622B2 (ja) * 1990-11-20 2000-10-16 沖電気工業株式会社 同期型ダイナミックｒａｍ
KR970011971B1 (ko) * 1992-03-30 1997-08-08 삼성전자 주식회사 반도체 메모리 장치의 비트라인 프리차아지회로
US5508964A (en) * 1993-01-08 1996-04-16 Texas Instruments Incorporated Write recovery time minimization for Bi-CMOS SRAM
US5457647A (en) * 1993-03-31 1995-10-10 Sgs-Thomson Microelectronics, Inc. Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array
US5574695A (en) * 1994-03-04 1996-11-12 Kabushiki Kaisha Toshiba Semiconductor memory device with bit line load circuit for high speed operation
JP3169788B2 (ja) * 1995-02-17 2001-05-28 日本電気株式会社 半導体記憶装置
WO2000026920A1 (fr) * 1998-10-29 2000-05-11 Hitachi, Ltd. Dispositif de circuit integre semi-conducteur
KR100334573B1 (ko) * 2000-01-05 2002-05-03 윤종용 계층적인 워드 라인 구조를 갖는 반도체 메모리 장치
US6542424B2 (en) 2001-04-27 2003-04-01 Hitachi, Ltd. Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier
KR100492773B1 (ko) * 2002-12-02 2005-06-07 주식회사 하이닉스반도체 확장 메모리 부를 구비한 강유전체 메모리 장치
KR100641707B1 (ko) * 2005-04-08 2006-11-03 주식회사 하이닉스반도체 멀티-포트 메모리 소자

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150286A (ja) * 1984-01-13 1985-08-07 Nec Corp メモリ回路
JPH0770222B2 (ja) * 1984-06-04 1995-07-31 株式会社日立製作所 Ｍｏｓスタテイツク型ｒａｍ
US4698788A (en) * 1985-07-01 1987-10-06 Motorola, Inc. Memory architecture with sub-arrays
JPH0719472B2 (ja) * 1985-10-18 1995-03-06 住友電気工業株式会社 半導体記憶装置
JPS639097A (ja) * 1986-06-30 1988-01-14 Sony Corp スタテイツクｒａｍ
JPS6334793A (ja) * 1986-07-29 1988-02-15 Sumitomo Electric Ind Ltd 半導体記憶装置
JPS63200391A (ja) * 1987-02-16 1988-08-18 Toshiba Corp スタテイツク型半導体メモリ
US4807191A (en) * 1988-01-04 1989-02-21 Motorola, Inc. Redundancy for a block-architecture memory

Also Published As

Publication number Publication date
EP0394652A2 (de) 1990-10-31
JP2651948B2 (ja) 1997-09-10
DE69021617T2 (de) 1996-04-04
JPH09180461A (ja) 1997-07-11
KR900017033A (ko) 1990-11-15
JPH03122897A (ja) 1991-05-24
EP0394652A3 (de) 1993-01-07
KR960002815B1 (ko) 1996-02-26
US4928268A (en) 1990-05-22
EP0394652B1 (de) 1995-08-16
JP2903064B2 (ja) 1999-06-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee