[go: up one dir, main page]

DE68927560D1 - Hochgeschwindige, hochleistende Nulldetektorschaltung mit Parallelverarbeitung - Google Patents

Hochgeschwindige, hochleistende Nulldetektorschaltung mit Parallelverarbeitung

Info

Publication number
DE68927560D1
DE68927560D1 DE68927560T DE68927560T DE68927560D1 DE 68927560 D1 DE68927560 D1 DE 68927560D1 DE 68927560 T DE68927560 T DE 68927560T DE 68927560 T DE68927560 T DE 68927560T DE 68927560 D1 DE68927560 D1 DE 68927560D1
Authority
DE
Germany
Prior art keywords
parallel processing
detector circuit
zero detector
performing zero
high speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927560T
Other languages
English (en)
Other versions
DE68927560T2 (de
Inventor
Masako Nec Ic Microcomp Nakano
Yutaka Nec Ic Microco Yamagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE68927560D1 publication Critical patent/DE68927560D1/de
Publication of DE68927560T2 publication Critical patent/DE68927560T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
DE68927560T 1988-04-29 1989-05-02 Hochgeschwindige, hochleistende Nulldetektorschaltung mit Parallelverarbeitung Expired - Fee Related DE68927560T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63108863A JPH01277931A (ja) 1988-04-29 1988-04-29 零検出回路

Publications (2)

Publication Number Publication Date
DE68927560D1 true DE68927560D1 (de) 1997-01-30
DE68927560T2 DE68927560T2 (de) 1997-05-28

Family

ID=14495497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927560T Expired - Fee Related DE68927560T2 (de) 1988-04-29 1989-05-02 Hochgeschwindige, hochleistende Nulldetektorschaltung mit Parallelverarbeitung

Country Status (4)

Country Link
US (1) US5020016A (de)
EP (1) EP0339685B1 (de)
JP (1) JPH01277931A (de)
DE (1) DE68927560T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245563A (en) * 1991-09-20 1993-09-14 Kendall Square Research Corporation Fast control for round unit
US5581496A (en) * 1992-07-20 1996-12-03 Industrial Technology Research Institute Zero-flag generator for adder
US5270955A (en) * 1992-07-31 1993-12-14 Texas Instruments Incorporated Method of detecting arithmetic or logical computation result
US5469377A (en) * 1992-08-18 1995-11-21 Nec Corporation Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1
US5504867A (en) * 1992-09-29 1996-04-02 Texas Instruments Incorporated High speed microprocessor branch decision circuit
US5367477A (en) * 1993-11-29 1994-11-22 Motorola, Inc. Method and apparatus for performing parallel zero detection in a data processing system
JPH07191831A (ja) * 1993-12-27 1995-07-28 Fujitsu Ltd 演算装置
GB9404377D0 (en) * 1994-03-07 1994-04-20 Texas Instruments Ltd Improvements in or relating to a comparator scheme
US5586069A (en) * 1994-09-30 1996-12-17 Vlsi Technology, Inc. Arithmetic logic unit with zero sum prediction
US5588127A (en) * 1995-06-07 1996-12-24 Texas Instruments Incorporated High speed microprocessor branch decision circuit
US5798958A (en) * 1996-06-05 1998-08-25 Samsung Electronics Co., Ltd. Zero detect for binary sum
US6018757A (en) * 1996-08-08 2000-01-25 Samsung Electronics Company, Ltd. Zero detect for binary difference
US6161164A (en) * 1996-09-16 2000-12-12 International Business Machines Corp. Content addressable memory accessed by the sum of two operands
GB2342729B (en) * 1998-06-10 2003-03-12 Lsi Logic Corp Zero detection in digital processing
US8015230B2 (en) * 2007-06-08 2011-09-06 Apple Inc. Fast modular zero sum and ones sum determination
EP2416241A1 (de) * 2010-08-06 2012-02-08 Panasonic Corporation Konfigurierbare arithmetisch-logische Einheit
US10101967B2 (en) 2017-02-22 2018-10-16 International Business Machines Corporation Zero detection of a sum of inputs without performing an addition

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
JPS59121539A (ja) * 1982-12-28 1984-07-13 Fujitsu Ltd 条件コ−ド決定回路
JPS62190925A (ja) * 1986-02-17 1987-08-21 Nec Corp ダイナミツク型ｎｏｒ回路
JPS6388636A (ja) * 1986-10-01 1988-04-19 Nec Corp マイクロコンピユ−タ
US4815019A (en) * 1987-02-26 1989-03-21 Texas Instruments Incorporated Fast ALU equals zero circuit

Also Published As

Publication number Publication date
DE68927560T2 (de) 1997-05-28
US5020016A (en) 1991-05-28
EP0339685A2 (de) 1989-11-02
EP0339685A3 (de) 1991-08-07
EP0339685B1 (de) 1996-12-18
JPH01277931A (ja) 1989-11-08

Similar Documents

Publication Publication Date Title
DE68927560D1 (de) Hochgeschwindige, hochleistende Nulldetektorschaltung mit Parallelverarbeitung
DE68925866D1 (de) Computersystem mit Verarbeitungsrechner
DE3750115D1 (de) Plasmabearbeitungsgerät.
DE69027299D1 (de) Paralleles Verarbeitungssystem
DE3750625D1 (de) Datenverarbeitungssystem mit zwei Ausführungseinheiten.
DE69008228D1 (de) Plasmabearbeitungsvorrichtung.
DE68927134D1 (de) Mikrowellen-Plasma-Bearbeitungsgerät
DE3853452D1 (de) Mehrfachverarbeitung mit hoher Verfügbarkeit.
DE3750948D1 (de) Datenverarbeitungssystem mit watch-dog Schaltung.
DE3767252D1 (de) Elektronen-nachweis mit energie-unterscheidung.
DE3750949D1 (de) Datenverarbeitungssystem mit watch-dog Schaltung.
DE3887933D1 (de) Plasma-Bearbeitungsgerät.
DE3485418D1 (de) Datenverarbeitungssystem mit ausgangsschaltkreis.
DE3769716D1 (de) Textverarbeitungsgeraet mit randtextaufbereitungsfunktion.
NL194936B (nl) Bewegende detectiekring.
DE3787395D1 (de) Parallele Berechnungsschaltung.
DE68923670D1 (de) Plattenspieler mit Servokreis von variabler Übertragungsfunktion.
DE3767795D1 (de) Atemschutzeinrichtung mit signalverarbeitungseinheit.
KR900010598A (ko) 묘화 처리 장치
DE68913743D1 (de) Detektorschaltung.
NO885125L (no) Krabbeforedlingsmaskin.
DE3769046D1 (de) Sortierapparat.
DE69033514D1 (de) Figurverarbeitungsgerät
DE69000868D1 (de) Detektorschaltung.
DE68914615D1 (de) Fokusfehlerermittlungsschaltung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee