DE68926059T2 - Organization of an integrated cache unit for flexible use in the design of cache systems - Google Patents

Abstract

Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be peformed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.

Description

The invention relates generally to an apparatus for organizing cache memories, and more particularly to an apparatus for organizing an integrated cache memory unit that enables flexible design of a cache memory system. The resulting cache memory unit is programmable and, in addition to supporting single-processor operations, is capable of supporting multiprocessor operations, e.g., by implementing copy-back and ownership schemes; supporting high-speed instruction and data processing in a reduced-instruction-set computing (RISC) environment; and supporting all of the foregoing functions with an architecture suitable for integration on a single chip.

Cache memories and cache memory controllers are widely known. Devices are also known in which both the memory and control functions are integrated on a single chip. One such device is the commercially available 43608 device manufactured by NEC. Such devices are referred to below as "integrated" cache memory units (ICUs).

Conventional ICU devices use specific algorithms to cache data and instructions, meaning that the devices are not programmable. So far, it has not been possible to implement a cache memory, a cache memory It is difficult to integrate controller and programmability features on a single chip, in part because of circuit density and data path requirements. In addition to the lack of programmability, no known ICU architecture has been able to overcome the problems caused by circuit density and data path requirements that arise when supporting high-speed RISC processing systems, particularly high-speed RISC systems with multiprocessor capabilities.

A programmable integrated cache unit would be desirable as it would have the inherent flexibility to allow the choice and/or modification of cache algorithms.

A single-chip ICU architecture with the above-mentioned programmability feature would be further desirable to minimize area and unit power requirements. In addition, it would be desirable to be able to use such an integrated cache memory unit to support high-speed processing operations in both single- and multiprocessor modes, for both RISC and non-RISC environments.

An article by D. Bursby in Electronic Design, Vol 35, No. 5 entitled "Intelligent cache-memory chip speeds access to most CPU's" describes an integrated cache unit (ICU) architecture in which the cache functions are implemented in a computing system. The system includes a central processing unit (CPU), a processor bus for communication between the CPU and the ICU, and a memory bus for communication between a memory and the ICU. A processor bus unit connected to the processor bus controls an ICU/processor bus interface, and a memory bus unit connected to the memory bus controls an ICU/memory bus interface. A cache unit connected to both the processor bus unit and connected to the memory bus unit, comprises a tag array device and a valid array device with an associated memory array device. The tag array device, the valid array device and the memory array device are organized as a 4-way set associative cache device.

In an article by C.J. Conti in Computer Group News, March 1969, pp. 10-13, entitled "Concepts for buffer storage," a set-associative buffer design is discussed, in which blocks intended for buffer storage, each of which is provided with an associated tag, are grouped into sets.

An article by 1. Wilson in New Electronics, Vol 20, No. 7, 31 March 1987, pp. 30,32,33, entitled "Extending 80386 performance" describes a cache memory system with an external memory.

In WESCON PROCEEDINGS, San Francisco, CA, 19-22 November 1985, Vol 29, 1985, Session 6/5, pages 1-6, New York, US; H/ SACHS: "The fairchild dipper microprocessor family - A high- performance 32-bit processor" the architecture of the CLIPPER microprocessor family is described. In particular, the document describes the separate instruction and data cache memory and shows that the operating system can assign the cache strategy (write through or copy back) to each page in the memory. The page table entry contains a field to define the cache strategy for each page.

According to the invention, an ICU architecture is provided generally as described in the above-mentioned article by Bursby, characterized in that the cache memory unit further comprises a set of special registers coupled to an address bus and a data bus, wherein the address bus and the data bus are coupled to the processor bus unit and to the memory bus unit, and at least one of the registers is a programmable register by means of which the user selects certain ICU options and procedures.

In the present specification, methods and apparatus are described for implementing an integrated cache memory unit that is flexible for use in a cache memory system design. The preferred embodiment of the invention has both a cache memory and a cache memory controller on a single chip, is programmable, and also has the other desired properties listed above.

According to the preferred embodiment of the invention, flexible cache memory system design is achieved by methods and apparatus that facilitate user specification of desired cache memory characteristics by setting appropriate cache option bits. This can be done under software control and enables a high performance cache memory system that can be designed with a small number of components and at low cost and can operate with high efficiency.

The preferred embodiment of the invention is described in the context of an integrated cache unit (ICU) having 8K bytes of data, 512-20 bit words of tags and the necessary control to fully implement the cache functions in both RISC and non-RISC environments. The preferred embodiment of the ICU has two buses, one for the processor interface and the other for a memory interface. An example of a processor and a high speed interface supported by the ICU is described in EP-A-0283115.

For the purposes of this description, it is assumed that the processor bus means is a non-multiplexed 32-bit address and data bus. The processor bus supports burst and pipeline accesses in accordance with the teaching of EP-A-0283115. Furthermore, for the purposes of this description, it is assumed that the memory bus forms the interface to the main memory and accommodates the multiprocessor organizations.

According to the preferred embodiment of the invention, the ICU is capable of operating at frequencies above 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or pipelined accesses. The invention can be used either as an instruction cache or as a data cache with flexible internal cache organization. A RISC processor and two ICUs (for instruction caching and data caching) result in a high performance processor with 16k cache bytes. Larger caches can be designed by using additional ICUs.

Methods and apparatus are described for implementing a programmable integrated cache memory unit having a wide range of user-defined options that can be used, for example, to specify replacement algorithms, cache memory organizations, and multi-processor support schemes.

Methods and apparatus are described for implementing a programmable integrated cache memory unit capable of supporting high speed data and instruction processing operations in both RISC and non-RISC architecture environments. The cache memory unit can be integrated on a single chip and the described ICU can be implemented either as a data Cache memory or instruction cache memory can be used.

The drawings, which are intended only as examples, are briefly explained below.

Fig. 1 shows a block diagram of a computing system containing two of the ICUs according to the invention.

Fig. 2 shows the pin package and the various inputs and outputs in/out of the ICU according to the invention.

Fig. 3 shows a data flow diagram to illustrate the data flow via the ICU between the processor bus unit and the memory bus unit of Fig. 1.

Fig. 4 shows a simplified split-bus multiprocessor system with two ICUs per processor, where one ICU is used as an instruction cache and the other as a data cache.

Fig. 1 shows a typical configuration of a computing system that can contain the novel ICU.

For illustrative purposes only, the invention will be described in the context of a RISC processing system having both single and multiprocessor modes of operation. Those skilled in the art will appreciate that the ICU, which is described in detail below, can also be used in non-RISC environments.

Figure 1 shows two of the novel ICUs. The ICU 101 is shown in use as an instruction cache, and the ICU 102 is shown in use as a data cache.

An example of the shown suitable high-speed interface connecting the RISC streamlined instruction processor (SIP) to the cache memories is described in detail in EP-A-0283115.

This application, incorporated herein, further teaches the various modes of operation of the SIP, processor inputs and outputs, etc. referred to herein and explained in terms of the manner in which they are supported by the novel ICU.

Fig. 1 also shows the processor bus, which consists of the address bus 120 and the data bus 121. The processor 110 accesses the instructions in the instruction ROM 150 and the instruction cache memory, the ICU 101, via the address bus 120. As shown, the captured instructions are transmitted to the processor 110 via the bus 125.

The address bus 120 also provides access to the data cache memory, the ICU 102. The bidirectional data flow between the processor 110 and the ICU 102 can take place in the manner shown via the data bus 121.

A memory bus 175 is shown as a bus connecting main memory 190 to ICU 101 and ICU 102. For completeness, an arithmetic accelerator 195, which would be part of a typical RISC system configuration, is shown coupled to buses 120 and 121. Data transfer controllers (DTCS) shown as DTC 198 may also be used as part of a typical system configuration, e.g., to allow commercially available peripherals having speeds significantly lower than the high-speed processor to be coupled to the system without limiting the performance of the processor, cache memory units, etc.

A typical arithmetic accelerator is described in EP-A-0214775.

Before continuing with the detailed description, the novel integrated cache memory architecture is first described, whereby for the sake of clarity the general cache memory expressions and multiprocessor cache memory expressions used must first be defined. The general cache memory expressions used here are defined as follows:

Block - A cache block is a group of sequential words associated with a tag. A cache block is allocated as a group and replaced whenever necessary. In the preferred embodiment of the ICU, the block size is four words (one tag per four words).

Block Status - Status bits associated with a cache memory block. According to the preferred embodiment of the ICU, there are two status bits per block. These specify the modified and shared status of a block.

Block status array - An on-chip random access memory array that contains the block status bits.

Copy-back - A writing technique in which, in the event of a hit, a write access is only performed in the cache memory. The block containing the written data is marked as modified. The data is only written (copied back) to main memory when the modified block is replaced.

Data Cache - A cache memory used to cache frequently used processor data variables.

Directly mapped - This is an alternative term for a one-way associative organization. A given address can only be cached (directly mapped) at a specific location in the cache memory.

Hit - The word specified by the access address is present in the cache memory array. An address match is detected in the tag array and the corresponding valid bit is set.

Invalidate - An operation that removes valid data from the cache memory. One or more valid bits are reset, making the corresponding words invalid.

Instruction Cache - A cache memory used to cach frequently used processor instructions.

Least recently used (LRU) - A replacement algorithm in which the block to be replaced is chosen according to the history of its use. The block that has been used the furthest in the past is replaced.

Cache Locking - Data variables or instructions can be locked in cache. They will not be replaced even if they are selected by the replacement algorithm. Note that the *LOCK input signal, to be described later, is intended for ICU interlock locking operations and is not used for cache locking operations. Each block has a lock bit associated with it to facilitate block locking.

Cache Array - On-chip random access memory array that contains cached data or instructions.

Memory bus - The bus that connects cache memory to main memory.

Miss - The word specified by the access address is not present in the cache memory array.

Modified Block - A block is marked as modified if it is written in a copy-back notation. This indicates that the block is modified relative to main memory and contains the more recent version of the data.

Non-cacheable - An instruction or data variable that cannot be cached. A non-cacheable operation is transferred to the memory bus by the ICU. The cache is not searched for it, and no cache block is allocated.

Prefetch - The operation of retrieving data variables or instructions into cache memory before they are requested.

Prefetch Buffer - A buffer that holds prefetched data variables or instructions read from the store buffer before they are written to cache memory. In the ICU, the read buffer is used in the function of a prefetch buffer.

Preload - A special prefetch operation that loads the cache memory with specific data variables or instructions. The addresses for the preload operation are specified by the user, unlike other prefetch operations, where the prefetched addresses are determined from the cache memory.

Processor bus - The bus that connects the cache memory to the processor.

Arbitrary Replacement - A replacement algorithm in which the block to be replaced is chosen arbitrarily.

Read Buffer - A buffer that holds the data variables or instructions read from the memory bus before they are written to the cache. In the preferred embodiment of the ICU, the read buffer is four words deep and is also used in the function of a prefetch buffer.

Read-through - In the event of a cache miss, the required data or instructions are delivered to the processor as soon as they are accepted by the memory. The reload operation completes in parallel. In a cache without read-through, the reload operation completes before the requested data or instructions are delivered to the processor.

Reload - The operation performed in the event of a data-memory miss to retrieve the requested data or instructions from main memory.

Replacement algorithm - The algorithm that determines the block to be replaced when a new block is placed in the cache. A block is chosen from the set containing the required new address.

Scope - This term is used in the context of cache instructions to define the scope of the instruction's effect. The instruction can specify a specific ICU, affect multiple instruction caches, multiple data caches, or multiple instruction and data caches.

Set - A group of tags and their associated cache blocks that are read and compared simultaneously with the required addresses. A match can be found with any of the tags in the set. The set is determined according to some of the address bits. The number of tags in the set equals the number of "ways" (defined below) in the cache organization.

Set-associative - A cache organization that allows a given address to be cached in a number of possible locations in the cache memory. This number is called the degree of associativity. It determines the number of "ways" in the cache organization and the number of tags that are read and compared simultaneously. The disclosed ICU supports two-way and one-way set-associative organizations.

Subblock - A group of one or more words that are fetched from main memory along with the requested word for the reload operation. The size of the subblock defines the maximum number of words that will be fetched. The size of the subblock is less than or equal to the size of the block.

Tag - The tag identifies the address of the data or instructions currently present in the cache memory. Each cache memory block is associated with a cache memory tag and is stored in the tag memory array. In the preferred embodiment of the ICU, each tag corresponds to a four-word block.

Tag Array - On-chip random access memory array that contains the address tags for the cached data or instructions.

Refresh memory - An operation that causes the update of main memory from cache memory. A modified block is written from cache memory to main memory so that memory is updated with the most recent version of the data.

Valid Array - On-chip random access memory array that contains the valid bits.

Valid Bit - A bit that indicates the validity of the cached data. In the preferred embodiment of the ICU, each cached word has a valid bit associated with it.

Way - A group of tags associated with a tag array module. From each way, only one tag, determined by the module's address decoder, is read and compared. In the preferred embodiment of the ICU, there are two ways, each with 256 tags.

Write Mapping - In case of a cache miss for the write operation, a cache block is allocated for the block containing the written address. A reload operation is performed for the requested block. For non-write mapping, no cache block is allocated and the write is performed only in the memory.

Write buffer - A buffer that holds the write access information (address, data and control) until the write access is performed for the memory bus. The preferred embodiment The ICU contains a quad-deep write buffer that can hold up to four write accesses.

Write-through - A write style in which every write access is made into main memory. In the event of a cache hit, the data is also written to the cache.

The multiprocessor cache memory terms used here are defined as follows:

Bus monitoring - The memory bus is monitored (observed) by the slave caches. These compare the transmitted addresses with the buffer addresses. If a match is found, a special operation can be performed. The terms "bus sniffing" or "cache sniffing" are equivalent.

Cache consistency - This is another term to describe data consistency in a multiprocessor cache system.

Data Consistency - This is the main problem in multiprocessor cache systems. If a variable is shared by multiple processors, it can be stored in multiple caches. The most recent version of the variable must be supplied whenever the variable is accessed. This ensures consistency of the data variables across the entire system.

Data Intervention - An operation that can be performed by a slave cache when a match is detected on a memory bus read access. If the slave cache contains modified data (the most recent version of the data), it intervenes in the access and supplies the data. In this case, the main memory must not supply the data.

Exclusive - Indicates that a variable or cache block exists exclusively in a cache. The variable or cache block may be used exclusively by a single processor, or it may be used by multiple processors but only exists in a single cache. In the preferred implementation of the ICU, a LOW in the shared block status bit indicates an exclusive block. The block may be either exclusively unmodified or exclusively modified.

Locking - Locking operations are used to temporarily lock a variable (lock variable) for exclusive use by a processor. No other processors or caches are allowed to use the variable while it is locked. The * LOCK input to the ICU indicates a locking operation, as explained below.

Master Cache - A cache that is a master of the memory bus. It issues the request and awaits a response.

Match - The memory bus access address matches one of the addresses present in the tag buffer and the corresponding word is valid. The expression is used for memory bus address comparison and is equivalent to the "hit" expression used for the processor bus.

Ownership - This is a scheme to guarantee data consistency. The most recent value of the variable is owned by a cache or main memory. It is the responsibility of the owner to maintain the consistency of the variable. There are several ownership schemes that differ in the number of states assigned to a variable and the algorithms for ownership and state transitions.

Shared - This term indicates that a variable or cache block is shared by more than one processor. A shared variable can be present in more than one cache. In the preferred embodiment of the ICU, a HIGH in the shared block status bit indicates a shared block. The block can be either unmodified when shared or modified when shared.

Shared Modified - A block state in the ICU that indicates that a cache block is shared and modified. The expression also indicates that the block is owned by the cache and that it is the most recent value of the block in the system.

Slave cache - A cache that is not the master of the memory bus. To achieve data consistency, a slave cache can monitor the memory bus.

Sniffing - Another term for "bus monitoring". The terms "bus sniffing" or "cache memory sniffing" are other equivalents.

Having defined the terms used herein above, the preferred embodiment of the novel ICU is described in detail below with respect to its pin elements and functional organization.

Regarding the description of the pins, it should be noted that the term "tri-state" is used to describe signals that can be driven to the high impedance state during normal operation. All output signals (except MSERR, which is to be described) can be driven to the high impedance state by the *TEST input signal (which is also to be described).

The preferred embodiment of the novel ICU is a CMOS with a 169 pin grid array package, as shown in Fig. 2.

The processor bus interface, which is described first, has the following features:

The address bus, pins A0-A31 of Fig. 2, is an ICU input, is synchronous, and carries the byte address for cache memory access to the processor bus.

The Access Status Control signals (shown as ASTC0 and ASTC1 in Fig. 2) are synchronous input signals that determine the status control associated with an access. According to the preferred embodiment of the invention, they are encoded as follows: Meaning Exclusive write-through Exclusive copy-back Shared Not cacheable

These input signals are normally coupled to the outputs MPGMo-MPGM1 of the processor 110, as shown in the incorporated application describing processor outputs.

*BINV (Bus Invalid) is an active LOW synchronous ICU input signal indicating that the address bus and associated controls are invalid. The signal defines an idle cycle in the processor bus 120.

*CBACK (Cache Burst Acknowledge) is an ICU output signal that is synchronous and active LOW. This output signal is asserted each time a burst mode cache access has been made on processor bus 120.

*CBREQ (Cache Burst Request) is an ICU input signal that is synchronous and in the active LOW state. This input signal is used to perform a burst mode cache access on the processor bus and to request the next transfer during a burst mode cache access. This signal may become valid late in the cycle compared to *DREQ or *IREQ, which will be described later.

*CERR (Cache Error) is an ICU output signal that is synchronous and in the active LOW state. This output signal indicates that an error has occurred during the current cache access.

*CRDY (Cache Ready) is an ICU output signal that is synchronous and active LOW. During processor bus cache reads, this signal indicates that there is valid data on the cache bus. During cache writes, The signal indicates that data on the cache memory bus does not need to be accessed.

CREQT0-CREQT1 (Cache Request Type) is a synchronous input signal. These signals specify the address space on the processor bus as follows: Data Cache Memory Usage Meaning Memory Access Input/Output Access Coprocessor Transfer (ignored by the ICU) Instruction Cache Memory Usage Meaning Memory Access Instruction Read Only Memory Access

For instruction cache usage, CREQT1 has a special function. It is sampled during RESET, and if the sample value is HIGH, the ICU responds to instruction ROM accesses. If the sample value is LOW, the ICU does not respond to instruction ROM accesses. After RESET, the CREQT1 input is ignored during instruction cache usage.

*CSEL (Chip Select) is a synchronous input signal that is in the active LOW state. An active level at the *CSEL input selects the ICU for processor bus Cache memory instruction accesses. It is not used for normal memory accesses. The *CSEL input can be disabled via the chip select map register, a part of the ICU to be described later. If *CSEL is enabled and not asserted, the ICU does not respond to processor bus cache memory instruction accesses.

*CSM (Chip Select for Memory access) is a synchronous ICU input signal that is active LOW. An active level on the *CSM input selects the ICU for memory accesses. The signal can be used for cache memory extensions and cache memory address space selection. The *CSM input can be enabled via the chip select mapping register. When *CSM is enabled, the ICU responds to memory accesses only if *CSM is asserted and the address matches corresponding enabled bits in the preselected field of the chip select mapping register (to be described in detail).

CB0-CB31, the cache memory bus, is bidirectional, synchronous and tri-state. The cache memory bus transfers instructions or data on the processor bus to and from the ICU.

*DREQ (Data Request) is a synchronous ICU input signal that is active LOW. This input signal requests data access to the processor bus. When active, the address for access appears on the address bus. In the instruction cache usage of the ICU, *DREQ is used for processor bus cache instruction transfers.

*IREQ (Instruction Request) is a synchronous ICU input signal that is in the active LOW state. This input signal requests an instruction cache memory access on the processor bus. When active, the address for access appears on the address bus. This input signal has a special function during the ICU reset operation. It is sampled by the rising edge of SYSCLK when RESET (to be described later) is active. The last sampled value determines the ICU operation as a data cache (*IREQ LOW) or an instruction cache (*IREQ HIGH). For a data cache operation, *IREQ must be tied LOW (it is ignored during normal operation). For an instruction cache operation, it must be coupled to the processor *IREQ output, which is invalidated during RESET. Note that if the processor is placed in test mode during RESET, external logic must drive the processor's IREQ signal HIGH. (The processor described in the copending application with respect to the high performance interface does not drive IREQ to the HIGH state in its test mode.)

*LOCK is an ICU input that is synchronous and active LOW. This input indicates that the processor cache memory access is to a locked variable. The ICU handles this access in a special way that will be explained in connection with the locking function, which will be described in detail later.

MSERR (Master/Slave Error) is a synchronous ICU output signal that is in the active HIGH state. This output signal shows the result of comparing the ICU output signals with the signals applied externally to the off-chip drivers. If there is a difference for any of the activated drivers, this signal is asserted.

OPT0-OPT2 (Option Control) is a synchronous ICU input signal. These signals represent the option control bits associated with a cache memory access. They are used to specify the data length and special access information. The interpretation of these signals depends on the use of the ICU as a data or instruction cache memory. The encoding and interpretation of these input signals is carried out according to the preferred embodiment of the invention as follows: OPT2-0-VALUE Meaning Data cache memory Meaning Instruction cache memory Bit access no access Instruction memory access (as data) Cache operand transfer Debug module access reserved

The OPT input signals are ignored if DREQT1 is in the HIGH state (treated as non-access). The codes 100,101 are treated as non-access if DREQT0 is in the HIGH state. The code 100 is used to access the instruction ROM as data A data cache responds to this code only if the ROM enable bit in the Moda register, to be described later, is HIGH. In this case, the request is treated as a non-cacheable access. Code 101 indicates an operand transfer for the ICU processor bus cache instructions. In accordance with the preferred embodiment of the invention, code 101 is used for a special debug module access. A data cache responds with *CRDY HIGH for four cycles, and then *CRDY is asserted for one cycle.

*PCA (Pipelined Cache Access) is a synchronous ICU input that is active LOW. If *DREQ for the data cache or *IREQ for the instruction cache is not active, this input indicates that the cache access is pipelined with another cache access in progress. The pipeline access cannot complete until the first access is complete. Completion of the first access is signaled by the assertion of *DREQ for the data cache and *IREQ for the instruction cache.

*RESET is an asynchronous input signal that is in the active LOW state. This input signal resets the ICU.

R/*W (Read/Write) is a synchronous input signal. This input signal indicates whether the cache memory access is a transfer from the ICU to the processor (R/*W High) or from the processor to the ICU (R/*W Low).

SUP/*US (Supervisor/User Mode) is a synchronous input signal. This input signal indicates the program mode of the processor shown (supervisory mode or user mode) during access. The ICU's internal registers and the execution of cache memory instructions are protected from user mode accesses.

SYSCLK (System Clock) is an external clock input signal with the operating frequency of the ICU.

*TEST, test mode, is an asynchronous input signal that is in the active LOW state. When this input signal is active, the ICU is in test mode. All outputs and bidirectional lines, except MSERR, are forced into the high impedance state.

WREP (Way for Replacement) is a synchronous input. This input forces the way number for replacement in case of a cache miss. It is sampled during the first cycle of a valid cache access. A miss in a set two-way mapping organization (if the replacement mode is external) causes a replacement determined by WREP: WREP LOW forces a way 0 replacement, WREP HIGH forces a way 1 replacement.

The following describes the memory bus interface, still in connection with Fig. 2. The memory bus can have the following features:

BSTC0-BSTC1 (Block Status Control) are bidirectional, synchronous and designed for three states. These signals are used to inspect and update the cache block status information. When requested by a memory bus instruction, the ICU uses these signals to indicate the block status bits associated with the addresses supplied. These signals are also used to supply the block status from the memory bus for a write block status instruction. The encoding of this signal for both of the above functions is as follows: Meaning exclusive unmodified exclusive modified shared unmodified shared modified

*DI (Data Intervention) 1 Data Intervention is a synchronous output signal that is tri-state and in the active LOW state. This output signal is used to indicate a data intervention operation on the memory bus. The data intervention operation is used in some multiprocessor configurations to fetch the most current version of the variable from the appropriate cache memory (as opposed to main memory). The ICU master preloads the *DI signal during the address cycle of a memory bus read access. It then places the signal in tri-state mode. The ICUs that are not the bus masters assert the *DI signal if they respond with a data intervention.

*GRT (Memory Bus Grant) is a synchronous input signal that is in the active LOW state.

This input signal indicates that the memory bus is allowed for ICU use.

*HIT is bidirectional, synchronous, tri-state, and active LOW. This signal can be programmed to be either an output signal or an input/output signal. As an output signal, it is used to indicate a hit. The signal is asserted when a hit is detected in the tag buffer for the address present on the memory bus. It is also used in some of the memory bus instructions to indicate the validity of a word or block.

When programmed as an input/output signal, it can be used as a hit detection signal in any other cache memory in addition to the output signal functions mentioned. The ICU master preloads the *HIT signal during the address cycle and then places it in the input signal tri-state mode. The ICUs that are not the bus masters only assert the *HIT signal when a hit is detected in their tag buffer.

*MASTB (Memory Address Strobe) is bidirectional, synchronous, tri-state, and active LOW. When the ICU is the memory bus master, this signal is asserted by the ICU to indicate that a byte address is present on the memory bus. When the ICU is not a master, this signal indicates that a byte address from another bus master is present on the memory bus. Note that if both the instruction cache and the data cache are present in the system, two *MASTB signals are available. The two signals can be used to distinguish between instruction and data accesses.

*MBACK (Memory Burst Acknowledge) is a synchronous input signal that is active LOW. This input signal is active whenever a burst mode cache access has been established on the memory bus.

MBPO-MBP3 (Memory Byte Parity) is bidirectional, synchronous and tri-state. It is the byte parity bus for transfers on the memory bus. Even or odd parity can be specified. MBP0 means byte parity for MEMAD0-MEMAD7, MBPL means byte parity for MEMAD9-MEMAD15, etc. For transfers from the ICU to memory, the ICU generates parity. For transfers to the ICU, it checks the byte parity.

If a parity error is detected and data is to be transferred on the processor bus, the *CERR signal is asserted. If the data does not need to be transferred on the processor bus (e.g., during a block reload), an error bit is set in the status register (to be described later) and the data is ignored. Parity generation and checking can be disabled. If parity generation and checking are disabled, the memory bus data timing is relaxed.

*MBREQ (Memory Burst Request) is bidirectional, synchronous, tri-state, and active LOW. This signal is used to establish a burst mode access to the memory bus and to request the next transfer during the burst mode access. When the ICU is the bus master, this signal is an output signal. If the ICU is not a master, the signal is an input signal used by the ICU for data consistency operations.

MDLNO-MDLNI (Memory Data Length) are bidirectional, synchronous and designed for three states. These signals reflect the data length for the memory bus data accesses. They are ignored for instruction accesses. For data cache use, the ICU supports 8, 16 and 32 bit transfers. The encoding of these signals is carried out according to the preferred embodiment of the invention as follows: Meaning Bit access invalid

It should be noted that the MDLN0 and MDLN1 encoding corresponds to that for OPT0 and OPT1 in the processor used in the exemplary embodiment of the invention.

MEMAD0-MEMAD31 (Memory Address/Data Bus) is bidirectional, synchronous, and tri-state. The memory bus is a multiplexed address/data bus used for the memory interface. When *MASTB is asserted, this bus holds the byte address of the memory bus access. If the ICU is the bus master, it outputs the address. If the ICU is not the bus master, the bus is an input, and the address is used by the ICU for its internal use. When MASTB is not asserted, the memory bus is used to transfer data to and from the ICU.

*MERR (Memory Error) is a synchronous ICU input signal and is actively LOW. This input signal indicates that an error has occurred during the current memory access. The ICU also uses this signal for data consistency operations.

*MLOCK (Memory Lock) is bidirectional, synchronous, tri-state, and active LOW. This signal indicates that the memory access is a locked access. The ICU master asserts this output when a locked access is made to the memory bus. If the ICU is not the bus master, this signal is used as an input. If a match is found on a write access while asserting *MLOCK, the associated word is invalidated. This feature is used for schemes that enable caching of lock variables.

*MRDY (Memory Ready) is bidirectional, synchronous, and actively LOW. When the ICU is the bus master, this signal is used as an input. For memory bus reads, this input indicates that valid data is present on the memory bus. For memory bus writes, this signal indicates that the data does not need to be driven further on the memory bus. When the ICU is not the bus master, this signal is used as an input for data consistency operations. It is used as an output for data intervention and memory bus special operations. The ICU asserts *MRDY to indicate that valid data is present on the memory bus. MREQT0-MREQT1 (Memory Request Type) are bidirectional, synchronous and tri-state. These signals specify the address space for accessing the memory bus. If the ICU is the bus master, it uses these signals as output signals. If it is not the bus master, the MREQT signals are used as input signals for data consistency operations. The encoding is done according to the preferred embodiment of the invention as follows: Meaning Data memory access Data input/output access Instruction memory access Instruction ROM access

When the ICU is not a bus master, the MREQT signals are also used (along with the MRW signals) to specify a memory bus cache instruction for the ICU.

MRWO-MRWL (Memory Read Write) are bidirectional, synchronous and tri-state. These signals are used to determine the type of read and write operations on the memory bus. When the ICU is the bus master, it uses these signals to indicate the requested operation. When the ICU is not the bus master, these signals are input signals used for data consistency operations. The encoding of these signals is done according to the preferred embodiment of the invention as follows: Meaning Write Read Write broadcast Read to modify

The above-mentioned read and write operations are performed with respect to the ICU, e.g. reading from the memory into the ICU.

When the ICU is not the bus master, the MRW signals are also used (along with the MREQT signals) to specify the memory bus cache instruction for the ICU. A detailed description of a memory bus instruction set suitable for use with the ICU described here will be given later.

MS/*MU (Memory Supervisor/User Mode) is a synchronous ICU output signal and is designed for three states. This output signal indicates the program mode for the processor during memory access (supervisor mode or user mode). The ICU transfers the SUP/*US value present on the processor bus to the MS/*MU value present on the memory bus for the corresponding transactions.

*REQ (Memory Bus Request) is a synchronous ICU output signal and is in the active LOW state. This output signal is used by the ICU to request the memory bus.

*VSI (Valid Status or Instruction) is a synchronous ICU output signal and is in the active LOW state. When the ICU is the bus slave, a validated *VSI indicates a memory bus cache instruction access. When the ICU is the bus master and issues a read request for a reload operation, the assertion of *VSI indicates that a special write block status instruction is to be executed. A detailed description of a suitable memory bus cache instruction set and the use of *VSI follows.

After describing the various inputs and outputs into and from the novel ICU using the pin connection diagram of Fig. 2, the functional organization of the ICU is described in detail for a deeper understanding of the novel methods and devices. This description is divided into several parts. First, an overview is given of the way the ICU fits into a computer system, in particular the example RISC system used to illustrate the applicability and operation of the invention. Second, the data flow through the ICU is described in detail. Third, an explanation is given of the register levels of a register set suitable for implementing the invention. Also described are a suitable cache instruction set, data formats and handling, cache memory accesses and prefetch operations.

Further details of the use of an ICU write buffer, initialization and reset operation are also explained.

In addition, to conclude the detailed description of the invention, the multiprocessor support provided by the ICU and the special ICU locking function are described.

As previously mentioned, the novel ICU is explained in the context of a RISC architecture containing a SIP. The preferred embodiment of the invention is described as used to support this architecture. Those skilled in the art will readily appreciate that modifications can be made to the preferred embodiment of the novel ICU without departing from the scope of the inventive concept, e.g., to support non-RISC processors. The following description is therefore for illustrative purposes only.

The core of the preferred embodiment of the ICU consists of a 9k byte memory array with the associated tags and valid arrays. The arrays are organized as a two-way set-associative cache with 4 words per tag (block size = 4 words) and one valid bit per word. This basic organization further supports a direct-mapped cache, variable block and sub-block size, and a flexible reload scheme. A block status array and an LRU array are also provided. These are used for cache replacement, locking data in the cache, and for data consistency purposes. The ICU contains all the control logic for the various cache functions, algorithms, and instructions. Special registers are used for programmable option selection, cache instruction implementation, and status reporting.

The cache functions can be selected using programmable options. The cache write function can be selected as write-through, copy-back, or flexibly on a per-access basis. A write-mapping or non-write-mapping option can be selected. can be selected. A four-word write buffer is provided to efficiently perform the write accesses. The write buffer can be enabled or disabled. The replacement algorithm can be programmed as LRU, direct or external facility. A flexible prefetch function can be selected. The read-through option can be enabled. A four-word read buffer is provided to support efficient prefetch and read operations.

The multiprocessor support function can be tailored to the system. The level of multiprocessor support can vary from a simple software-controlled organization to an extensive ownership scheme. A bus monitor function can be enabled or disabled. The ownership algorithm can be controlled to support the requested scheme. Caching of locking variables can be enabled or disabled.

Two-chip select inputs and a chip select mapping register allow easy cache memory expansions as well as multiple cache memory organizations. The reload function can be tailored to the system by choosing the appropriate access control options, such as reload sizing, start and stop addresses, burst and wraparound

The preferred embodiment of the ICU operates at the same frequency as the RISC processor in the illustrative example given, i.e., at a nominal frequency of 25 MHz and possibly higher frequencies. The embodiment achieves access times of two cycles for the first hit access and of one cycle for the next burst mode or pipeline hit accesses.

A three-IC configuration, one containing the RISC processor and two dedicated to the ICUs (one for an instruction cache and one for a data cache), forms a high-performance cache memory system with 16k cache bytes.

As already explained in connection with Fig. 1, the ICU has two interface buses, the processor bus and the memory bus. It can be connected directly to the RISC processor without any interface logic. The ICU cache memory bus is connected to the processor's data or instruction bus for data or instruction cache storage, respectively. Pipeline and burst mode accesses are supported in such a way that the processor channel is maximally utilized. The memory bus is a separate interface to the memory, other processors, and the system bus. It is a multiplexed address and data bus with support for burst mode accesses. It also has multiprocessor support functions. In multiprocessor environments with shared memory, the memory bus can effectively be used as a shared multiprocessor bus. In single-processor systems it can be used as a system bus or a local bus.

The preferred embodiment of the ICU includes special hardware to support fault tolerance. The hardware supports master/slave checking and byte parity generation and checking on the memory bus. For master/slave checking, one or more ICUs are connected in parallel to one or more caches (the slaves) to check the outputs of the master. Byte parity generation and checking can be used on the memory bus for reliable bus transfers.

As already mentioned, the preferred embodiment of the invention is designed in CMOS technology and has a maximum power consumption of 1.5 W.

The internal data flow organization of the ICU is shown in Fig. 3. The following description refers to the functional components of this data flow diagram. The ICU is divided into three main functional units: processor bus unit, memory bus unit, and cache memory unit, all of which are shown in Fig. 3. The following description refers in part to specific bit locations and fields of various words used for any number of purposes. Those skilled in the art will readily appreciate that these specific references are not limiting and may be modified to suit a desired application. Each reference is made for clarity and is intended to describe only a practical, illustrative, preferred embodiment of the invention.

The processor bus unit controls all activity of the processor bus. It supports all RISC/SIP channel protocols; simple, bursted and pipelined. It contains the address incrementer, the data shifter and the processor bus control device, all of which are described below.

The address incrementer (AI) latches the address bus input. It can be incremented every cycle. The AI output is the address for a cache memory access. The AI is shown in Fig. 3 as unit 301.

The data shifter (DSH) is used for data alignment.

It shifts bytes and halfwords and holds the data for write access. It is also used for byte and halfword reading used for the corresponding byte and halfword shift operation. The DSH is shown in Fig. 3 as unit 302.

The processor bus controller (PBC) controls the various processor bus operations. The PBC is shown in Figure 3 as unit 303.

The memory bus unit controls the activity of the memory bus. It contains the write buffer, the memory address logic, the memory read buffer and the memory bus controller, all of which are described below.

The write buffer (WB) used in the preferred embodiment of the invention contains two four-word first-in-first-out (FIFO) buffers (one for address and one for data). The WB can buffer all ICU write operations. For write-through operations, it buffers up to 4 bytes, half-word or word writes. For copy-back operations, it buffers a four-word block. The WB is shown in Figure 3 as unit 304.

The memory address logic (MAL) has two address incrementers. The first latches and increments the memory bus addresses for operations from the bus to the ICU. The second latches and increments the addresses for read operations initiated by the ICU. The MAL is shown in Figure 3 as unit 305.

The memory read buffer (MRB) is a four-word data buffer. It buffers the data from the memory bus until the cache memory is available for the update operation. The MRB is used as a prefetch memory when prefetching is enabled. The MRB is shown in Fig. 3 as unit 306

The memory bus controller (MBC), which controls the memory bus operations, is shown in Figure 3 as unit 307.

The cache memory unit performs all cache memory functions. It contains the memory array, the tag array, the validity array, the block status array, the LRU array, special registers, and the cache memory controller, all of which are described below.

The memory array is a 64k bit memory array for cached instructions or data. It is organized as two ways of 1024 words. For read operations, the two ways are accessed simultaneously using bits 11-2 of the address, according to the preferred embodiment of the invention. The word in question is selected according to the hit signals from the tag array. For write operations, the correct word is written to the array after the tag access is complete and the hit signals are generated. The memory array is shown in Figure 3 as unit 310.

The tag array stores the cache tags in a two-way, seeded, associative organization. Each way is organized as 256 x 20 bits. Each tag corresponds to a block of 4 consecutive cached words. For each cache access, two tags are accessed simultaneously using bits 11-4 of the address. The tags are compared (in one embodiment of the invention) to bits 31-12 of the address. The hit signals are generated from the comparison results and the configuration bits. The tag array is written each time a miss occurs and a cache block is allocated. The tag is chosen according to bits 11-4 of the address and the replacement algorithm. Address bits 31-12 are written to the tag array. The tag array is shown in Fig. 3 as unit 311.

The validity array, unit 312 of Fig. 3, is a 2k bit array containing one valid bit for each cached word. It is organized as two 1024 x 1 arrays. A valid bit is set for each word as it is written to the cache memory. The valid bit is chosen by the address bits 11-2 (as in the memory array) and the correspondence path. On each cache memory access, two valid bits corresponding to the two paths are checked. A hit signal is generated only if the corresponding valid bit is set.

The block status array, unit 313 in Figure 3, is a 1536-bit array containing 3 block status bits for each cache memory block. It is organized as two 256 x 3 arrays (this corresponds to the tag array organization). The three bits are as follows: Modified, Shared and Locked. The Modified bit indicates that the block is modified and should be flushed back into memory before being replaced. It is used for copyback operations and data consistency operations. The Shared bit indicates that the block is shared. It is used for data consistency operations. The Lock bit indicates that the block is locked and cannot be replaced. It is used to lock important data or instructions in the cache memory.

The LRU array, unit 314 in Fig. 31, is a 356 bit array that stores the LRU bits. It is organized as a 256 x 1 array. Each LRU bit corresponds to a set of two tags. The LRU array is used when the least recently used replacement algorithm is selected. The corresponding LRU bit is updated to reflect the least recently used block of the two blocks in a set. If necessary, the LRU bit determines which block from the set is replaced.

The special register block, shown in Fig. 3 as unit 315, contains all the special registers of the ICU. These are used to program ICU options, control special operations, and hold status information.

The cache control block, unit 316 in Figure 3, contains the control logic for the cache operations.

After listing and describing the data flow through the novel ICU based on Fig. 3, the register structure for supporting the data flow and control of the ICU is explained below.

The preferred embodiment of the ICU contains 8 special purpose registers. These registers select programmable options, support cache control operations, and indicate cache status information. Each register can be read or written by the processor via the processor bus or the memory bus. A cache register read or register write instruction is communicated to the ICU via the appropriate cache instruction protocol on either bus. For the processor bus instruction, the register number is determined by the three least significant bits of the opcode. The instruction transfer protocol and the ICU response are controlled by the register read control and the instruction transfer protocol control, respectively, in the Modb register. For the memory bus instruction, the register number is determined by the three least significant bits of the address. Below, a detailed description of these three example protocols and reactions is given.

During processor bus accesses, all ICU special registers are protected. They can only be accessed when the SUP/*US input signal is HIGH. User mode accesses are not performed. A *CERR response gives an invalid user mode access. The registers are not protected for the memory bus cache instruction.

According to the preferred embodiment of the invention, each register is assigned a number as follows:

Reg. No. Reg. Name

0 Chip selection image

1 Instruction

2 Address operand

3 Counting status

4 Error address

5 Status

6 Mod a

7 Mod b

In the following, only the general function of each register is described, since it is clear to those skilled in the art that special bit assignments can be made for application-specific purposes.

The chip select mapping register is a special register 0.

It determines the address and conditions for the ICU chip select functions. The ICU has two independent chip select functions: for normal cache memory accesses and for cache memory instruction accesses.

For normal cache accesses, the chip select function can be used for cache extensions, cache address space mappings, and multiple cache configurations. In the preferred embodiment of the invention, up to 32 ICUs (16 instruction caches and 16 data caches) can be used without external chip select hardware. be used. The memory access (MA) selection is further affected by the *CSM input signal and a memory bit enable field of the Moda register. If the *CSM input signal is enabled, it must be asserted to enable a memory access. If the *CSM input signal is disabled, it is ignored. The memory bit enable field can selectively enable the comparison of an appropriate address bit with a corresponding (MA) field bit in the chip select memory register. If a bit for comparison is disabled, it is ignored. If all bits are disabled, a match is forced. Note that if *CSM is enabled, it must be asserted and an MA field comparison match must exist for the memory access to be accomplished.

For cache instruction accesses, the chip select function is used to select the correct ICU for access. A cache instruction access is asserted when *CSEL is asserted and enabled, or when the address inputs A31-A14 and CREQTO match the cache instruction addresses and cache instruction address space fields in the chip select map register. In the second case, all caches that match are selected. If the instruction scope includes multiple caches, all selected caches respond. If the instruction scope includes only one cache, only the cache whose address inputs A13-A8 correspond to a particular cache number field of the chip select mapping register will respond.

During initialization, the *CSEL input signal is used to program the chip select map registers of a given ICU. In a typical configuration, a different address bit can be assigned to the *CSEL signal of different ICUs. When *CSEL is asserted and enabled, the ICU treats data accesses as cache memory instruction accesses. After the chip select mapping register has been programmed, the *CSEL input signal can be deasserted and the mapping determined by the chip select mapping register is applied.

The instruction register is a special register 1. It is used to specify an instruction for the ICU. The instruction register is usable for reads and writes like any other special register, but it is automatically loaded for a valid cache instruction. A valid cache instruction is detected when the *CSEL input is driven and activated, or when the address inputs A31-A14 and CREQT0 match the cache instruction addresses and cache instruction address space fields in the chip select map register. In these cases, the instruction is copied from the address inputs A7-A0.

The instruction register can be accessed as a special register to save and restore the ICU state in the event of a processor interrupt during the instruction transfer protocol or in the event of a multiple cache instruction being interrupted. When the instruction register is accessed as a special register, a read or register write cache instruction is submitted to the ICU. Shadow registers are provided to be able to latch the register read instruction and optional operand without destroying the required old contents of the instruction and operand registers. The shadow instruction register is initially loaded with an instruction. For all instructions except the register read and register write instructions, the instruction register is updated when instruction execution begins. For the register read and register write instructions the instruction register is updated only if no other valid instruction is present in the instruction register. If a valid instruction is present in the instruction register, the register read instruction is executed without affecting the instruction and operand registers. This feature is also used to check the status of the ICU without affecting the execution of a cache memory instruction.

An instruction is executed by the ICU every time if all required operands are valid. A detailed description of examples of instructions, required operands and cache memory instruction accesses follows.

The operand register is a special register 2. It specifies an operand for certain ICU instructions. The register contains a bit (OV bit) to indicate the validity of the operand register value. A shadow operand register is included in the ICU, which is used to correctly execute the register read and register write instructions. The shadow operand register is initially loaded with an operand. For all instructions except the register read and register write instructions, the operand register is updated if the validity bit is reset. If the OV bit is set, the ICU delays the *CRDY response until the OV bit is reset (completion of the previous instruction) and then loads the register. For register read and register write instructions, the operand register is only updated if no other valid instruction exists in the instruction register. If another valid instruction exists in the instruction register, the register read and register write instructions are executed without affecting the instruction and operand registers. This makes it possible to save and restore the operand register, if necessary. If necessary, the operand register can be read using the register read or register write instructions.

The count register is a special register 3. It determines the number of words to be processed using certain ICU instructions. The count register is not affected by instruction execution.

The exception address register is a special register 4. It is used to report the address associated with some exception cases. The exception address register is loaded with the exception address. The exception type can be found in the status register.

The status register is a special register 5. It is used to report the status of the ICU and to transfer information between the ICU and the processor in the read tag and write tag instructions (which will be discussed later). Bits are reserved to report the tag value for the read tag instruction and to transmit the tag for the write tag instruction; to report the WAY signal for cached data; to report the valid bits for a block and to transmit the valid bits for the write tag instruction; to report the lock bit for the block and to transmit the lock bit for the write tag instruction; to report the shared bit for the block and to transmit the shared bit for the write tag instruction; to report the modified bit for the block and to transmit the modified bit for the write tag instruction; to indicate whether a hit was detected in the cache; and to indicate protection violations, illegal instructions, memory errors, and parity errors.

The Moda register is a special register 6. It is used to select various ICU options. The Moda register is reset during initialization.

Fields are reserved to: control the global cache operation; to lock all cache locations; to disable the write buffer; and to disable the read-through option.

This register contains a ROM enable bit that has different functions for instruction cache and data cache use ("ROME" bit).

When using instruction cache, if this bit is set, the ICU responds to ROM accesses and caches them. If it is 0, ROM accesses are ignored.

When this bit is set in data cache use, the data cache is enabled for instruction memory accesses (as data). When the OPT inputs indicate an instruction memory access, the ICU treats this as a non-cacheable transaction. The specified address is read on the memory bus and transferred to the processor without being loaded into the cache. If the ROME bit is 0, the ICU ignores this type of instruction.

Additional fields are provided in the register to enable the prefetch option for single accesses; to disable an address wraparound option; to control ICU handling of a single access miss; to control ICU operation when the processor completes a burst mode read request; to enable the prefetch option for burst accesses; and to select the sub-block sizing (SBS).

Note that the subblock size is used in controlling cache reload operations. The number of words to be reloaded into the cache on a single cache miss is determined by the defined subblock size and the information stored in the field control ICU operation for an access miss (e.g., control information such as start and stop at a subblock boundary). Furthermore, the SBS field is used along with the burst mode control information in burst termination control. The inherent block size of the ICU is 4 words, with one tag associated with four data words. The subblock size is either 1, 2, or 4 words.

The Moda register also contains fields to control the expansion of memory bus address transfers; to indicate whether a write mapping option is enabled; and to select the write function options on a global basis.

According to the preferred embodiment of the invention, the writing functions are the following: the flexible, the write-through or the copy-back function.

If a write-through function is selected, each processor write to the ICU is also written to memory. If a copy-back is selected, each processor write hit is written to cache memory and the modified bit is set. The block is copied back to memory only if the block is replaced. If the flexible function is selected, a write-through or copy-back operation for an access can be selected on a per-access basis. The write function for an access is further influenced by the ASTC input signals, the shared block status information, and the write share hit control and the processor status bit control fields. of the Modb register (which will be explained later).

The Moda register also contains a field used to select the block replacement function. This selection is not used for direct mapping organization. In a two-way set-associative organization, if one of the blocks is not valid, it is selected as the new block. According to the preferred embodiment of the invention, the options for the replacement function are: least recently used (LRU), direct, or external.

When the LRU feature is selected, the LRU array is used to select the block to be replaced. The LRU array is updated for each cache memory access. Each set is allocated to one bit. It points to the least recently used block out of the two blocks in a set.

When the direct access function is selected, a pseudo-direct access logic selects the block to be replaced. This logic is a simple flip-flop that changes state at each block cycle and is used for all sets.

When the external function is selected, the WREP input signal is latched to the processor address. The latched value forces the selection of the offset block. This option can be used for cache memory testing and multi-level cache memory organization.

The Moda register contains fields for selecting the cache memory organization (two-way set associative or direct mapped); for selecting the cache memory operation as instruction cache or data cache; for controlling parity generation and checking options and memory bit activation information for activating the corresponding MA bits in the chip selection mapping register for address comparison during memory accesses.

The Modb register is a special register 7. It is used to select various ICU options. A field in the Modb register is allocated to multiprocessor organizations. A detailed description of multiprocessor organizations and the use of this field will follow.

The Modb register also contains a bit for controlling the ICU for input/output data accesses on the processor bus (it is ignored when instruction cache is used); a bit specifying the mode of operation for reading the ICU registers; a bit specifying the protocol for cache instruction transfer on the processor bus; and a bit controlling the byte and half-word requirement within a word for the relevant ICU operations.

The multiprocessor-oriented information in the Modb register includes: a cache-locked enable bit; a bus read monitor enable bit; a write bus monitor enable bit; a field that controls operation of the ICU in the event of a memory bus read match by another master; a field that controls operation for memory bus write operation by another master in the event of a match; a write miss access control that controls memory bus operation for a copyback write miss on write allocation; a write share hit control field that controls operation for a write bit on a shared block; a processor share bit control that, for each processor access, if set, causes a modification of the block status share bit; and an external sharing bit control that controls the allocation of the shared block status by external control. In the external shared Control uses the *HIT signal as an input for memory bus read and/or write accesses. If it is asserted, the data is also present in other caches and the block is given a shared status. If the *HIT input is not asserted, the variable is not present in any cache and the block is given an exclusive status. A detailed description of this feature in the context of ICU multiprocessor support follows.

First, the ICU instruction set is explained.

In the preferred embodiment of the ICU, 20 processor bus cache instructions and 9 memory bus cache instructions are used. The processor bus instructions are used by the processor for special register accesses and for special cache operation requests. The memory bus instructions are issued by special logic on the memory bus for special cache operation requests. In this section, examples of different instruction transfer protocols and an example of a typical processor bus instruction and memory bus instruction set are explained in detail.

The processor bus cache instructions and operands are transferred from the processor to the ICU through a special sequence of processor bus transactions. The instruction is executed each time the required operands are transferred to the ICU.

Some processor bus cache instructions have four optional operation ranges. The instruction range specifies the number of ICUs affected by a cache instruction. The range is defined in the Instruction table designated with (s). Instructions without the (s) designation can only be executed for a specific ICU. The instruction area can be designed as follows: specified (s) Op-Code significant bits Meaning a specific ICU affects all instruction caches affects all data caches affects all caches affects

This flexibility allows a system designer to provide cache instructions that operate on the desired addresses in the appropriate caches. In a multiple ICU environment, it is more efficient to issue a single instruction that executes on all caches simultaneously. For example, the block invalidation instruction with (s) = A (INVBA) invalidates the specified block in all ICUs (in which the block is valid) in parallel.

Most instructions are executed in two cycles. However, exceptions may exist, as explained below. During the execution of the processor bus cache instruction, the ICU may accept additional processor transactions (including new instruction transfers), but in most cases they will be (if specified in the Instruction descriptions do not specify otherwise) are only executed after the processor bus cache instruction is complete. Memory bus transactions are executed during the execution of the processor bus cache instruction. However, because they are not synchronized to instruction execution, the ICU operation reflects the current state of the cache.

All processor bus cache instructions are privileged. If the SUP/*US input is LOW, it is ignored during the execution of the processor bus cache instruction access, and *CERR is asserted in response. The status register is updated with status information for the relevant instructions. In case of an exception, the exception address register and the status register are updated with exception information.

There are several options for communication between the ICU and the processor during execution of the cache instruction. The protocol is defined according to the instruction transfer protocol control (ITPC) and register read control (RRC) bits of the Modb register, as well as the type and size of the cache instruction. All instructions except register reads are transmitted using a write operation. The register read instruction is transmitted using a read and write operation as defined in the register read control bit of the Modb register. A description of these options can be found in the explanation of the register read instruction given later.

The first part of every instruction is the detection of a processor bus cache instruction request. A processor bus cache instruction request can be either a read or a write processor bus access. It is detected by the ICU in two cases: 1) *CSEL is asserted made and activated or 2) the address inputs CREQT0 and CREQT0 match the cache instruction address and cache instruction address space fields in the chip select mapping register.

If no operand is required for instruction execution, the transfer is completed in a single cycle. In this case, the value on the cache bus is irrelevant and instruction execution starts immediately.

If operands are required, there are two optional transfer protocols supported by the ICU. The protocol is selected according to the instruction transfer protocol control bit of the Modb register.

When ITPC is 1, the cache bus is used for operand transfer. The processor bus uses a normal write operation, and the processor address and data buses are both used. The ICU latches the operand value from the cache bus. For an ICU used as an instruction cache, external transceivers are required to transfer the data from the ICU data bus to the cache bus. This option is the natural choice for the ICU used as a data cache. For an ICU used as an instruction cache, using external transceivers also provides a more efficient protocol.

If ITPC is 0, the cache memory bus is not used. The operands are transferred on the processor address bus. A special two-cycle protocol is required for instruction and operand transfer. After valid information is latched, the ICU awaits a special data transaction on the processor bus. The CREQT input signals must specify a memory data transaction, the option input signals must specify a cache memory operand transfer. and the address bus contains the operand. This special write transaction is detected by the ICU and the operand on the address bus is latched. Note that the above transaction must be ignored by all other elements coupled to the processor bus. This option is less efficient than the other, but it does not require any transceivers for the ICU used as an instruction cache.

Both options can be chosen independently for an ICU used as a data cache or for an ICU used as an instruction cache. However, from a system programming standpoint, it may be desirable to access both caches in a similar manner. If this is the case, both caches can be programmed to respond to the same protocol.

If a count operand is required for the instruction to execute, a register write instruction must be executed to write it into the count register before instruction execution begins. The instruction is executed by the ICU every time the instruction and all required operands are valid.

Processor interrupts may occur during the cache instruction transfer protocol. The preferred embodiment of the ICU includes logic to handle such cases. The instruction register, operand register, and count register can be read in such a way that their contents are saved unaffected using the register write instruction. The instruction valid, operand valid, and count valid bits indicate the validity for the corresponding register. The rescue and recovery operations allow the instruction transfer protocol to continue from the point of interruption.

In the following, a set of processor bus cache instructions useful for an embodiment of the invention is listed mnemonic and with a brief description of their purpose in a table: Mnemonic Description no operation invalidate word invalidate block invalidate multiple invalidate all commit word if modified commit block if modified update memory and invalidate update memory and invalidate multiple value lock block unlock block read block status write block status commit word if match read tag write tag preload cache memory reset read register write register

It should be noted that the symbol (s) in the mnemonic instruction expression indicates the instruction scope as previously defined and the symbol (i) in the RDR and WRR instructions indicates the register number specified by the 3 least significant bits of the op-code.

It should also be noted that certain operands (although not discussed here) are specified according to instruction requirements. If more than one operand is to be specified, a WRR instruction is required to load the second specified operand.

At the functional level, the following actions occur when the instructions are executed:

No Operation (NOP) - The ICU will not perform any operation for this instruction.

Invalidate word (INVWO, INVWI, INWWD, INVWA) (note the different ranges) - The word specified by an address operand is invalidated (the corresponding valid bit is reset).

Invalidate Block (INVBO, INVBI, INVBD, INVBA) - The four-word block specified by the address operand is invalidated (all corresponding valid bits are reset).

Multiple Invalidate (INVMO, INVMI, INVMD, INVMA) - Sequential multiple four-block words are invaded by the ICU. Each individual operation is similar to the INVB instruction.

The instruction is executed in several cycles (two cycles for initialization + one cycle per four-word block). For this instruction, the count register must contain a valid count. The count register is loaded using the register write instruction. The count valid bit remains after the instruction is executed. set. To ensure correct execution, the count register must either be loaded before the INVM instruction is requested, or it must contain the correct value from a previous operation. This instruction can be used to invalidate a page frame. The count register must contain a number of four-word blocks in a page (page size in bytes divided by 16).

Invalidate All (INVAO, INVAI, INVAD, INVAA) - This instruction invalidates all words in the cache memory. All valid bits are reset

Transmit Word If Modified (SWMO, SWMI, SWMD, SWMA) - If the word specified by the address operand is present in the cache and the modified bit for the block is set, it is written to the corresponding address in the memory.

Transmit Block If Modified (SBMO, SBMI, SBMD, SBMA) - If the four-word block specified by the address operand is modified, all valid words are written to the corresponding addresses in memory.

Refresh Memory and Invalidate (UPMIO, UPMII, UPMID, UPMIA) - If the four-word block specified by the address operand is modified, all valid words are written to the corresponding addresses in memory. Then all valid bits are reset. The write operation is performed using a burst mode or a single memory bus write access (depending on the number of valid words) after the memory bus has been granted access to the ICU.

Updating Memory and Invalidating Multiple Values (UPIMO, UPIMI, UPIMD, UPIMA) - Multiple sequential memory update and invalidate operations are performed by the ICU. Each individual operation is designed in a similar manner to the update memory and invalidate instruction. The instruction is executed in multiple cycles (two cycles for initialization plus one cycle per four-word block). For this instruction, the count register must contain a valid count. The count register is loaded using the register write instruction. The count valid bit remains set after the instruction is executed. To ensure correct execution, the count register must either be loaded before the INVM instruction is requested, or it must contain the correct value from a previous operation. This instruction can be used to update memory and invalidate a page frame. The count register must contain a number of four-word blocks in a page (page size in bytes divided by 16).

Locking the block (LCKO, LCKI, LCKD, LCKA) - If the four-word block specified by the address operand (or a portion of that block) is present in the cache, the corresponding block status lock bit is set.

Unlock Block (ULCKO, ULCKI, ULCKD, ULCKA) - If the four-word block specified by the address operand (or a portion of that block) is present in the cache, the corresponding block status lock bit is reset.

Read Block Status (RBST0, RBSTI, RBSTD, RBSTA) - The specified word address is checked for its presence in the cache memory and the status register is updated accordingly.

Write Block Status (WBSTO, WBSTI, WBSTD, WBSTA) - The block containing the specified word address is checked for its presence in the cache memory and the block status bits are updated based on the value of the bits in the status register.

Send Word If Hit (SWH) - If the word specified by the address operand is present in the cache memory, it is written to the corresponding address in the memory.

Read Tag (RTAG) - This instruction is used to read a specific tag in the cache memory.

Write Tag (WTAG) - This instruction is used to write a specific tag in the cache memory.

Preload (PRLD) - Preload is a special operation that can be performed to load a cache with certain data variables or instructions before they are needed. The operation is performed under software control. The addresses of the required variables or instructions are supplied by the user. It should be noted that the preload operation is different from simple prefetch operations. A prefetch is usually performed under hardware control, and the prefetched addresses are in close proximity to the address of the original memory request.

The user and compiler knowledge of the program should be used to predict the most useful instructions or data variables. The corresponding addresses are preloaded into the instruction and data caches before the program execution is started. The operation can be performed under cache control without processor intervention. This allows for better Utilization of cache memory and greater overall performance.

The prefetch operation, which is novel in itself, is described in the context of the RISC/SIP architecture included here. It can also be used in other cache memory systems.

The instruction is initiated by the processor by sending the opcode and operands to the appropriate cache unit. Two operands are required: an address operand and a count operand. Multiple sequential words are loaded into the cache using the memory bus read burst transaction under ICU control. The address operand specifies the starting word address. The count register specifies the number of four-word blocks. When the highest possible address is reached, a wraparound is performed.

The instruction is executed in multiple cycles (two cycles for initialization plus one memory bus burst read access per word). This instruction also requires the count register to contain a valid count. The precharge instruction can be performed in several ways. The basic options are the following:

A simple method of using the preload instruction does not require any special cache configuration and can be used with any cache system. In this method, the preload instruction is executed under software control before the program is executed. The instruction can be issued as part of the contextual switch. Since the caches are preloaded, the cold start effect is minimized. The main disadvantage of this method is that the preload operation induces other may interfere with cache memory operations required by the processor.

This limitation can be overcome by using a more complex cache configuration. This configuration (called switchable caches) requires more than one cache for each processor and a method for switching between caches. The switchable cache configuration allows multiple caches to operate in the same address space. Two or more caches are arranged in parallel, but only one of the caches is designed for processor memory access responses. The other cache or caches can be programmed to preload the variables or instructions required for the next program (or execution). Before execution of the next program starts, the correct cache (containing the preloaded data) is activated and the other caches are deactivated.

The implementation of this scheme is fully supported by the ICU. All required support is implemented on the single chip. Disabling or enabling an individual ICU can be done by programming an operating state register. The precharge instruction is implemented to support this scheme. In particular, the ICU can execute the precharge instruction even if it is disabled for normal cache operations. Two or more ICUs can be placed in parallel, and only one can be enabled for normal cache operations while the other performs precharge operations. (No gluing logic is required).

This configuration can provide a significant performance benefit because the preload operations occur with minimal impact on the execution of the current program.

Reset (RST) - The reset instruction performs the same function as performed by asserting the *RESET input signal. The ICU is initialized. The RST instruction is executed immediately after it is accepted. A multiple instruction (INVM, UPIM, PRLD) is terminated.

Read Register (RDR) - The Read Register instruction is used to read the ICU's special registers. The number of the special register is determined by the opcode. The ICU responds to this instruction in different ways, depending on the state of a Register Read Control (RRC) bit in the Modb register. If RRC is 1, a Read instruction with the instruction on the address bus causes the instruction to be initiated. If RRC is 0, main memory is used to read the registers.

Write Register (WRR) - The Write Register instruction is used to write to the ICU's special registers. The number of the special register is determined by the op-code. The data is specified as an instruction operand. The WRR instruction is executed immediately after it is accepted. If a valid instruction and operand are present in the instruction and operand registers, it is executed without affecting their contents. This feature can be used to restore the ICU registers.

As mentioned earlier, the memory bus cache instructions are executed by special logic on the memory bus. This logic must be able to route the instruction to the appropriate ICU. All ICUs in the system that detect a valid instruction on their inputs will execute it. There are no equivalent concepts regarding processor bus instruction scope and privileged instructions on the memory bus.

All memory bus cache instructions can be sent to the ICU if it is the bus slave using a specific cache instruction transfer memory bus transaction. The block state write instruction can also be sent if the ICU is the bus master by asserting the *VSI input. The instruction is executed whenever the required cache resources are available after the instruction and operands are accepted. All instructions are executed internally in two cycles. If a memory bus operation is required to execute the instruction, the cycle number for the bus operation must be added.

The memory bus cache instructions are executed independently of other ICU operations occurring on the processor bus (including the processor bus cache instructions). The memory bus instructions and the processor bus operations are executed according to the order in which they are received. The result of the memory bus instruction reflects the current state of the cache. If a memory bus cache instruction is accepted during the execution of a multiple processor bus cache instruction, it is executed without affecting the execution of the multiple instruction.

All memory bus cache instructions, except for writing a word to cache, have an equivalent processor bus cache instruction with a similar name. These instructions have a similar effect on the internal cache, but the processor bus and memory bus operations are different.

All memory bus cache instructions are transferred via a single cache memory instruction transfer memory bus Transaction committed. If the ICU is not the bus master, the assertion of *VSI causes a cache instruction transaction on the memory bus. During the first cycle of the transaction, the MRW, MREQT, BSTC signals and the address are latched. The MRW and MREQT signals specify the instruction. The BSTC signals specify the block status for the relevant instructions. The address is used as the address operand for the relevant instruction. If the instruction requires a data operand, the data is latched during the second cycle.

When the ICU is the bus master and issues a read request for a reload operation, the *VSI input signal has a special function. If it is asserted before the transaction is complete (the last *MRDY signal has not been accepted), then the BSTC signals are latched and a write block status instruction is executed. The address operand is the block address corresponding to the address passed by the ICU for the reload operation.

In the following, a set of memory bus cache instructions useful for an embodiment of the invention is listed mnemonic and with a brief description of their purpose in a table: Mnemonic expression Description no operation Submit word if match Submit word if modified Mnemonic Description Submit block if modified Invalidate word Invalidate block Write block status Write register Update memory and invalidate Read block status Read register Write word to cache

Note that the instruction codes are designed so that MRWO is consistent with other memory bus operations. If MRWO is LOW, the direction is from the ICU to the memory bus, and if MRWO is HIGH, the direction is from the memory bus to the ICU.

At the functional level, the following actions occur when the instructions are executed:

No Operation (NOP) - This action has no effect on the ICU. The memory bus cache instruction transaction protocol is executed as for any instruction.

Send Word If Hit (SWH) - If the word specified by the address operand is present in the cache memory, the *HIT signal is asserted. The word is addressed on the memory address bus, which is shared by Block status used and modified bits are driven to the BSTC signals and *MRDY is asserted.

Send Word If Modified (SWM) - If the word specified by the address operand is present in the cache memory and the modified bit for the block is set, the *HIT and *MRDY signals are asserted and the shared block status and modified bits are driven to the BSTC signals. Then the word is written to the corresponding address in memory.

Transmit Block If Modified (SBM) - If the four-word block specified by the address operand is modified, the *HIT and *MRDY signals are asserted and the bits used with shared block status and modified are driven to the BSTC signals. Then all valid words are written to the corresponding addresses in memory.

Invalidate Word (INVW) - The word specified by the address operand is invalidated (the corresponding valid bit is reset). The *HIT signal is driven according to the hit or miss conditions and *MRDY is asserted after instruction execution is complete.

Invalidate Block (INVB) - The four-word block specified by the address operand is invalidated (all corresponding valid bits are reset). The *HIT signal is driven according to the hit or miss conditions and *MRDY is asserted after instruction execution is complete.

Write Block Status (WBST) - This instruction can be executed when the ICU is the bus slave or the bus master. If the ICU is the slave, the address operand is specified by the memory bus transaction. In this case the block containing the specified word address is checked for presence in the cache memory. If the block is present, the *HIT and *MRDY signals are asserted and the block status bits are copied from the BSTC signals. If the block is not present, the Hit signal is deasserted and *MRDY is asserted. The Hit and Valid bits of the status register are reset.

When the ICU is the bus master and issues a read request for a reload operation, the *VSI input signal has a special function. If it is asserted before the transaction is complete (the last *MRDY has not been accepted), the BSTC signals are latched and the block status write instruction is executed. The address operand is the address passed by the ICU for the reload operation. In this case, the block containing the specified word address is always present in the cache (since it is being reloaded). The block status bits of this block are copied from the BSTC signals. The status register is not affected.

Write Register (WRR) - The Write Register instruction is used to write the special registers of the ICU.

Update Memory and Invalidate (UPMI) - If the four-word block specified by the address operand is modified, the *HIT and *MRDY signals are asserted and the bits used and modified with shared block status are driven to the BSTC signals. Then all valid words are written to the corresponding addresses in memory and then the valid bits are reset

Read Block Status (RBST) - The specified word address is checked for its presence in the cache memory. The Block status bits are driven on the BSTC signals. The *HIT and *MRDY signals are also driven accordingly.

Read Register (RDR) - The Read Register instruction is used to read the special registers of the ICU.

Write Word to Cache (WRW) - If the word specified by the address operand is present in cache, the *HIT signal is asserted and the supplied data is written to cache. The two least significant bits of the address are ignored. Note that the address cycle is specified by the *VSI input signal and not by the *MASTB signal. The data is specified by the value on the memory bus during the cycle following the address cycle. If the word is not present in cache, the *HIT signal is invalidated and the hit and valid bits of the status register are reset. The *MRDY signal is asserted when the ICU latches the data from the memory bus.

Having concluded this description of a convenient and practical instruction set for use with the preferred embodiment of the invention, there follows a brief description of the data formats and data manipulation mechanisms supported by the new ICU.

As previously explained, a word is defined by 32 data bits. A half word consists of 16 bits. A byte consists of 8 bits. The ICU provides direct support for word, half word and byte accesses. On the processor bus, the access length is defined according to the OPT input signals. The access length is only effective for simple data memory accesses. For all other processor bus accesses (including burst mode memory accesses) it is ignored and a memory length is assumed. On the memory bus, the access length is defined according to the MDLN signals.

The numbering conventions for data units within a word in the preferred embodiment of the invention conform to the RISC/SIP definitions set forth in the application describing a RISC processor, incorporated herein. Bits are numbered in increasing order from right to left. Bytes and half words may be arranged either right to left or left to right, as controlled by the byte order bit of the Modb register.

The preferred embodiment of the ICU contains the necessary hardware to fully support byte, half-word and word accesses. The different data types must be aligned on their natural address boundaries. Accesses that do not occur on their natural address boundaries are reported to the error and status registers; however, the access is performed as if it were correctly aligned (i.e., the corresponding address bits are ignored).

During memory byte read operations on the processor bus, the alignment hardware moves the byte to the lowest order (rightmost) location within a word.

During memory halfword read operations on the processor bus, the alignment hardware moves the halfword to the lowest order (rightmost) location within a word.

In case of a memory read miss, the ICU uses word accesses to the memory bus for the reload operation. Byte and half-word accesses are used for non-cacheable read accesses. The byte or half-word is aligned before being given to the processor. The access length is transmitted from the processor bus (OPT input signals) to the memory bus (MDLN signals).

For memory write operations, the ICU writes bytes and half-words to the appropriate cache locations. For a byte write, the byte from the low-order byte location is duplicated to all other byte locations within a word. The appropriate byte write enable signal is activated to write the correct byte to the cache. For a half-word write, the half-word is duplicated from the low-order to the high-order half-word. It is then written to the cache by activating the appropriate half-words.

For write-through and non-cacheable write accesses, the access length is communicated from the processor bus (OPT input signals) to the memory bus (MDLN signals). The duplicated bytes or halfwords are placed on the memory bus. The memory controller decodes the address and length and asserts the correct write enable signals.

It should be noted that although the ICU supports byte and half-word accesses, the user can decide whether the system supports them. If the decision is to support only word accesses, the OPT and MDLN inputs must always specify word accesses.

In the directly following section of the detailed description, the ICU operation is explained for the different cases of cache memory accesses on the processor and memory buses.

The processor bus accesses are either single, pipeline or burst mode accesses.

All accesses to the processor bus are initiated by the processor. The ICU supports the three access protocols as defined in the accompanying applications previously incorporated by reference.

Single accesses are used for simple data read and write accesses as well as for special instruction accesses.

Pipeline accesses are supported by the ICU. The ICU locks the address. (*PEN should be controlled by external logic). The processor can use the address bus to start another ICU access. The address of a pipeline access is used by the ICU for the tag comparison function, pipelined with the previous access. In the case of a cache hit, a cycle is required to complete the pipeline access after the first access has completed. In the case of a cache miss, the memory bus access starts one cycle earlier.

Burst mode accesses are used for instruction accesses and multiple data accesses. In these accesses, the address for the first word is transferred, and then sequential addresses are assumed for the following words. Burst mode read and write accesses are fully supported by the ICU. The maximum rate of one word per cycle is achieved with cache hits.

A single-memory read access is used to read data variables from a data cache. (The RISC processor included here executes all instruction read protocols using the burst mode read protocol.) The address is used to find the cache memory for the requested word. If the word is found (hit), the data is fed to the processor and the *CRDY output signal is asserted. Alignment is performed for byte and half-word accesses. For simple memory read accesses, the ICU responds in two cycles.

If the requested word is not found in the cache (miss), the ICU initiates a specific miss handling procedure. The shared block status bit is updated on each miss. Furthermore, the LRU bit associated with the set is updated on each access to reflect the most recently used block.

A burst mode memory read access is treated by the ICU as a series of sequential memory read accesses. In the first cycle of a burst mode read access, the address for the first word is transmitted from the processor. When the ICU detects a burst mode read access, it latches the address and asserts the *CBACK signal. The address is compared and automatically incremented for each word in the burst. In the case of a cache hit, the ICU responds with the first word in two cycles. An address can be incremented and compared at a maximum rate of once per cycle. This makes it possible to achieve a rate of one cycle per word in the case of cache hits. Note that a one-cycle access is maintained even in the case of a block boundary violation.

If a miss is detected at any point during the burst mode access, a specific burst miss handling procedure is initiated.

During the memory bus burst mode access, the next word address (current word plus 1) in the cache memory checked. If a hit is detected during the memory bus burst mode operation, the memory bus access is terminated and the data transfer is continued from the cache memory. The miss and hit cases and the transfers from one to the other are transparent to the processor (only the access time is affected).

A burst mode read access may be terminated by the processor at any point by disabling *BREQ. Another word is processed as defined in the burst mode protocol of the RISC processor included herewith.

A single-cycle memory write access is used to write data variables into the cache memory. The addresses and data are latched by the ICU in the first cycle of the access, and the *CRDY signal is asserted during this cycle (single-cycle writes). Note that the *CRDY signal is asserted regardless of the hit or miss conditions.

In case of a cache hit, the data is written to the cache in the second cycle. The write function is determined according to the ASTC inputs, the write function field of the Moda register, the write share hit control and processor share bit control fields in the Modb registers, and the block status share bit. There are three possible write functions: exclusive write-through, exclusive copy-back, and sharing.

For an exclusive write-through access, the data is also written to memory. If the write buffer is enabled, the data is written to the write buffer. If it is disabled, the write operation is not buffered, as described below in connection with the description of the write buffer. In both cases, the memory bus access is started when there are no other memory bus operations that must be executed earlier and when the memory bus is available.

For an exclusive copyback write access, the data is written only to the cache memory and the modified bit is set. The data is written to memory when the block is replaced.

In the case of a shared write access, a write-through or write broadcast access is always performed on the memory bus. In this case, the write shared hit control field of the Modb register, and not the write function field, controls the ICU operation.

In the case of a cache miss, the ICU operation is determined according to the write allocation bit of the Moda register. If write allocation is enabled, a cache block is allocated for the missed block and a miss procedure is initiated. The miss procedure is similar to the memory read miss procedure. After the miss procedure is completed, the cache operation continues as previously described for the write hit case.

If write mapping is disabled, no block is allocated in the cache. The data is just written to memory as explained for the write-through operation. Note that in this case, a copy-back write is treated as a write-through access.

The shared block status bit is updated on every miss. It can also be updated on a cache hit if the corresponding bit of the modb register is set.

The LRU bit associated with the set is updated on each access so that it reflects the most recently used block.

A burst mode memory write access is treated by the ICU as a series of sequential memory write accesses. In the first cycle of a burst mode write access, the address and data for the first word are transmitted by the processor. When a burst mode write access is detected by the ICU, it latches the address and data and asserts the *CRDY and *CBACK signals. The address is compared and automatically incremented for each word in the burst.

In the case of a cache hit, the ICU writes the first word into the cache during the second cycle. An address can be incremented and compared at a maximum rate of once per cycle. This makes it possible to achieve a rate of one cycle per word in the case of cache hits. Note that a one-cycle access is maintained even in the case of a block boundary violation. A memory bus write operation can also be started under the same conditions as for single-memory writes. If the write buffer is enabled, it is used to buffer up to four writes. The memory bus access is a burst mode write. The conditions for the memory bus operation are checked for each word in the burst and the memory bus operation is affected accordingly.

If a miss is detected at any point during the burst mode access, the ICU operation is determined according to the write allocation bit of the Moda register. If write allocation is enabled, a cache block is allocated for the missed block and a miss handling procedure is initiated. The memory bus access consists of either read or read to modify, depending on whether the write miss memory access control bit of the Modb register is HIGH or LOW, respectively. After the miss handling procedure is completed, the cache operation continues in the manner described for the hit case. Note that in this case, each missed sub-block is first read into the cache and then written. The memory bus operation is not a continuous burst.

If write mapping is disabled, no block is allocated in the cache. The data is written to memory only using a burst mode write operation. The conditions for the memory bus operation are checked for each word in the burst and the memory bus operation is affected accordingly.

The next word address (current word address plus 1) is checked in the cache for each word write. If a hit is found after one or more misses, the ICU continues its operation in the manner described for the hit case. The miss and hit cases and the transfers from one to the other are transparent to the processor (only the access time is affected)

A burst mode write access can be terminated by the processor at any point by disabling *BREQ. The ICU processes the last word write and terminates the memory bus burst mode access if necessary.

A variety of other access operations supported by the preferred embodiment of the invention are described below.

A non-cacheable memory access is supported. It is used to bypass the cache memory for special variable accesses. During this access, the cache memory is not searched for the requested data. A memory access is started to read the data in the memory or write it to it. No block is allocated in the cache memory for this data.

Instruction ROM accesses can optionally be supported. These accesses are operated by an instruction cache as a regular memory read access. In the case of a miss, the memory bus access is referred to as a ROM access. The ICU can be programmed to ignore ROM accesses.

Input/output accesses can optionally be supported and treated as non-cacheable accesses by a data cache. The ICU transfers the access to the memory bus with I/O information. The ICU can be programmed to ignore input/output accesses.

Kcprocessor transfers are ignored by the data cache.

Furthermore, a memory access is supported, which can be specified as a lock access. This is done by setting the *LOCK input signal. A lock access can be used to access semaphores and other synchronized shared variables. Lock accesses are controlled by the Modb register.

Instruction memory access as data is supported. This is a special data access used to read and write the contents of an instruction memory. It is indicated by a special code on the OPT input signals.

A debug module access is also supported. This is a special data access used to access the RISC/SIP debug module. It is indicated by a special code on the OPT inputs. The ICU drives the *CRDY signal for this access. *CRDY is driven HIGH for four cycles and then asserted for one cycle. This is done to allow the introduction of the debug module into the cache memory system without affecting the *RDY logic of the processor.

In addition to the above features, a cache instruction access is supported. This access is used to communicate process bus cache instructions to the ICU.

With regard to memory bus accesses, it is important to emphasize that the memory bus is used for both the ICU's master cache and slave caches. Memory is accessed by an ICU bus master by issuing a memory bus access. The ICU acquires bus master status by asserting the *MBUSR (bus request) output and waiting for *MBGRT (bus grant). An ICU bus slave can monitor memory bus accesses for cache consistency purposes. Cache instructions can be activated by special accesses to the memory bus.

The following explains read accesses, write accesses and read for modification accesses that are carried out with the support of the ICU.

A memory bus read access is initiated by a cache master for a reload operation and for non-cacheable accesses. All reload operations use the access length of words. For non-cacheable For accesses, the access type and appropriate length are conveyed from the processor bus to the MDLN, MREQT, and *MLOCK memory bus signals. For the reload operation, a burst mode access is used if more than one word is required. In all other cases, a single access is used.

The reload operation depends on the original processor bus operation. It differs for single accesses and burst mode accesses£

In the event of a cache miss during a processor bus single-memory read operation, the start and end addresses and address wraparound or non-wraparound are controlled by the single-miss control (SMC) and sub-block sizing (SBS) fields of the Moda register.

In the event of a cache miss during a processor bus burst mode read access, a burst mode access to the memory bus is started for the reload operation. The reload start address is always that of the missed word. The burst end address is controlled by the Moda register.

When the ICU is the bus master memory and issues a read request for a reload operation, the * VSI input signal has a special function. If it is asserted before the transaction is complete (the last *MRDY has not been accepted), then the BSTC signals are latched and a special block state write instruction is executed.

The following describes the operation of a slave cache memory for memory bus read accesses in connection with the ICU multiprocessor support.

First, write accesses are explained. A write operation is initiated by the cache master memory for write-through and non-cacheable accesses, modify block copy-back to memory and shared block write hit operations. A burst mode access is initiated for the modify block copy-back operation and for burst mode write accesses to the processor bus. In all other cases, a single access is initiated. For single accesses, access type and length are communicated from the processor bus to the MDLN, MREQT and *MLOCK memory bus signals.

A burst mode write access to the memory bus starts at the requested starting word address and stops at the last word to be written to memory. It is not affected by the Moda options as in the case of burst mode read accesses.

In case of a hit on a shared block, a write-through operation is initiated under control of the Modb register, depending on the value of the write-sharing-hit-control field of the register.

The following describes the operation of a Siave for memory bus write accesses in connection with the ICU multiprocessor support.

A read to modify is a special read operation. It is used by the ICU in the event of a miss in a copyback write operation under the control of the Modb register. The master cache indicates that the block will be modified after the read is completed. In all other respects, the master operation is similar to the read access.

When the ICU is the bus master and issues a read-to-modify request for the reload operation, the *VSI input signal has a special function. If it is asserted before the transaction is complete (the last *MRDY has not been accepted), then the BSTC signals are latched and a special block state write instruction is executed.

The following describes the operation of a slave cache memory for modification accesses in connection with the ICU multiprocessor support.

Two additional operations are supported by the preferred embodiment of the ICU, namely a write broadcast operation and a memory bus cache instruction access.

A write broadcast operation is initiated by the ICU only in the event of a write hit on a shared block, under the control of the modb register. The difference between a write broadcast and a regular write is that a write broadcast does not update memory. In all other respects, the operation is similar to a write access.

A memory bus cache instruction access can be asserted from the memory bus by external logic. If the ICU is not the bus master, the assertion of *VSI causes a cache instruction transaction on the memory bus. During the first cycle of the transaction, the MWR, MREQT, and BSTC signals and the address are latched. The MWR and MREQT signals specify the instruction. The BSTC signals specify the block status for the relevant instructions. The address is used as the address operand for the relevant instruction. If the instruction requires a data operand, the data is locked during the second cycle.

The preferred embodiment of the ICU follows the following priority rules regarding the various cache memory accesses:

1. All access is handled on a first come, first served basis.

2. A second access can be started in a pipelined manner while the first access is completing. The tag and the memory arrays can handle a different access in each cycle.

3. If two accesses, one to the processor bus and one to the memory bus, require a tag array access at the same time, the processor bus has priority only if it is a primary (non-pipelined or continuous burst) memory access. The memory bus access has priority in all other cases.

4. Responses to processor bus accesses are always in the order they are received. If a hit occurs in the cache for a pipelined or continuous burst access, the response is delayed until the primary access is completed. Note that the pipelined or continuous burst access may complete after the response to the primary access has been issued, but before it is fully completed. This occurs for primary write accesses, before the write has been executed on the memory bus, for reload operations, after the required data has been issued to the processor. and in executing some of the special instructions.

Those skilled in the art will appreciate that the ICU's special purpose registers can accommodate programmable option selection and status reporting. The cache functions can be selected using programmable options. The cache write function can be selected as write-through, copy-back, or flexibly on a per-access basis. A write-mapping or non-write-mapping option can be selected. The replacement algorithm can be programmed as LRU, direct, or external device. A flexible prefetch function can be selected. The read-through option can be enabled. A four-word read buffer is provided to support efficient prefetch and read operations.

As already explained, the option bits for option selection are defined and stored in the Moda register.

As previously stated, by comparison with the prefetch operation, a prefetch operation is defined as the fetching of variables or an instruction before it is requested. The ICU contains the hardware to support several programmable prefetch options. It also contains a memory read buffer that is used as a prefetch buffer. Prefetched words can be saved in the prefetch buffer if the cache array is not available for updating. Any of the following prefetch options can be used independently or in any combination.

The simplest form of prefetching can be achieved by using a sub-block size larger than one word, The ICU reloads the sub-block in case of a miss. The words in the same sub-block as the requested word are prefetched.

The Moda register controls the operation of the ICU for single-access misses.

The Moda register also controls the ICU's operation for a miss on a burst mode access. If the burst is suspended by the processor, the cache can prefetch more words before the memory bus burst is stopped. In this case, the prefetch can advance to the end of the same sub-block or the next sub-block.

The Moda register also enables the prefetch option for single-access cache hits and thirsty-access cache hits.

In addition to the prefetch, a reload operation is defined under control of the programmable Moda register.

The reload operation depends on the original processor bus operation. It is different for single accesses and burst mode accesses.

In the event of a cache miss during a processor bus single-memory read operation, the start and end addresses as well as address wraparound or non-wraparound are controlled by the Moda register.

In the event of a cache miss during a processor bus burst mode read access, a burst mode access to the memory bus is started for the reload operation. The reload start address is always that of the missing word. The burst end address is also controlled by the Moda register.

Before describing in detail how the ICU supports multiprocessor operations, the criteria for the ICU write buffer and ICU initialization and reset are listed.

The ICU contains a 4 location write buffer. It can buffer up to four write addresses (address, control and data). The write buffer can be disabled by setting a bit in the Moda register.

When enabled, the write buffer is used to buffer write accesses to the memory bus. For write-through and write-broadcast accesses, four individual write accesses can be buffered. The write contents wait in the write buffer until the bus is available. This can provide a significant performance improvement when using a write-through cache or when there are numerous write-broadcast operations.

The write buffer is also used to buffer a modified block before it is written to memory. In the event of a miss, if a modified block is chosen as a replacement, it is placed in the write buffer. The read operation for the missed sub-block is started before the write. This feature allows the ICU to respond more quickly to the processor request.

If the write buffer is full, the ICU can still process another cache access as long as the memory bus is not requested (read hit or copyback write hit). If the memory bus is requested for another write operation, the cache waits until there is available space in the write buffer for the write. buffer is present. All further requests are only processed after the write buffer is empty. This is necessary to ensure correct sequencing of requests, ie a miss in a memory read operation waits until all writes have been completed so that an updated memory is read.

When the write buffer is disabled, no write accesses are buffered. The write operation on the memory bus is started as soon as the bus is available. The ICU can still process another cache access as long as the memory bus is not requested (read hit or copyback write hit). If the memory bus is requested, the cache waits until the previous write operation is completed.

As for initialization, the ICU must be initialized when power is first applied. If necessary, it can be initialized at a later time.

There are two methods for initializing the ICU, asserting a *RESET input signal or issuing a reset instruction. The two methods have exactly the same effect on the ICU. According to the preferred embodiment of the invention, a special initialization sequence is performed in the following manner:

1. Any cache operation or cache instruction currently in progress is suspended.

2. Any memory bus operation is suspended.

3. The chip select disable and chip select for memory access enable bits stored in the chip select mapping register are reset

4. The instruction and operand validity bits stored in the instruction register are reset

5. An instruction count validity bit stored in the count register is reset

6. The parity error, memory error, illegal instruction and protection violation bits of the status register are reset.

7. All Moda register bits except the read-only memory enable bit (ROME) and the bit that indicates whether the cache is an instruction cache or a data cache (ID bit) are reset

8. All modb registers are reset.

9. All valid bits are reset

For a correct reset operation, the following conditions should be met:

1. The *IREQ input of all ICU data caches in the system must be tied LOW. The *IREQ signal of all instruction caches must be tied to the *IREQ output of the processor.

2. The CREQT1 signal of only one instruction cache must be tied to HIGH if the reset ROM is placed on the memory bus. All CREQT1 signals must be tied to LOW if the reset ROM is placed on the processor bus.

3. The chip select mapping register of different ICUs must be programmed to point to different addresses for memory accesses and cache memory instruction accesses. This can be done by using the *CSEL input signal. A simple configuration is possible that does not require any external hardware. The *CSEL input signal of different cache memories can be coupled to different address bits and use the corresponding addresses. After the initial register programming is completed, the *CSEL input signal can be disabled.

4. Programming the ICU registers must be the first sequence of operations after reset. No memory accesses (except instruction ROM accesses), I/O or coprocessor accesses may be performed until the ICUs are configured appropriately for the particular system.

5. If a data transfer controller (DTC), which is discussed in the co-pending application incorporated herein in connection with the DTC, is present in the system, the Modb register must be programmed before a DTC access is made. If the DTC is placed on the processor bus, it must be programmed to respond to I/O addresses. (The ICUs must be programmed to ignore the 1/0 accesses.)

The multiprocessor support features of the ICU are explained below.

From a caching perspective, the main problem of multiprocessor organizations is data consistency. This problem occurs when more than one cache contains a copy of the same memory location and one of the caches is modified by its processor. Then the other caches contain an outdated (not updated) copy of the data. The novel ICU architecture addresses this problem. Those skilled in the art will appreciate that the multiprocessor support structures included in the novel ICU can also be used in other multiprocessor cache memory environments.

The core idea behind ICU multiprocessor support is to avoid expensive features in order to provide a high performance, high efficiency multiprocessor cache memory system. The features have sufficient flexibility so that the ICU imposes minimal restrictions on the multiprocessor system organization. Choosing the appropriate way to use the multiprocessor system features is simple. It is done under software control by programming option bits in the on-chip special registers.

Fig. 4 is explained below.

Figure 4 shows a typical diagram of a multiprocessor system using a shared bus. Two or more processor groups can share the same bus (two are shown in the figure). Each processor group consists of one processor and two ICUs. One ICU is used as an instruction cache and the other as a data cache. The processor address bus (A) is shown coupled to the address bus (A) of the two ICUs. The processor instruction bus (I) is coupled to the instruction cache cache bus (CB). The processor data bus (D) is coupled to the data cache cache bus (CB). The ICUs' memory buses (MEMAD) are both coupled to the shared memory bus. Many variations of this basic arrangement are possible.

It should be recalled that according to the preferred embodiment of the invention, each cache memory block is assigned two block status bits and four validity bits. The validity bits indicate the validity of the words in the block. Each validity bit corresponds to one word. If at least one validity bit is set, the block is valid, and the block status bits indicate a valid status. If all validity bits are reset, the block is in a non-valid state, and the block status bits are irrelevant. The block status bits are referred to as the sharing and modifying bits. The sharing bit indicates whether the block is shared by more than one processor or is present in more than one cache. The modifying bit indicates whether the block is modified relative to main memory. The two bits are independent, and a valid block can be assigned a status in the following way: Block status bits Value (shared, modified) Meaning exclusive not modified oexclusive modified shared not modified shared modified

Furthermore, it should be remembered that non-cacheable data are data variables that are not cached. A cacheable processor bus access is indicated at the ICU, ASTC inputs. In this access, the cache memory is not searched for the requested data. A memory access is indicated to read or write the data from or to the memory. For this data, a cache memory is used. No block is allocated in memory. Non-cacheable data can be allocated on a per-access basis. Usually, the ASTC inputs are coupled to the processor's MMU programmable (MPGM) outputs. In this case, the non-cacheable data is allocated on an MMU page basis. The non-cacheable data must be placed in a location that the system has designated as non-cacheable. One way to solve the data consistency problem is to designate shared variables as non-cacheable.

A processor bus memory access can also be specified as a locking access. This is done by setting the ICU *LOCK input signal. Locking accesses are controlled by the Modb register and can be referred to as cacheable and non-cacheable accesses.

In a multiprocessor environment, locking variables can be used for synchronization and synchronized communication. These variables are accessed in a synchronized manner. They can be written by only one processor at any given time. A detailed description of the ICU support for locking accesses is given below.

The ICU supports flexible write-through and copy-back write functions. The write functions can be allocated either globally or on a per-access basis. The Moda register controls the global write function. It can specify the flexible write-through or copy-back function. The ASTC inputs define the write function on a per-access basis. The access can be allocated as exclusive write-through, exclusive copy-back, or shared access. If a cache hit conflicts between the sharing bit allocation made for the ASTC inputs and the shared bit allocation made for the ASTC inputs, the ICU will resolve the conflict. and the block status sharing bit in the cache memory, the write operation is controlled by the value of a processor sharing bit control signal (PSBC) in the Modb register. If PSBC is 0, the bit used with shared block status is not affected and the write function is determined according to the block status. If PSBC is 1, the bit used with shared block status is assigned according to the ASTC inputs and the write function is determined accordingly.

In the case of a shared write access, a write-through or write broadcast access to the memory bus is always performed. In this case, a write sharing hit control (WSHC) field in the Modb register, and not the write function field, controls the ICU operation.

In a multiprocessor cache environment, the write-through feature is less problematic than the copy-back feature. If the write-through feature is used, the memory always contains an updated version of the data. The write-through access can also be used by other caches to invalidate their own copy.

The processor bus cache instructions can be used by the system to control the cache in a multiprocessor environment. Invalidation instructions can be used to invalidate stale data. Other instructions can be used in more complex software-controlled multiprocessor cache environments to read and write block status and memory updates to and from the memory bus and to output cached data to the memory bus.

Another multiprocessor support feature of the ICU is the "bus monitoring". The new ICU is able to To monitor memory bus addresses and check if they match an address in the tag array. This is done with transparency to the processor bus cache memory accesses. The bus read monitor enable information in the Modb register controls (enables or disables) the bus monitoring capability for memory bus read accesses. The bus read monitor enable information in the Modb register performs the same function for memory bus write accesses. When enabled, the bus is monitored only when the ICU is the bus slave. In the event of an address match, the ICU performs operations as controlled by the read match control and write match control information in the Modb register.

In case of a memory bus read match, the *HIT signal is asserted by the ICU. The bit used with shared block state is set because the block is potentially claimed by another cache. The modb register controls the data intervention operation and the block state modification bit mapping. The options are: no data intervention, data intervention (modified bit unchanged), and data intervention (modified bit reset).

When data intervention is disabled, if there is a match with the memory bus read content read by another master, the ICU asserts the *HIT signal but does not drive the data. The block status modified information is not changed. When data intervention is enabled, if there is a match with the memory bus read content read by another master and the block is modified, the ICU asserts the *DI output signal and drives the required data on the memory bus. The block status modified bit is either not changed or is reset.

In case of a match on a read-to-modify access, the corresponding word is invalidated by the slave caches. In all other respects, the cache operation is similar to the case of a match on a regular read access.

For memory bus burst mode accesses, the initial addresses are latched. The address is incremented and checked in the slave cache for each individual transfer.

The slave cache operation in case of a match is similar to the single address match.

Bus monitoring for reading is essential to supporting the data consistency ownership schemes, which are described in detail below.

The data intervention option is required by some of the ownership schemes. In these schemes, the memory must be designed to support it. The *DI signal is precharged by the master cache during the first cycle of the access. An external pull-up resistor must be connected to the *DI signal to hold the precharged HIGH value. The *DI signal is discharged by the slave caches if the data intervention operation is performed. In this case, the data must not be supplied from the memory and the read access must be cleared in the memory. Note that the *DI output signal is valid for two cycles after the address appears on the memory bus. The memory may not respond during these cycles.

In case of a match on a memory bus write or write broadcast signal, the *HIT signal is asserted.

For burst mode write accesses, the starting address is latched. The address is incremented for each individual data transfer and checked in the slave cache. In case of a match, the slave cache operation is similar to the single access match.

Write bus monitoring is essential to supporting most data consistency schemes.

The following describes how the bits used with shared block status are assigned.

The bit used with shared block status can be assigned either by software or hardware control. Under software control, the processor can assign the shared bit using the ASTC input signals. These input signals define the allocation of the shared bit on an access-by-access basis. The access can be assigned as exclusive write-through access, exclusive copy-back access, or shared access. Typically, the ASTC input signals are coupled to the MPGM signals, which are controlled according to the user-programmable MMU bits. The shared and exclusive variables are placed on shared or exclusive pages, and the user-programmable bits for the pages are assigned accordingly. Depending on the state of the PSBC bit of the Modb register (mentioned earlier), the common bit can be modified for every processor access (PSBC=1) or only in case of a cache miss (PSBC=0).

In hardware control, the shared bit can be set by using the *HIT signal or by using special purpose logic for the memory bus and the write block status memory bus cache instruction *HITSiignal usage in read and write accesses is controlled by an external sharing bit control (ESBC) field of the Modb register.

In the case where a master cache uses the *HIT signal, it precharges it during the first cycle of the memory bus access. Then the *HIT signal is tripled. An external pull-up resistor must be applied to the *HIT signal to keep the precharged HIGH value. The slave cache discharges the signal if a match is found in the tag buffer. The *HIT signal is latched by the master cache when *MRDY is asserted or two cycles after the memory bus address cycle, whichever is later. If the *HIT signal is asserted, then the variable is also present in other caches and the block is assigned a common state. If the *HIT signal is not asserted, the variable is not present in any cache and the block is assigned an exclusive status.

This technique is used in some of the ownership schemes. It guarantees that the shared state reflects the exact state of the variable. It is shared only if it is present in another cache. Note that there is a performance cost associated with using the *HIT signal. The ICU must wait two cycles for all other caches to respond. Also, a special internal cache array access is required if the shared bit needs to be modified. Before choosing this option, one should be aware of this versus the benefits.

The previously described write block status memory bus cache instruction can be used to Block status to assign a specific status to the bit used. This instruction can be used by external logic to flexibly control the common bit.

In the event of a conflict occurring between the three methods mentioned during the allocation of the common block, in the preferred embodiment of the invention the operation is carried out according to the following priority:

1. Block state write instruction.

2. *HIT input signal control.

3. ASTC input signal control.

For example, if the block is designated as exclusive by the ASTC inputs, but a memory bus access is required, use of the *HIT input is enabled and the block is indicated to be exclusive. The block state write instruction is also used during the memory access and is assigned a shared state. The block ends in the shared state.

The various shared block allocation schemes and their combinations are used to implement all multiprocessor cache memory systems supported by the novel ICU.

The following describes the ICU operation in the case that a write hit occurs on a shared block.

When a write access is directed to a shared block and hits it in the cache, a special operation must be performed on the memory bus. The other caches in the system must be aware of the fact that a shared data variable has been modified. Their copy must either be invalidated or updated to reflect the current version of the shared variable. Main memory may be written to or not. The block state of the master cache is affected accordingly. The ICU operation for a write hit on a shared block is controlled by a Write Share Hit Control (WSHC) field in the Modb register. One coding scheme is as follows: WSHC Value Master Cache Operation Slave Cache Operation New Block State Write-Through Write Broadcast Invalidate Update Exclusive Modified Unmodified Shared

When WSHC = 00, the ICU writes through every write hit to a shared block. The memory is updated and other caches are invalidated. The block is assigned the exclusive unmodified status. Since the block becomes exclusive, further writes for the same block can only be written to the cache. This scheme is effective if a shared variable is written many times by a particular processor before it is needed by other processors.

If WSHC = 1, the ICU uses a write broadcast transaction on the memory bus. The memory is not updated and the other caches are invalidated. The block is assigned the exclusive modified status. Since the block becomes exclusive, further writes for the same block can only be written to the cache. Since the memory is not updated, the modified bit is set. This data intervention option should be enabled to support the most current value when another master attempts to read this block.

If WSHC = 10, the ICU writes out every write hit to a shared block. The memory is updated, and other caches are also updated. If ESBC is not enabled for writes, the block is assigned to the shared unmodified state. If ESBC is enabled for writes, the block is assigned to the exclusive unmodified or shared unmodified state according to the *HIT input. In this scheme, all caches are kept synchronized at the expense of the memory bus write transaction for each shared block write. It is effective if a shared variable is not written many times by a particular processor before it is requested by other processors.

If WSHC = 11, the ICU writes each write hit to a shared block in a broadcast manner. The memory is not updated and other caches are updated. If ESBC is not enabled for writes, the block is assigned the shared modified state. If ESBC is enabled for writes, the block is assigned the exclusive modified or shared modified state according to the *HIT input. In this scheme, all caches are kept synchronized at the expense of the memory bus write transaction. for each write to a shared block. It is effective if a shared variable is not written many times by a particular processor before it is requested by other processors. Since the memory is not updated, the modified bit is set. The data intervention option should be enabled to support the most recent value when another master tries to read this block.

The WSHC options are used for the different ownership schemes. They can also be used for other multiprocessor cache memory systems.

The ICU memory bus operation for a copyback write miss on write map is controlled by a write miss memory access control (WMMC) bit in the Modb register. It has no effect on write-through accesses or copyback accesses without write map. If WMMC = 1, the ICU uses a read access to the memory bus to fetch the requested sub-block, followed by a cache write access. This access is treated as a separate cache write operation. It always hits and is written to cache. If the block is shared, a memory bus operation is performed according to the WSHC field of the Modb register. If WMMC = 0, the read-to-modify transaction on the memory bus is used to fetch the requested sub-block. Slave caches invalidate their copy of the block in case of a match. The write is performed to the cache without any memory bus operation.

The WMMC options are used for the different ownership schemes. They can also be used for other multiprocessor cache memory systems.

The memory bus cache instructions are issued by a special logic on the memory bus. They allow flexible control of the cache memory. Cached data can be invalidated, read and written. The block status can be read and written. A detailed description of the memory bus cache instructions is already given above.

In the multiprocessor environment, the special control logic must be able to route the instruction to the correct ICU. The logic can be designed for any multiprocessor system required. In particular, this method must be used in systems without a common bus (crossbar circuit or multiple bus configurations). In these systems, the bus monitoring function is not effective and thus special logic should monitor the memory accesses and issue commands to the different ICUs accordingly. The control logic can also be designed to implement a specific multiprocessor scheme that is not directly supported by the ICU.

There are many possibilities for multiprocessor cache memory organizations. The ICU is designed to support various shared memory multiprocessor cache organizations. The ICU can also be used in a non-shared memory organization, but does not include any special hardware support for these systems. The following detailed description explains the main shared memory organizations supported by the ICU. Variations, combinations, or systems other than those described are also possible.

The main shared storage organizations supported are the following: Organizations with software-controlled cache, with write-through cache, with copy-back cache with shared write-through variables, with ownership schemes, and shared memory with non-shared bus.

For software-controlled caches, all multiprocessor communication and synchronization is under software control. Cache consistency is maintained by software. This can be done using a combination of non-cacheable variables, locking operations (described in detail below), and the use of cache instructions (e.g., invalidate). Shared variables can either be allocated as non-cacheable or invalidated from the corresponding caches if they can be modified by another processor. Locking operations are used for synchronization. Shared buffers or mailboxes are used for communication.

This is a very flexible scheme with no special hardware requirements or restrictions. It can be used successfully in systems with a low level of sharing. However, if the level of sharing is high, this scheme can potentially have a massive impact on system performance. Many variables cannot be cached, or it requires a lot of effort to maintain cache consistency. Another disadvantage of this scheme is that the cache is not transparent to the software, and the information to which the variables must be shared must be known. Software control can be used in combination with any of the other multiprocessor schemes.

There are no special requirements for programmable options for this configuration. The Modb register can be programmed to .

For write-through caches, processors share the same bus and memory, and all caches use the write-through feature. A master cache communicates all processor write information to the memory bus. Cache consistency is maintained by performing bus sensing for writes. Each write on the shared memory bus is checked in all slave caches. If a match is found, the corresponding address is invalidated. This is a simple data consistency scheme. Its main disadvantage is that each write causes a memory bus operation. This can significantly reduce performance. Memory bus usage can be much higher, so only a small number of processors can be accommodated in the system. The write buffer can help reduce these adverse effects.

For this option, all blocks should be designated as exclusive write-through blocks, the write function should be programmed as a write-through function, the bus monitor should be enabled for write accesses, and the modb register should specify word invalidation.

For copyback caches with shared write-through variables, the processors share the same bus and memory, and the caches use a flexible write function. The exclusive variables use a copyback option (placed on a page designated for exclusive copyback). It is the responsibility of the system to ensure that only the variables that used exclusively by a single processor are designated for exclusive copyback. Note that if process migration is allowed, an exclusive variable must be invalidated in the cache of the old processor.

The shared variables use a write-through option (placed on a page designated for exclusive write-through). It is the responsibility of the system to assign this status to any variable that could be shared (including sharing with I/O, or processors without caches). Some variables, such as I/O, have yet to be designated as non-cacheable. A bus monitor for write schemes (similar to that described for the write-through caches) is used to maintain data consistency. In the event of a match, slave caches invalidate their copy. A possible variation with better performance is for slave caches to update their copy rather than invalidate it.

This scheme is based on the assumption that all shared variables are known and placed on write-through or shared pages. If this is the case, better performance can be achieved compared to the write-through scheme. However, if the amount of sharing is high, the penalties of write-through operations of the shared data become more severe and performance degrades.

In addition to the assignments for the shared and exclusive variables, the bus monitor for write accesses should be enabled and the Modb register should specify the invalidation of words. If the slave memory update variation is desired, the Modb register should be programmed accordingly.

The following are the ownership schemes. These schemes are based on shared memory and shared bus organizations with bus monitoring to maintain data consistency. The basic principle of ownership schemes is that a variable is owned by only one cache. The owner cache contains the most recent version of the variable and is responsible for maintaining its consistency. If a variable is not owned by any cache, the cache contains an updated value. In all ownership schemes, a variable can be in one of several (maximum 5) states in a cache. The five possible states (block states) supported by the preferred embodiment of the ICU are as follows:

1. Exclusive writing

2. Exclusive copying back

3. Used together and modified

4. Shared modified

5. Not valid

Each ownership scheme is controlled by a hardware-implemented state machine that controls the state transitions. The different ownership schemes require different operations for the cases: match read, match write, hit write, and miss write. Thus, different levels of hardware support are required in the caches and in the system in general.

None of the ownership schemes require software control of the cache memory. They allow higher performance at the expense of more complicated hardware requirements.

There are six ownership schemes that are well known to the expert:

1. Write Once

2. Berkeley

3. Illinois

4. Firefly

5. Dragon

6. Futurebus

Another scheme, known as the Synapse scheme, is very similar to the Write Once scheme, but is based on a single bit tag present for each cache block in main memory. This scheme is not directly supported by the ICU, but it can be implemented using the Write Once options and some external logic.

Although the details of the various ownership schemes are widely known and described in publications, for the sake of completeness and to facilitate the explanation of the manner in which these schemes are supported by the ICU, the main features of each scheme are explained below.

All ownership schemes and possibly other schemes that may occur are directly supported by the ICU. This is done by selecting the required programmable options. For all ownership schemes, the write function is programmed to be flexible. Most of the write accesses can use a copyback function. Bus monitoring is enabled for both reading and writing. The Modb register with the various control fields already defined can be used to implement the various ownership schemes.

The write-once scheme defines only the following states: exclusive unmodified, exclusive modified, shared and unmodified, and invalid. The shared and modified state is not used. The basic principle of this scheme is that any write that hits the cache the first time (write to shared page) causes a write-through. Then the block is designated as exclusive modified, and further writes can only be made to the cache. The slave caches invalidate their own copy of the block. A copy-back write to an exclusive block sets the modified bit. An exclusive modified block is owned by the cache, and data intervention is used in the event that another cache attempts to read it. (Furthermore, the cache is updated, and the block is then designated as shared unmodified). In this scheme, all processor accesses should be indicated as shared. Note that an exclusive block state takes precedence over the shared indication by the ASTC inputs.

In the Berkeley scheme, only the following states are defined: exclusive modified, shared and unmodified, shared and modified, and invalid. The exclusive unmodified state is not used. A cache that contains the exclusively modified or the shared and modified block owns it. In case of a read miss, the block is reported as shared and unmodified. In case of a write hit on a shared block, a broadcast write is performed and the block is reported as exclusively modified. Other caches invalidate their copy of the block. In case of a read match, a data intervention is issued by the owner. For this scheme, all processor accesses should be reported as shared.

In the Illinois scheme, only the following states are defined: exclusive unmodified, exclusive modified, shared and unmodified, and invalid. The shared and modified state is not used. A cache that contains the exclusive modified block owns it. In the case of a read miss, the block is declared shared and unmodified or exclusive and unmodified depending on the *HIT input. In the case of a write hit on a shared block, a broadcast write is performed and the block is declared exclusively modified. Other caches invalidate their copy of the block. In the case of a read match, a data intervention is performed by the owner. Note that the data intervention operation is different from the original definition in the Illinois scheme, but the end results are the same. In the original definition, all caches that contain a copy of the requested data attempt to intervene. In this case, data intervention is only performed if the block is modified. If the block is shared and unmodified, the data is supplied from memory. For this scheme, the processor access sharing bit mapping is irrelevant, since the *HIT signal is used for this purpose.

In the Firefly scheme, only the following states are defined: exclusive unmodified, exclusive modified, shared and unmodified, and invalid. The shared and modified state is not used. A cache that contains the exclusive modified block is its owner. In case of a miss in the When read, the block is declared as shared and unmodified or exclusive and unmodified depending on the *HIT input. In the case of a write hit on a shared block, a write-through operation is performed and the block is declared as shared and unmodified or exclusively modified according to the *HIT input. In the case of a read match, the owner performs a data intervention. Note that the data intervention operation is different from the original definition in the Firefly scheme, but the end results are the same. In the original definition, all caches that contain a copy of the requested data attempt to intervene. In this case, data intervention is performed only if the block is modified. If the block is shared and unmodified, the data is supplied from memory. For this scheme, the processor access sharing bit mapping is irrelevant because the *HIT signal is used for this purpose.

The Dragon scheme uses all five block state possibilities. In the case of a read miss, the block is declared as shared and unmodified or exclusive and unmodified depending on the *HIT input. In the case of a write hit on a shared block, a broadcast write is performed (memory is not updated), and the block is declared as shared and unmodified or exclusive and unmodified depending on the *HIT input. Other caches update their copy of the block. In the case of a read match, the owner performs data intervention. For this scheme, the processor access sharing bit mapping is irrelevant since the *HIT signal is used for that purpose.

The Futurebus scheme uses all five block state possibilities. This scheme is a flexible scheme that allows (with some slight modifications) the implementation of any other ownership scheme. The cache operations in the case of read and write matches, as well as write hits and read and write misses, are defined with enough flexibility to implement the various ownership schemes. Furthermore, the use of the *HIT signal is optional. The Futurebus scheme is fully supported by the flexibility of the ICU. The ICU has more flexibility than the Futurebus scheme requires, so some of the limitations, such as memory refreshing during data intervention and broadcast write support, are eliminated. For this scheme, processor access sharing bit mapping can be done either by software mapping or by using the *HIT signal.

Finally, shared memory without shared bus organizations will be discussed. First, it should be noted that the bus monitoring function is only useful in a multiprocessor organization with a shared bus. Other shared memory organizations that include multiple buses or a crossbar switch are also supported by the ICU. These organizations are required when the shared bus is a bottleneck in the system. In this case, they allow for a larger number of processors and better performance.

The basic support for these organizations is provided by the memory bus cache instructions. A detailed description of the memory bus cache instructions has already been given. An external control logic is required to monitor the memory accesses and to route the cache memory instructions to the correct ICU. This logic can be customized according to the specific system organization. It should be able to monitor all main memory accesses. (This function can be placed in the memory controller.) Then, according to the global information, a memory bus cache instruction can be routed to the correct cache memory. The details of such an implementation are system dependent and not part of the invention, and many variations are possible. To illustrate ICU support for these organizations, some basic functions are now described.

When a cache attempts to read a block from memory, the control logic can use the block state write instruction to designate the block as shared or exclusive. If the updated version of the required variable is not in memory but in one of the caches, "Commit Word," "Commit Word If Modified," or "Commit Block If Modified" can be used to receive the updated version.

When a shared variable present in some of the caches is written by one of the processors, the ICU can be programmed to either write through or broadcast the write information. An invalidate word, invalidate block, or write to cache instruction can be used to invalidate or update the copy of the other caches.

The block state of each cache block can be read or written whenever required using the read block state and write block state instructions. This can be done by the control logic to obtain information about cache contents or to determine the block state.

Some of the programmable options can also be used for these organizations to specify the ICU operation in the event of a common hit, read or write miss. Bus monitoring can be used if special logic is provided to perform read and write operations on the ICU memory bus, rather than memory bus cache instructions.

In a multiple-bus organization, a combination of the bus monitor and the memory bus cache instruction may be used. The bus monitor may cover the data consistency of the caches sharing the same bus. Special logic is required to transfer the relevant accesses or issue a memory bus instruction to the corresponding caches to achieve inter-bus data consistency, i.e., an operation on one bus that affects the data in a cache located on another bus. The design of this special logic is within the skill of the person skilled in the art and is outside the scope of the invention.

To complete the description of the novel ICU, the locking function is described in detail. In a more general sense than in the context of the ICU, it is known to those skilled in the art that locking variables are used for semaphores and other synchronization variables in a multiprocessor or general-purpose environment. Synchronization variables can also be used as protection keys for a shared memory area. Accesses to the locking variables should be synchronized. At any given time, only a single processor may access locking variables. Each reading of locking variables should result in the return of the most current value of the variable.

To support locking variable accesses, the processor should include some type of atomic read-modify-write operation. This allows a variable to be checked and manipulated atomically by one processor, while no other processor can interfere. In a system that includes cache memory, locking variables cause a special problem because their access should be synchronized independently of the cache memory.

A simple solution to this problem is to designate all locking variables as non-cacheable. In this case, caching of locking variables is not allowed and all locking variable accesses are forwarded to memory. This approach is used in most of the known cache memory systems. The main disadvantage is the lower performance and increased bus overhead caused by locking variable accesses to memory. As the number of locking variable accesses increases, the performance impact can be significant.

The novel ICU and the locking function described below, which is novel in itself, allow locking variables to be cached. This allows better performance and lower bus usage. Most of the locking variable accesses are faster and do not appear on the memory bus because the access occurs only in the cache memory. The scheme is simple and can be implemented on the single-chip ICU.

There are various approaches to ensuring synchronization associated with locking variables. The processor used in the exemplary embodiment of the invention contains the These are explained in the copending application dealing with the processor, which is incorporated herein, and are in particular the LOADSET, LOADL and STOREL instructions, the LK bit in the current processor status register and the *LOCK output signal. The ICU implements two schemes for handling locking variables. The desired scheme can be selected by programming the cache lock enable (CILE) bit of the Modb register.

When the CILE bit is LOW, the cache lock variables are disabled. Lock variables (*LOCK bit asserted) are treated as non- cacheable accesses. The cache is not checked for a hit, and the access is communicated to the memory bus with the lock indication (*MLOCK asserted). With this option, the handling of the lock variables is under the control of the memory. The memory must disable any access to the lock variable while the *MLOCK signal is asserted. A LOADSET instruction can be used to test and set the lock variable in the memory.

When the CILE BIT is HIGH, the locking variable caching feature is enabled. This is a special feature built into the ICU to allow more efficient handling of locking variables. It is compatible with the processor and takes advantage of the various locking primitives of the processor.

The locked read and write operations (*LOCK is asserted) are handled in a special way. A locked read operation (which is used by the processor for the LOADL and LOADSET instructions) is treated as a miss if it does not hit in a shared block. A reload operation is started on the memory address bus, asserting *MLOCK. This read data is stored in the cache and the block is designated as shared. On a shared block hit, the data is fed into the cache without memory address bus access.

A locked write operation is treated differently for the processor STOREL instruction than the LOADSET instruction write. According to the state of the *LOCK input signal in the cycle preceding the write cycle, the ICU can distinguish between two types of locked writes. If the *LOCK bit is set, it means that the locked write is the LOADSET instruction write. If it is not set, it is the STOREL instruction write.

In case of a locked STOREL write, the ICU initiates a write-through to memory. In case of a lock hit, the block is invalidated.

In the case of a locked LOADSET write, the data is written to the cache memory. Only if the LOADSET instruction's read access generated a miss will the data be written to memory. This ensures that memory is only written to the first time the locked variable is read.

In both cases, the *MLOCK output is asserted during the memory write operation. All other caches invalidate their own copy when another master performs a write while *MLOCK is asserted.

There is a special way in which the processor should access locking variables if the locking feature is enabled. (Variations may be possible.) The LOADSET instruction is used to test and set a locking variable. If the value of the variable is 0, it is not active and can be used by the processor (or process). Note that as a result of the LOADSET instruction, a sub-block is loaded into the cache. This sub-block contains the locking variable (word) and possibly some other words if the sub-block size is greater than one. The user can take advantage of this fact and place relevant information in the same sub-block of the locked variables.

If the value of the variable is 1, it is active and it (or the area it protects) cannot be used. The program can either use a busy-wait scheme and continue testing until the variable is free, or perform other operations (or tasks) and test the variable later. Testing of the variable is performed using the LOADSET instruction.

The master ICU uses the memory address bus only for the first LOADSET instruction. The variable is read from memory and placed in the cache with the shared block state. The first LOADSET write is also written to memory. The next LOADSET instructions (in most cases) hit the cache and do not use the memory address bus. In the event of a match on a write when *MLOCK is in effect, other caches invalidate their own copy.

The STOREL instruction is used to release a locked variable. The STOREL instruction is followed by from the master cache, a write access with *MLOCK asserted is initiated on the memory address bus, and the variable is invalidated in all other caches. If the variable is still in the master cache, it is also invalidated. This is done to ensure that the next time the processor accesses that variable, it is read from memory to obtain the most current value. Note that while the master cache uses a locking variable, if another processor attempts to test the same variable for the first time (using LOADSET), the LOADSET write is performed on the memory bus and the variables in all other caches (including the master cache) are invalidated.

All other processors that have been waiting for the variable must access the memory when they next test it. Only the one cache that wins the bus ranking gets the free locked variable.

The main advantage of using the locking function is better performance and less bus overhead. In a multiprocessor system with many locking variable accesses, a significant performance improvement can be achieved by using the locking function. Another advantage is that the memory controller can treat locking accesses as regular accesses.

It should also be noted that the locking function can also be implemented in devices other than the RISC/SIP processor described in the relevant copending application cited here.

The present description covers the novel ICU itself, together with the novel organization of the ICU for a flexible design for a cache memory system, a novel cache memory locking function, a novel and flexible multiprocessor support scheme, and a preload scheme for integrated cache memories. The details of these have been explained in terms of the function, internal registers, inputs and outputs, scan instruction sets, data formats, programmability, types of systems supported and other aspects of the novel ICU.

Claims (30)

1. Architecture for integrated cache memory units (“ICU”) for a computer system comprising at least one central processing unit (“CPU”) (110), a processor bus device (120,121) for communication between the CPU (110) and the ICU (101,102), and a memory bus device (175) for communication between a memory (190) and the ICU (101,102), where the ICU (101,102) has: a processor bus unit (301-303) coupled to the processor bus device (120,121) for controlling an ICU/processor bus interface; a memory bus unit (304-307) coupled to the memory bus device (175) for controlling an ICU/memory bus interface; and a cache memory unit (310-316) coupled to both the processor bus unit (301-303) and the memory bus unit (304-307) for performing caching functions, the cache memory unit comprising a tag array device (311), a valid array device (312) and an associated memory array device (310) organized as a 2n-way associative cache memory, where n is an integer greater than or equal to zero, characterized in that the cache memory unit (310-316) further comprises a set of special registers (315) coupled to a cache address bus and a cache data bus, the address bus and the data bus being connected to the processor bus unit (301-303) and to the memory bus unit (304-307), and at least one of the registers (315) is a programmable register by means of which the user selects certain ICU options and procedures. 2. The ICU architecture of claim 1, wherein the memory array device (310) stores cached data and instruction signals and is organized as a set of blocks, wherein each block corresponds to a certain number of cache words. 3. ICU architecture according to claim 2, wherein for each block at least one associated tag is stored in the tag array device (311). 4. ICU architecture according to claim 2 or claim 3, wherein for each block at least one associated validity bit is stored in the valid array device (312). 5. ICU architecture according to one of claims 1-4, wherein the processor bus unit (301-303) further comprises: (a) a first address incrementing device (301) coupled to the processor bus device (120,121) and the cache memory unit (310-316) for receiving, temporarily storing and incrementing address signals input from the processor bus device, and for outputting address signals to the cache memory unit to facilitate cache memory accesses; (b) a data shifter (302) coupled to the processor bus device (120,121) and the cache memory unit (310-316) for aligning data signals input from the processor device and for aligning data signals output by the cache memory unit for transmission to the processor (110); and (c) a processor bus unit control means (303) for synchronizing and controlling the operation of the first address incrementing means, the data shifting means and the cache memory unit. 6. ICU architecture according to one of claims 1-5, wherein the memory bus unit (304-307) further comprises: (a) a selectively activated write buffer (304) for buffering address and data signals transmitted between the memory bus device (175) and the cache memory unit (310-316); (b) a memory address logic device (305) coupled to the memory bus device (175), the write buffer (304) and the cache memory unit (310-316) for temporarily storing and incrementing memory bus addresses entered via the memory bus device and for temporarily storing and incrementing addresses for cache memory read operations initiated by the cache memory unit; (c) a memory read buffer device (306) coupled to the memory bus device (175), the write buffer (304) and the cache memory unit (310-316) for buffering the data from the memory bus device until the cache memory unit is to update and is available to support both prefetch and read operations; and (d) a memory bus unit control means (307) for synchronizing and controlling the operation of the write buffer, the memory address logic means, the memory read buffer means, and the cache memory unit. 7. The ICU architecture of claim 6, wherein the write buffer further comprises an address buffer and a data buffer 8. ICU architecture according to one of claims 2-4, wherein the cache memory unit (310-316) further comprises: (a) block status array means (313) coupled to the cache data bus for storing an indication of the status of each block as modified, shared or locked; and (b) a cache memory unit controller (316) coupled to the processor bus controller (303) and the memory bus controller (307) for synchronizing and controlling operations of the cache memory unit (310-316), the processor bus unit (301-303) and the memory bus unit (304-307). 9. ICU architecture according to claim 8, wherein the control device (316) for the cache memory unit further comprises a logic device coupled to the cache memory unit address bus and the tag array (311) for comparing of addresses carried on the cache memory unit address bus with tags located in the tag array. 10. The ICU architecture of claim 8 or claim 91, wherein the cache memory unit controller (316) further comprises logic means coupled to the valid array (312) for determining whether a particular cached word is valid during cache memory access. 11. ICU architecture according to one of claims 8-10, wherein the cache memory unit controller (316) is further operable to generate hit signals for valid cache memory accesses and to maintain and update data stored in the set of special registers (315) and the block status array (313). 12. The ICU architecture of claim 10, further comprising a least recently used (LRU) array device (314) for storing LRU bits each time the cache memory unit uses an LRU replacement algorithm. 13. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for disabling a read-through option. 14. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for enabling single-access prefetch. 15. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for disabling wrap-around addressing. 16. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for controlling the operation of the ICU in the event of a single access miss. 17. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit to control the operation of the ICU when the processor completes a burst mode read request. 18. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for enabling a prefetch option in the burst mode. 19. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for specifying and varying a sub-block size. 20. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for selecting a write allocation option. 21. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for selecting write policy options on a global basis. 22. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for specifying a block replacement policy. 23. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit for selecting a 2n-way associative cache memory organization. 24. ICU architecture according to one of the preceding claims, wherein the programmable register contains at least one bit to specify a cache operation as an instruction cache in a first mode of operation and to specify a cache operation as a data cache in a second mode of operation. 25. ICU architecture according to one of the preceding claims, further comprising means for supporting user-defined write-through and copy-back write policies on a per-access flexible basis. 26. ICU architecture according to one of the preceding claims, wherein the CPU (110) is a simplified instruction processor that supports burst protocols and pipeline protocols and wherein the ICU (101,102) further comprises means for supporting the protocols. 27. ICU architecture according to one of the preceding claims, further comprising fault tolerance support means, including means for generating and checking byte parity. 28. The ICU architecture of claim 27, wherein the fault tolerance support means further comprises means for operating the ICU (101,102) in a cache master and a cache slave mode. 29. ICU architecture according to one of the preceding claims, in which instructions and data are preloaded into the cache memory (310) before the processor (110) begins executing the program. 30. ICU architecture according to one of the preceding claims, wherein the set of special registers further comprises: (a) a chip select mapping register; (b) an instruction register; (c) an address operand register; (d) a counting register; (e) an error register; and/or (f) a status register.